CN115349107B

CN115349107B - Array substrate and liquid crystal display panel

Info

Publication number: CN115349107B
Application number: CN202180000104.0A
Authority: CN
Inventors: 李鸿鹏; 梁蓬霞; 方正; 石戈; 崔贤植; 孙艳六; 韩佳慧; 杨松; 刘玉杰
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2024-01-12
Anticipated expiration: 2041-01-29
Also published as: WO2022160282A1; CN115349107A; US20230090555A1; US11899320B2; EP4141530A1; EP4141530A4

Abstract

An array substrate and a liquid crystal display panel, the array substrate comprises a substrate (101), a first electrode (1081), an insulating medium layer (107) and a second electrode (1082) which are sequentially laminated; the second electrode (1082) is provided with at least one hollow hole (300, 301), and the hollow hole (300, 301) is in a convex polygon, a round shape or an oval shape, so that liquid crystal in the liquid crystal display panel can be driven to fall towards a plurality of different directions, and the multi-domain characteristic is displayed.

Description

Array substrate and liquid crystal display panel

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate and a liquid crystal display panel.

Background

The ADS (Advanced Super Dimension Switch, advanced super-dimensional field switching technology) display panel includes an array substrate and a color film substrate disposed opposite to each other, and a liquid crystal layer interposed between the array substrate and the color film substrate. The array substrate generally comprises a substrate, a plate electrode and a slit electrode which are sequentially stacked, wherein a fringe electric field can be generated between the slit electrode and the plate electrode; the liquid crystal in the liquid crystal layer is deflected by the drive of the fringe electric field.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure aims to overcome the shortcomings of the prior art, and provide an array substrate and a liquid crystal display panel, and improve color cast of the liquid crystal display panel.

According to one aspect of the present disclosure, there is provided an array substrate including a substrate, a first electrode, an insulating medium layer, and a second electrode stacked in this order; the second electrode is provided with at least one hollow hole, and the hollow hole is in a convex polygon, a round shape or an oval shape.

According to one embodiment of the disclosure, the hollowed-out hole is regular polygon or circular.

According to one embodiment of the present disclosure, the hollowed-out hole is circular, and the diameter of the hollowed-out hole is in the range of 10-14 microns.

According to one embodiment of the disclosure, the hollowed-out hole is square, and a dimension of one edge of the hollowed-out hole is in a range of 9-13 micrometers.

According to one embodiment of the disclosure, the hollow holes include first hollow holes, and a distance between two adjacent first hollow holes is in a range of 2-4 micrometers.

According to one embodiment of the present disclosure, the first hollow holes are arranged in at least one hollow hole row, and the hollow hole row includes a plurality of first hollow holes that are sequentially adjacent and are linearly arranged along a first direction; the first direction is parallel to the plane of the substrate.

According to one embodiment of the present disclosure, the first hollow holes are arranged into at least one hollow hole row, and the hollow hole row includes a plurality of first hollow holes that are sequentially adjacent and are linearly arranged along the second direction; the second directions are parallel to the plane of the substrate base plate and are intersected with the first direction.

According to one embodiment of the present disclosure, the first direction and the second direction have an angle of 90 ° or 60 °.

According to one embodiment of the disclosure, the hollowed-out hole is square; the included angle between one edge of the hollowed-out hole and the first direction is in the range of 0-10 degrees.

According to one embodiment of the disclosure, the first direction and the second direction have an angle of 90 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 11 microns, and the distance between the centers of two adjacent first hollowed holes is 14 microns.

According to one embodiment of the disclosure, the first direction and the second direction have an angle of 90 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 9 microns, and the distance between the centers of two adjacent first hollowed holes is 11 microns.

According to one embodiment of the disclosure, the first direction and the second direction have an included angle of 60 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 10 microns, and the distance between the centers of two adjacent first hollowed holes is 13 microns.

According to one embodiment of the disclosure, the first direction and the second direction have an angle of 90 °; the hollowed-out hole is circular; the diameter of each hollowed hole is 11 microns, and the distance between the centers of two adjacent first hollowed holes is 14 microns.

According to one embodiment of the disclosure, the first direction and the second direction have an included angle of 60 °; the hollowed-out hole is circular; the diameter of each hollowed hole is 13 microns, and the distance between the centers of two adjacent first hollowed holes is 16 microns.

According to one embodiment of the disclosure, the hollow hole further comprises a second hollow hole, and the second hollow hole is arranged close to the outer side edge of the second electrode; the distance between the second hollowed-out hole and the adjacent first hollowed-out hole is smaller than the distance between the adjacent two first hollowed-out holes.

According to one embodiment of the present disclosure, the first hollowed-out holes are arranged into at least one hollowed-out hole row and at least one hollowed-out hole column; the hollowed-out hole row comprises a plurality of first hollowed-out holes which are sequentially adjacent and are linearly arranged along a first direction; the hollowed-out hole columns comprise a plurality of first hollowed-out holes which are adjacent in sequence and are arranged in a straight line along a second direction; the first direction and the second direction are parallel to the plane of the substrate base plate and are intersected;

Any one of the second hollow holes is linearly arranged with each first hollow hole in one hollow hole row along the first direction, or is linearly arranged with each first hollow hole in one hollow hole column along the second direction.

According to one embodiment of the disclosure, the first electrode and the second electrode are both transparent electrodes.

According to another aspect of the present disclosure, there is provided a liquid crystal display panel including:

the array substrate;

the color film substrate and the array substrate are arranged in a box-to-box manner;

the liquid crystal layer is clamped between the array substrate and the color film substrate.

According to one embodiment of the present disclosure, the liquid crystal in the liquid crystal layer is a negative liquid crystal.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic cross-sectional structure of an array substrate according to an embodiment of the disclosure.

FIG. 2 is a schematic top view of an array substrate according to an embodiment of the disclosure; only the first electrode layer, the gate layer, the active layer, and the source drain metal layer are shown in fig. 2.

FIG. 3 is a schematic top view of an array substrate according to an embodiment of the disclosure; only the second electrode layer is shown in fig. 3.

FIG. 4 is a schematic top view of an array substrate according to an embodiment of the disclosure; only the first electrode layer, the gate layer, the active layer, the source drain metal layer, and the second electrode layer are shown in fig. 4.

Fig. 5 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 8 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 10 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 11 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 12 is a schematic structural view of a second electrode according to an embodiment of the present disclosure.

Fig. 13-1 to 13-4 are schematic views illustrating the structure of a second electrode in an embodiment of the present disclosure.

Fig. 14 is a graph showing a transmittance test result of a liquid crystal display panel having the second electrode shown in fig. 13-1 to 13-4 according to an embodiment of the present disclosure.

FIGS. 15-1 to 15-10 are photographs showing light transmittance tests of different liquid crystal display panels according to an embodiment of the present disclosure; the second electrodes of the liquid crystal display panels are respectively provided with a circular hollowed-out hole with different sizes.

Fig. 16 is a schematic diagram showing a light transmittance data acquisition position in a light transmittance test of a liquid crystal display panel according to an embodiment of the present disclosure.

Fig. 17 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 18 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 19 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 20 is a schematic structural diagram of a second electrode of a liquid crystal display panel for performing light transmittance testing according to an embodiment of the present disclosure.

Fig. 21 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 22 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 23 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 24 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 25 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 26 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 27 is a photograph showing light transmittance test of different lcd panels according to an embodiment of the present disclosure.

Fig. 28 is a schematic structural diagram of a second electrode of a liquid crystal display panel for performing light transmittance testing according to an embodiment of the present disclosure.

Fig. 29 is a photograph showing a light transmittance test of different lcd panels according to an embodiment of the present disclosure.

Fig. 30 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 31 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 32 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 33 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

FIGS. 34-1 to 34-10 are photographs showing light transmittance tests of different liquid crystal display panels according to an embodiment of the present disclosure; the second electrodes of the liquid crystal display panels are respectively provided with square hollowed-out holes with different sizes.

Fig. 35 is a schematic diagram of a light transmittance data acquisition position in a light transmittance test of a liquid crystal display panel according to an embodiment of the present disclosure.

Fig. 36 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 37 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 38 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 39 is a schematic diagram of a structure of a second electrode of a liquid crystal display panel for performing a light transmittance test according to an embodiment of the disclosure.

Fig. 40 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 41 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 42 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 43 is a photograph showing a light transmittance test of different lcd panels according to an embodiment of the present disclosure.

Fig. 44 is a schematic diagram of a second electrode of a liquid crystal display panel for performing light transmittance testing according to an embodiment of the present disclosure.

Fig. 45 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 46 is a graph showing the transmittance test results of different lcd panels according to an embodiment of the present disclosure.

Fig. 47 is a graph showing the results of transmittance testing of different lcd panels according to an embodiment of the present disclosure.

Fig. 48 is a photograph showing a light transmittance test of different lcd panels according to an embodiment of the present disclosure.

Fig. 49 is a color shift test result of a liquid crystal display panel in which the second electrode is a slit electrode according to an embodiment of the present disclosure.

Fig. 50 is a color shift test result of a liquid crystal display panel with a circular hollow hole on the second electrode according to an embodiment of the disclosure.

Fig. 51 is a color cast test result of a liquid crystal display panel with a square hollow hole formed on the second electrode according to an embodiment of the disclosure.

Reference numerals illustrate:

101. a substrate base; 102. a first electrode layer; 103. a gate layer; 104. a polysilicon semiconductor layer; 105. a source drain metal layer; 106. a second electrode layer; 107. an insulating dielectric layer; 1071. a gate insulating layer; 1072. an interlayer dielectric layer; 1073. a passivation layer; 1081. a first electrode; 1082. a second electrode; 109. a switching electrode; 201. an active layer of the switching transistor; 202. a data lead; 203. scanning the lead wire; 204. a common connection line; 300. a hollowed hole; 301. the first hollowed-out hole; 302. the second hollowed-out hole; A. a hollowed-out hole row; B. hollow hole columns; C. a first direction; D. a second direction.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

In the related art, the ADS liquid crystal display panel may include an array substrate and a color film substrate disposed opposite to each other, and a liquid crystal layer interposed between the array substrate and the color film substrate. The array substrate comprises a substrate, a first electrode layer, an insulating medium layer and a second electrode layer which are sequentially stacked; wherein, in any one pixel region, the first electrode layer may include a first electrode, and the second electrode layer may include a second electrode; wherein one of the first electrode and the second electrode serves as a pixel electrode, and the other may serve as a common electrode. And a fringe electric field is generated between the pixel electrode and the common electrode and is used for driving liquid crystal in the liquid crystal layer to deflect so as to control the light emission of the liquid crystal display panel in the pixel area. In the ADS liquid crystal display panel in the related art, the rotation plane of the liquid crystal molecules is parallel to the plane of the substrate, which results in a room for further improvement in contrast of the ADS liquid crystal display panel.

In order to improve the above-mentioned shortcomings of the ADS display panel in the related art, the present disclosure provides an ADS liquid crystal display panel with vertical alignment. In the ADS liquid crystal display panel, liquid crystal molecules are in a Vertical Alignment (VA) mode to improve contrast of the liquid crystal display panel. However, the second electrode of the ADS liquid crystal display panel in the related art is usually a slit electrode, which cannot realize multi-domain characteristics when applied to the ADS liquid crystal display panel with vertical alignment of the present disclosure, which is disadvantageous for suppressing color shift and improving viewing angle of the ADS liquid crystal display panel with vertical alignment of the present disclosure.

For this reason, the present disclosure provides an array substrate that may be applied in a liquid crystal display panel, and particularly, an ADS liquid crystal display panel, to improve color shift differences of the liquid crystal display panel at different viewing angles.

Referring to fig. 1, the array substrate of the present disclosure may include a substrate 101, a first electrode 1081, an insulating dielectric layer 107, and a second electrode 1082, which are sequentially stacked. Referring to fig. 5 to 12, the second electrode 1082 is provided with at least one hollow hole 300, and the hollow hole 300 has a convex polygon, a circle or an ellipse.

In the present disclosure, the second electrode 1082 is provided with a hollow hole 300, and an edge of the hollow hole 300 may form a fringe electric field with the first electrode 1081. The hollow hole 300 is a convex polygon, a circle or an ellipse, that is, the edge of the hollow hole 300 is a closed ring shape and is a convex pattern. The edge of the hollow hole 300 is in a closed ring shape, and the fringe electric field between the edge of the hollow hole 300 and the first electrode 1081 changes direction correspondingly along with the change of the edge direction of the hollow hole 300, so that the fringe electric field between the edge of the hollow hole 300 and the first electrode 1081 also presents a plurality of directions, and then the liquid crystal in the liquid crystal display panel can be driven to lodge towards a plurality of different directions, so that the liquid crystal display panel presents a multi-domain characteristic. The hollow hole 300 is in a convex pattern, so that the hollow hole 300 is prevented from being in a concave pattern locally to reduce the area of the hollow hole 300, and the influence of the phase-dislocation phenomenon in the hollow hole 300 on the light transmittance is reduced, so that the hollow hole 300 is ensured to have higher light transmittance. Therefore, the liquid crystal display panel based on the array substrate disclosed by the invention not only can realize multi-domain characteristics, but also can ensure higher light transmittance.

In the present disclosure, when one polygon is a convex polygon, any one of edges of the polygon may serve as one supporting line, and the remaining edges are all on the same side of the supporting line. Illustratively, the convex polygon may be a regular polygon, such as a regular quadrangle, a regular pentagon, a regular hexagon, a regular octagon, and the like. For circular or oval shapes, it can also be considered a convex pattern; any tangent line of the circle or the ellipse can be used as a supporting line, and other points of the circle or the ellipse are all positioned on the same side of the supporting line.

The structure, principle and effect of the array substrate provided by the present disclosure are further explained and illustrated below with reference to the accompanying drawings.

Referring to fig. 1, the array substrate of the present disclosure includes a substrate 101, a first electrode layer 102, an insulating dielectric layer 107, and a second electrode layer 106, which are sequentially stacked. Wherein the first electrode 1081 is located on the first electrode layer 102, and the second electrode 1082 is located on the second electrode layer 106. The first electrode 1081 and the second electrode 1082 are provided correspondingly; of the correspondingly disposed first electrode 1081 and second electrode 1082, the orthographic projection of the first electrode 1081 on the substrate 101 at least partially coincides with the orthographic projection of the second electrode 1082 on the substrate 101. The first electrode 1081 may be a plate electrode in terms of shape, and may not be provided with a slit or a via hole. The second electrode 1082 may be provided with the hollow hole 300 so as to form a fringe electric field with the first electrode 1081. At the functional level of the electrodes, one of the first electrode 1081 and the second electrode 1082 may be a common electrode, and the other may be a pixel electrode. In other words, one of the first electrode layer 102 and the second electrode layer 106 may be provided with a common electrode, and the other may be provided with a pixel electrode.

For example, in one embodiment of the present disclosure, referring to fig. 2 to 4, the first electrode 1081 provided in the first electrode layer 102 may be a plate-shaped electrode and may serve as a pixel electrode. The second electrode 1082 of the second electrode layer 106 may be provided with a hollowed-out hole 300, which may serve as a common electrode.

Alternatively, in the array substrate of the present disclosure, the materials of the first electrode layer 102 and the second electrode layer 106 may be transparent conductive materials, for example, may be transparent metal oxides. Illustratively, the material of the second electrode 1082 is ITO (indium zinc oxide).

Referring to fig. 2, the array substrate of the present disclosure is provided with a plurality of data leads 202, and the data leads 202 may be disposed parallel to each other. The data lead 202 may extend in the column direction as a whole, and may be a straight line or a fold line that is reciprocally bent in the row direction.

When the data lead 202 is a polyline, it may include a plurality of lead segments that extend in different directions. In some embodiments, the edges of the portions of the data leads 202 proximate to the second electrodes 1082 may be parallel to the edges of adjacent second electrodes 1082.

Illustratively, in one embodiment of the present disclosure, referring to fig. 2, the data leads 202 are straight and extend in the column direction; along the row direction, both sides of the second electrode 1082 are provided with data leads 202; the second electrode 1082 is close to the edge of the data lead 202 to be parallel to the extending direction of the data lead 202.

Referring to fig. 2 and 4, the array substrate of the present disclosure is provided with a plurality of scan lines 203 and switching transistors connected to pixel electrodes; one end of the switching transistor is connected with the data lead 202, the other end of the switching transistor is connected with the pixel electrode, and the grid electrode of the switching transistor is connected with the scanning lead 203. The switching transistor may be turned on under control of the scan voltage applied to the scan line 203 so that the data voltage applied to the data line 202 is applied to the pixel electrode.

Alternatively, referring to fig. 2 and 4, the scan lines 203 may extend in the row direction as a whole. The scanning wire 203 may be a straight wire in the row direction or a folded wire that is folded back and forth in the column direction. At least a portion of the first electrode 1081 and the second electrode 1082 may be disposed between adjacent two scan wires 203. In one embodiment of the present disclosure, the first electrodes 1081 and the scan lines 203 are alternately arranged, and the second electrodes 1082 and the scan lines 203 are alternately arranged, along the column direction.

Alternatively, referring to fig. 2 and 4, the scan line 203 may be multiplexed as a gate of the switching transistor. The active layer 201 of the switching transistor may include a source contact region, a channel region, and a drain contact region connected in sequence, the source contact region being connected to the data wire 202 through a via hole, the drain contact region being connected to the pixel electrode through a via hole, and the scan wire 203 overlapping the channel region of the switching transistor such that a portion of the scan wire 203 overlapping the channel region of the switching transistor may serve as a gate electrode of the switching transistor. Further, referring to fig. 2 and 4, the portion of the scan wire 203 overlapping the channel region of the switching transistor may be partially increased in size such that the scan wire 203 completely covers the channel region of the switching transistor.

Alternatively, the material of the active layer 201 of the switching transistor may be an amorphous silicon semiconductor material, a polycrystalline silicon semiconductor material, a metal oxide semiconductor material, or an organic semiconductor material. Illustratively, in one embodiment of the present disclosure, the material of the active layer 201 of the switching transistor may be a low temperature polysilicon semiconductor material; the source contact region and the drain contact region may be ion-doped to have high conductivity, and the channel region may be turned on or off by a scan signal applied to the corresponding gate electrode while maintaining semiconductor characteristics.

Alternatively, referring to fig. 2 and 4, the array substrate of the present disclosure may be further provided with a plurality of common connection lines 204, and the common connection lines 204 extend in a row direction and are connected to respective common electrodes disposed in the same row. In other words, the common electrodes arranged in the same row are connected to the same common connection line 204.

Further, the common connection line 204 may be disposed on the same film layer as the scan line 203, that is, the same material as the scan line 203, and prepared in the same process. As such, the array substrate may be provided with the gate layer 103, and the gate layer 103 is provided with the common connection lines 204 and the scan lines 203 alternately disposed. Among the pixel electrodes and the common electrode provided correspondingly, the common electrode is connected to the common connection line 204 through a via hole, and the gate of the switching transistor to which the pixel electrode is connected to the scan line 203.

In some embodiments, the gate layer 103 is located between the substrate base 101 and the insulating dielectric layer 107, and the second electrode 1082 is a common electrode; the common electrodes arranged in the same row may be connected to the same common connection line 204 through vias. Each of the first electrodes 1081 is a pixel electrode; along the column direction, the pixel electrode is sandwiched between one scan wire 203 and one common connection wire 204; the scan line 203 is used for driving a switching transistor electrically connected to the pixel electrode, and the common connection line 204 is used for connecting to the second electrode 1082 corresponding to the pixel electrode.

In one embodiment of the present disclosure, the orientation layer may not be provided at a side of the second electrode layer remote from the substrate base plate. Thus, an increase in cost of the array substrate due to the provision of the alignment layer and a decrease in yield due to the alignment layer can be avoided.

In the following, a film structure of the array substrate and patterns of the respective films are exemplarily described in order to further explain and explain the structure and principle of the array substrate of the present disclosure. It is understood that the exemplary array substrate is only one specific implementation example of the array substrate of the present disclosure, and is not a specific limitation on the structure of the array substrate of the present disclosure.

Referring to fig. 1 to 4, the exemplary array substrate includes a substrate 101, a first electrode layer 102 and a gate layer 103, a gate insulating layer 1071, a polysilicon semiconductor layer 104, an interlayer dielectric layer 1072, a source drain metal layer 105, a passivation layer 1073, and a second electrode layer 106, which are sequentially stacked.

In this exemplary array substrate, the substrate 101 may be a transparent substrate, and the material thereof may be glass, a sub-gram, or the like.

In this exemplary array substrate, the material of the first electrode layer 102 is a transparent metal oxide, such as ITO. The first electrode layer 102 may be formed with first electrodes 1081 distributed in an array, and the first electrodes 1081 are plate-shaped electrodes and serve as pixel electrodes. The first electrodes 1081 distributed in the array are arranged into a plurality of first electrode 1081 rows and a plurality of first electrode 1081 columns, wherein the first electrode 1081 rows include a plurality of first electrodes 1081 arranged along a row direction, and the first electrode 1081 columns include a plurality of first electrodes 1081 arranged along a column direction.

In this exemplary array substrate, the gate layer 103 includes a plurality of scan lines 203 and a plurality of common connection lines 204 extending in a row direction and alternately arranged. Wherein each of the scan wires 203 and each of the common connection wires 204 are divided into a plurality of wire groups, one wire group including one scan wire 203 and one common connection wire 204 which are adjacently disposed. One lead group is arranged corresponding to one first electrode 1081 row; in one lead group and one first electrode 1081 row correspondingly provided, the scan lead 203 and the common connection line 204 are located on both sides of the first electrode 1081 row, respectively. As such, one scan line 203 and one common connection line 204 are disposed between two adjacent first electrode 1081 rows. Alternatively, the scan lines 203 in the line group corresponding to the first electrode 1081 of the upper row and the common connection lines 204 in the line group corresponding to the first electrode 1081 of the lower row are located between the adjacent two first electrode 1081 rows.

In the preparation, the first electrode layer 102 may be prepared first and then the gate layer 103 may be prepared, or the gate layer 103 may be prepared first and then the first electrode layer 102 may be prepared. In terms of the film layer relationship, the first electrode layer 102 may be located on a side of the gate layer 103 close to the substrate 101, may be located on a side of the gate layer 103 away from the substrate 101, or may be nested with the gate layer 103 and sandwiched between the substrate 101 and the gate insulating layer 1071.

In this exemplary array substrate, the polysilicon semiconductor layer 104 is provided on a side of the gate insulating layer 1071 remote from the substrate 101, and may include a plurality of active layers in one-to-one correspondence with a plurality of first electrodes 1081. The active layer comprises a source electrode contact region, a channel region and a drain electrode contact region which are sequentially connected; the channel region maintains the semiconductor characteristics, and the source contact region and the drain contact region are implanted with dopant ions to have good conductivity. In the active layer and the scan wire 203 corresponding to the same first electrode 1081, the orthographic projection of the channel region of the active layer on the substrate 101 is located within the orthographic projection of the scan wire 203 on the substrate 101; in this way, the source contact region of the active layer may form the source of the switching transistor corresponding to the first electrode 1081, the drain contact region of the active layer may form the drain of the switching transistor corresponding to the first electrode 1081, and the portion of the scan line 203 overlapping the channel region may be multiplexed as the gate of the switching transistor corresponding to the first electrode 1081. In one embodiment of the present disclosure, in the active layer and the scan line 203 corresponding to the same first electrode 1081, the source contact region is at least partially located at a side of the scan line 203 away from the first electrode 1081, and the drain contact region is at least partially located at a side of the scan line 203 close to the first electrode 1081.

In the exemplary array substrate, the source-drain metal layer 105 is disposed on a side of the interlayer dielectric layer 1072 remote from the substrate 101, and may include data leads 202 disposed in one-to-one correspondence with respective first electrode 1081 columns, and include first and second connection portions in one-to-one correspondence with respective switching transistors. The data wires 202 extend along the column direction and are located at one side of the column of the first electrodes 1081. A column of first electrodes 1081 is disposed between two adjacent data leads 202, and a data lead 202 is disposed between two adjacent columns of first electrodes 1081. The first connection portion is connected to the data wire 202 and connected to the source contact region of the corresponding switching transistor through a via penetrating the interlayer dielectric layer 1072; the second connection portion is connected to the drain contact region of the corresponding switching transistor through a via penetrating the interlayer dielectric layer 1072, and is connected to the first electrode 1081 of the corresponding switching transistor through a via penetrating the interlayer dielectric layer 1072 and the gate insulating layer 1071.

In this exemplary array substrate, the second electrode layer 106 is disposed on a side of the passivation layer 1073 away from the substrate 101, and includes second electrodes 1082 disposed corresponding to the respective first electrodes 1081, and the second electrodes 1082 are provided with the hollowed-out holes 300 and function as common electrodes. One row of the second electrodes 1082 corresponds to the same common connection line 204, and one second electrode 1082 overlaps the corresponding common connection line 204, which are connected through vias penetrating the passivation layer 1073, the interlayer dielectric layer 1072, and the gate insulating layer 1071. The second electrode layer 106 is further provided with a transfer electrode 109, and the transfer electrode 109 is connected to the second conductive portion of the source/drain metal layer 105 through a via penetrating the passivation layer 1073, and is connected to the first electrode 1081 through a via penetrating the passivation layer 1073, the interlayer dielectric layer 1072, and the gate insulating layer 1071, so that the drain of the switching transistor is connected to the first electrode 1081. Accordingly, referring to fig. 2 and 4, to provide the transfer electrode 109, the second electrode 1082 may be formed with a relief notch B.

In this exemplary array substrate, the materials of the passivation layer 1073, the interlayer dielectric layer 1072, and the gate insulating layer 1071 may be dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. Illustratively, in one embodiment of the present disclosure, the material of the passivation layer 1073 and the interlayer dielectric layer 1072 is silicon nitride and the material of the gate insulating layer 1071 is silicon oxide. The passivation layer 1073, the interlayer dielectric layer 1072, and the portion of the gate insulating layer 1071 between the first electrode 1081 and the second electrode 1082 may serve as the insulating dielectric layer 107 of the present disclosure. It is understood that one or more of the passivation layer 1073, the interlayer dielectric layer 1072, and the gate insulating layer 1071, a portion between the first electrode 1081 and the second electrode 1082 may also be removed or thinned to adjust the thickness of the insulating dielectric layer 107.

In the array substrate provided by the present disclosure, referring to fig. 5 to 12, the second electrode 1082 is provided with at least one hollow hole 300, and the hollow hole 300 is a convex polygon, a circle or an ellipse. The number of the hollowed-out holes 300 may be determined according to the size of the second electrode 1082. The smaller the size of the hollowed-out holes 300, the more the number of hollowed-out holes 300; the larger the size of the second electrode 1082 is, the smaller the number of the hollowed-out holes 300 is. It can be appreciated that the spacing between the hollowed holes 300 is also an important factor affecting the number of hollowed holes 300, and the larger the spacing between the hollowed holes 300 is, the smaller the number of hollowed holes 300 is.

Optionally, the second electrode 1082 is fully disposed in the hollow hole 300, so that the hollow area of the second electrode 1082 can be increased as much as possible, and the light transmittance of the display panel can be further improved. It can be appreciated that the hollow holes 300 and the edges of the hollow holes 300 and the second electrode 1082 are not directly connected, so as to avoid the hollow holes 300 from blocking the second electrode 1082 and avoid affecting the formation and distribution of the fringe electric field.

In order to verify the effect of different hollowed-out holes on the light transmittance of the liquid crystal display panel, the first to fourth test liquid crystal display panels were prepared and tested. Fig. 13-1 is a schematic diagram showing a partial structure of the second electrode 1082 of the first test lcd panel, wherein the black filled portions represent the hollow holes. The hollow holes 300 on the second electrode 1082 are circular in shape, and the hollow holes 300 are distributed in an array. Fig. 13-4 are schematic partial structures of the second electrode 1082 of the fourth test lcd panel, wherein the black filled portions represent the hollow holes. The shape of the hollow holes 300 on the second electrode 1082 is square, and each hollow hole 300 is distributed in an array along the row-column direction; the row direction may be the direction from the upper left corner to the lower right corner of fig. 13-4, and the column direction may be the direction from the lower left corner to the upper right corner of fig. 13-4. Fig. 13-2 is a schematic diagram showing a partial structure of a second electrode 1082 of a second test lcd panel, wherein black filled portions represent hollowed-out holes. The shape of the hollow holes 300 on the second electrode 1082 is square, and each hollow hole 300 is distributed in an array along the row-column direction; the row direction may be the direction from the upper left corner to the lower right corner of fig. 13-2, and the column direction may be the direction from the lower left corner to the upper right corner of fig. 13-2. Adjacent two rows of hollowed-out holes 300 are distributed in a staggered manner, and adjacent two columns of hollowed-out holes 300 are distributed in a staggered manner. The second test lcd panel is equivalent to that on the basis of the second electrode 1082 of the fourth test lcd panel, one hollow hole 300 is omitted from each hollow hole 300 in each row of hollow holes 300, and one hollow hole 300 is omitted from each hollow hole 300 in each column of hollow holes 300, so that the number of hollow holes 300 on the second electrode 1082 in the third test lcd panel is reduced by nearly half. Fig. 13-3 is a schematic diagram showing a partial structure of the second electrode 1082 of the third test lcd panel, wherein the black filled portion represents a hollowed hole. The hollow holes 300 on the second electrode 1082 are cross-shaped, and each hollow hole 300 is distributed in an array.

Fig. 14 shows the light transmittance of the first to fourth test liquid crystal display panels; the curve represented by the circle is the light transmittance of the first test liquid crystal display panel, the curve represented by the square hollowed-out is the light transmittance of the fourth test liquid crystal display panel, the curve represented by the square interval is the light transmittance of the second test liquid crystal display panel, and the curve represented by the cross is the light transmittance of the third test liquid crystal display panel. Referring to fig. 14, the light transmittance of the first and fourth test liquid crystal display panels is significantly higher than that of the second and third test liquid crystal display panels.

Comparing the light transmittance of the second test liquid crystal display panel with the light transmittance of the fourth test liquid crystal display panel, the light transmittance of the second test liquid crystal display panel is still substantially identical to the light transmittance of the third test liquid crystal display panel under the condition that approximately half of the hollow holes 300 are cancelled on the second electrode 1082; this shows that the use of the hollow hole 300 as a convex polygon can significantly improve the light transmittance of the liquid crystal display panel compared to the use of the cross-shaped hollow hole 300 as a concave polygon.

Comparing the light transmittance of the second test liquid crystal display panel with that of the fourth test liquid crystal display panel, it can be seen that eliminating approximately half of the hollow holes 300 on the second electrode 1082 in the test liquid crystal display panel results in a significant reduction in the light transmittance of the test liquid crystal display panel. This shows that increasing the number of the hollowed-out holes 300 on the second electrode 1082 helps to increase the light transmittance of the liquid crystal display panel.

Comparing the light transmittance of the first test liquid crystal display panel with that of the fourth test liquid crystal display panel, when the second electrode 1082 is fully covered with the hollow holes 300, the liquid crystal display panel can have higher light transmittance no matter whether the hollow holes 300 are square or circular. This means that the shape of the hollowed-out hole 300 is a convex pattern, such as regular polygon, circle, ellipse, etc., which can ensure high transmittance of the liquid crystal display panel.

Alternatively, in the array substrate of the present disclosure, referring to fig. 5 to 12, the hollowed-out holes 300 may include first hollowed-out holes 301, where each first hollowed-out hole 301 may be distributed in an array. The first hollow holes 301 are arranged in at least one hollow hole row a, and the hollow hole row a includes a plurality of first hollow holes 301 that are adjacent in sequence and are arranged in a straight line along the first direction C. In other words, on the second electrode 1082, one or more hollowed-out hole rows a may be provided, and any one hollowed-out hole row a includes a plurality of first hollowed-out holes 301 that are sequentially adjacent and are arranged in a straight line along the first direction C. It will be appreciated that in some embodiments, one row a of hollowed-out holes may also include only one first hollowed-out hole 301. That is, in one hollow hole row a, one first hollow hole 301 may be included, or a plurality of first hollow holes 301 may be included.

In one embodiment of the present disclosure, the distance between two adjacent first hollowed-out holes 301 is in the range of 2-4 microns.

In one embodiment of the present disclosure, the distance between any two adjacent first hollowed holes 301 is the same.

In the present disclosure, the distance between two hollowed holes 300 refers to the minimum value of the distance between any point on the edge of one hollowed hole 300 and any point on the edge of the other hollowed hole 300.

Optionally, the first hollow holes 301 may be further arranged into at least one hollow hole row B, where the hollow hole row B includes a plurality of first hollow holes 301 that are sequentially adjacent and are linearly arranged along the second direction D; the second directions D are all parallel to the plane of the substrate 101 and intersect the first direction C. It will be appreciated that in some embodiments, one hollowed-out hole column B includes one first hollowed-out hole 301. That is, one first hollow hole 301 may be included in one hollow hole row B, or a plurality of first hollow holes 301 may be included.

Optionally, the angle between the first direction C and the second direction D is 90 ° or 60 °. Thus, the distribution density of the first hollow holes 301 can be increased, so as to increase the number of the first hollow holes 301 on the second electrode 1082 and increase the light transmittance of the liquid crystal display panel.

For example, referring to fig. 5, 6, 9, 10, the first direction C is at an angle of 90 ° to the second direction D. In this way, four first hollow holes 301 exist in two adjacent hollow hole rows a and two adjacent hollow hole columns B, the four first hollow holes 301 may be distributed in a square shape, and the centers of the four first hollow holes 301 are located on four top corners of a square respectively.

Still further exemplary, referring to fig. 7, 8, 11, 12, the first direction C is at an angle of 60 ° to the second direction D. In this way, there are three first hollow holes 301 in two adjacent hollow hole rows a and two adjacent hollow hole columns B, the three first hollow holes 301 may be in regular triangle distribution, and the centers (O1, O2 and O3) of the three first hollow holes 301 are respectively located on three vertex angles of a triangle. In this embodiment, the first hollowed holes 301 are closely arranged in a regular hexagon.

In some embodiments, hollowed-out hole 300 is square; the angle between one edge of the hollowed-out hole 300 and the first direction C is in the range of 0-10 °.

Optionally, referring to fig. 7, 8, 11, and 12, the hollowed-out hole 300 further includes a second hollowed-out hole 302, where the second hollowed-out hole 302 is disposed near an outer edge of the second electrode 1082; the spacing (d 2, d 3) between the second hollow hole 302 and the adjacent first hollow holes 301 is smaller than the spacing d1 between the adjacent two first hollow holes 301.

Further, the first hollowed holes 301 are arranged into at least one hollowed hole row a and at least one hollowed hole column B; the hollowed-out hole row A comprises a plurality of first hollowed-out holes 301 which are adjacent in sequence and are arranged in a straight line along a first direction C; the hollowed-out hole column B comprises a plurality of first hollowed-out holes 301 which are adjacent in sequence and are arranged in a straight line along the second direction D; the first direction C and the second direction D are both parallel to the plane of the substrate 101 and intersect;

any one of the second hollow holes 302 is arranged in a straight line with each of the first hollow holes 301 in one of the hollow hole rows a along the first direction C, or is arranged in a straight line with each of the first hollow holes 301 in one of the hollow hole columns B along the second direction D.

In some embodiments, the first hollowed holes 301 are distributed in an array and arranged in hollowed hole rows a and hollowed hole columns B; the distance between the centers of two adjacent first hollow holes 301 is a preset distance. When the space between the edge of the second electrode and the first hole line a is enough to set a hole, but insufficient to enable the hole to keep a preset distance from the adjacent first hole 301 in the hole line a, a second hole 302 may be set in the space. Although the first hollowed holes and the second hollowed holes cannot be distributed in an array on the whole, the arrangement mode can improve the number of the hollowed holes on the second electrode, and further improve the light transmittance of the liquid crystal display panel.

Accordingly, when the space between the edge of the second electrode and the hollow hole row B is enough to provide one hollow hole, but insufficient to enable the hollow hole to keep a preset distance from the adjacent first hollow hole 301 in the hollow hole row B, a second hollow hole 301 may be provided in the space. Although the first hollowed holes and the second hollowed holes cannot be distributed in an array on the whole, the arrangement mode can improve the number of the hollowed holes on the second electrode, and further improve the light transmittance of the liquid crystal display panel.

In the present disclosure, a liquid crystal display panel having only one circular hollow hole 300 of the second electrode 1082 may be manufactured, and the transmittance variation of the liquid crystal display panel at different positions on a test reference line may be tested.

Fig. 15-1 to 15-10 show test photographs of the hollowed-out holes 300 with different sizes, respectively. Wherein, FIG. 15-1 is a photograph of a test when the diameter of the hollowed-out hole is 2 micrometers; FIG. 15-2 is a photograph of a test with a hollowed-out hole of 4 microns in diameter; FIG. 15-3 is a photograph of a test with a hollowed-out hole of 6 microns in diameter; FIGS. 15-4 are photographs of tests with a hollowed-out hole of 8 microns in diameter; FIGS. 15-5 are photographs of tests with a hollowed-out hole of 10 microns in diameter; FIGS. 15-6 are photographs of tests with a hollowed-out hole of 12 microns in diameter; FIGS. 15-7 are photographs of tests with a hollowed-out hole of 14 microns in diameter; FIGS. 15-8 are photographs of tests with a hollowed-out hole of 16 microns in diameter; FIGS. 15-9 are photographs of tests with a hollowed-out hole of 18 microns in diameter; fig. 15-10 are photographs of tests with a hollowed-out hole of 20 microns in diameter. As can be seen from these photographs, the transmittance of the lcd panel is different when the diameters of the hollow holes are different. Referring to fig. 15-3 to 15-10, the liquid crystal display panel exhibits an obvious four-domain characteristic, and a phase error phenomenon exists between four domain areas.

Fig. 16 shows the position of the test reference line, which is the position shown by the arrow. FIG. 17 shows the change in light transmittance at different locations of the hollowed-out hole when the hollowed-out hole is 2 microns to 14 microns; fig. 18 shows the change in light transmittance at different positions of the hollow holes when the hollow holes are 14 micrometers to 20 micrometers. In fig. 17 and 18, the abscissa distance is the relative distance, which is used to represent the relative distance between different test positions and the test reference origin; dx represents the test curve for a hollowed-out hole with a diameter of x microns.

As can be seen from fig. 17 and 18, the maximum light transmittance in the hollow hole 300 increases gradually and then decreases gradually with the increase of the diameter of the circular hollow hole 300. When the diameter of the circular hollow hole 300 is not more than 12 micrometers, the maximum light transmittance in the hollow hole 300 increases along with the increase of the diameter of the circular hollow hole 300; when the diameter of the circular hollow hole 300 is not smaller than 14 micrometers, the maximum light transmittance in the hollow hole 300 decreases with the increase of the diameter of the circular hollow hole 300. When the diameter of the circular hollow hole 300 is 10 micrometers to 14 micrometers, the maximum light transmittance in the hollow hole 300 is more than 35%.

Fig. 19 shows the average light transmittance in the hollow holes 300 when the hollow holes 300 are different in size, and the average light transmittance of the liquid crystal display panel when the hollow holes 300 are different in size. Referring to fig. 19, when the diameter of the circular hollow hole 300 is 10 micrometers, the maximum light transmittance of the liquid crystal display panel in the hollow hole 300 reaches a maximum value; and when the diameter of the circular hollow hole 300 is 12 or 14 micrometers, the average light transmittance of the liquid crystal display panel in the hollow hole 300 is close to 20%, and the liquid crystal display panel is kept at a higher level. When the diameter of the circular hollow hole 300 reaches more than 10 micrometers, the overall light transmittance of the liquid crystal display panel is reduced at a speed that increases with the increase of the diameter of the circular hollow hole 300.

Based on the above test of the liquid crystal display panel with the single circular hollow hole 300, when the diameter of the circular hollow hole 300 is 10-14 micrometers, the liquid crystal display panel can obtain larger light transmittance in the hollow hole 300 region.

In one embodiment of the present disclosure, the hollowed-out hole 300 is circular in shape, and the hollowed-out hole 300 has a diameter of 11 to 13 microns.

In the present disclosure, a liquid crystal display panel with the second electrode 1082 having the hollow holes 300 distributed in an array may be manufactured, referring to fig. 20, the hollow holes 300 are circular in shape, and the included angle between the hollow hole row a and the hollow hole column B is 90 °. That is, in the liquid crystal display panel, the hollow holes 300 may be densely arranged in a square shape. In the liquid crystal display panel for testing, an alignment layer may not be provided, and an included angle between upper and lower polarizers of the liquid crystal display panel is 90 °.

The present disclosure also tests the transmittance of the liquid crystal display panel at different driving voltages with different second electrodes 1082. In fig. 21 to 26, dxSy indicates that the diameter D of the hollowed-out hole is x micrometers and the space S is y micrometers. Fig. 27 shows a test photograph of a liquid crystal display panel having a different second electrode. The photographs at the intersection of Dx row and Sy column are test photographs of a liquid crystal display panel with hollowed-out holes with a diameter of x micrometers and a spacing of y micrometers.

Referring to fig. 21 to 23, among the respective liquid crystal display panels, when the diameters of the hollow holes 300 are fixed, the liquid crystal display panel having a pitch of 2 μm between the hollow holes 300 has the lowest start voltage Vth, wherein the start voltage Vth is a voltage applied to the first electrode 1081 and the second electrode 1082 such that the liquid crystal starts to fall down. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 9V, the liquid crystal display panel having the pitch of 2 μm between the hollow holes 300 has the highest light transmittance. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 15V, the liquid crystal display panel having the 3 μm pitch between the hollow holes 300 has the highest light transmittance. Referring to fig. 24 to 26, when the interval between the hollowed holes 300 is fixed, the larger the diameter of the hollowed holes 300 is, the larger the transmittance of the liquid crystal display panel is. Referring to fig. 27, when the array of hollowed holes is arranged, each hollowed hole position exhibits a distinct four-domain characteristic.

In some embodiments of the present disclosure, the hollowed holes 300 are circular, and the first hollowed holes are densely distributed in a square shape. The diameter of the hollow holes 300 is 11-13 micrometers, and the distance between the first hollow holes is 2-4 micrometers.

Illustratively, in one embodiment of the present disclosure, the hollowed-out holes 300 are 11 microns in diameter, and the distance between the centers of two adjacent first hollowed-out holes 301 is 14 microns.

In the present disclosure, a liquid crystal display panel with the second electrode 1082 having the hollow holes 300 distributed in an array may be manufactured, referring to fig. 28, the hollow holes 300 are circular in shape, and the included angle between the hollow hole row a and the hollow hole column B is 60 °. That is, in the liquid crystal display panel, the hollow holes 300 may be densely arranged in a regular hexagon. In the liquid crystal display panel for testing, an alignment layer may not be provided, and an included angle between upper and lower polarizers of the liquid crystal display panel is 90 °.

The present disclosure also tested the transmittance of the liquid crystal display panel at different driving voltages with different second electrodes 1082, and the results are shown in fig. 30 to 33. In fig. 30 to 33, dxSy indicates that the diameter D of the hollowed-out hole is x micrometers and the space S is y micrometers. Fig. 29 shows a test photograph of a liquid crystal display panel having a different second electrode. The photograph at the intersection of Dx row and Sy column is a liquid crystal display panel with hollowed-out holes with diameter of x micrometers and space of y micrometers.

Referring to fig. 30 to 32, among the respective liquid crystal display panels, when the diameters of the hollow holes 300 are fixed, the liquid crystal display panel having a pitch of 2 μm between the hollow holes 300 has the lowest start voltage Vth, wherein the start voltage Vth is a voltage applied to the first electrode 1081 and the second electrode 1082 such that the liquid crystal starts to fall down. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 9V, the liquid crystal display panel having the pitch of 2 μm between the hollow holes 300 has the highest light transmittance. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 15V, the liquid crystal display panel having the 3 μm pitch between the hollow holes 300 has the highest light transmittance. As can be seen from the data of fig. 30 to 33, when the space between the hollow holes 300 is fixed, the larger the diameter of the hollow holes 300 is, the larger the transmittance of the liquid crystal display panel is. Referring to fig. 29, when the array of hollowed holes is arranged, each hollowed hole position exhibits a distinct four-domain characteristic.

In some embodiments of the present disclosure, the hollowed-out holes 300 are circular and are densely arranged in a regular hexagon. The diameter of the hollow holes 300 is 11-13 micrometers, and the distance between the first hollow holes is 2-4 micrometers.

Illustratively, in one embodiment of the present disclosure, the hollowed-out holes 300 are 13 microns in diameter, and the distance between the centers of two adjacent first hollowed-out holes 301 is 16 microns.

In the present disclosure, a liquid crystal display panel having only one square hollow hole 300 of the second electrode 1082 may be manufactured, and the transmittance variation of the liquid crystal display panel at different positions on a test reference line may be tested. Fig. 35 shows the position of the test reference line, which is the position shown by the arrow.

Fig. 34-1 to 34-10 show test photographs of the hollowed-out hole 300 with different sizes, respectively. 34-1 is a photograph of a test of a hollowed-out hole with an edge length of 2 microns; FIG. 34-2 is a photograph of a test with a 4 micron length of one edge of a hollowed-out hole; FIG. 34-3 is a photograph of a test with a 6 micron length of one edge of a hollowed-out hole; fig. 34-4 are photographs of tests with a hollowed-out hole of 8 microns in diameter; fig. 34-5 are photographs of a test with one edge of the hollowed-out hole having a length of 10 microns; FIGS. 34-6 are photographs of a test with one edge of a hollowed-out hole having a length of 12 microns; FIGS. 34-7 are photographs of a test with one edge of the hollowed-out hole having a length of 14 microns; FIGS. 34-8 are photographs of a test with a length of 16 microns of one edge of a hollowed-out hole; FIGS. 34-9 are photographs of a test with one edge of the hollowed-out hole 18 microns in length; fig. 34-10 are photographs of a test with one edge of the hollowed-out hole having a length of 20 microns. According to the photographs, when the edge lengths of the hollowed-out holes are different, the transmittance of the liquid crystal display panel is different. Referring to fig. 34-3 to 34-10, the liquid crystal display panel exhibits an obvious four-domain characteristic, and a phase error phenomenon exists between four domain areas.

FIG. 36 shows the variation of light transmittance at different positions of the hollow holes when the hollow holes are 2-12 microns; fig. 37 shows the change in light transmittance at different positions of the hollow hole when the hollow hole is 12 micrometers to 20 micrometers. In fig. 36 and 37, the abscissa distance is the relative distance, which is used to represent the relative distance between different test positions and the test reference origin; dx represents a test curve of a hollowed-out hole with an edge length of x micrometers.

As can be seen from fig. 36 and 37, the maximum light transmittance in the hollow holes 300 increases gradually and then decreases gradually with the increase of the size of the square hollow holes 300. When the length of one edge of the square hollow hole 300 is not more than 10 micrometers, the maximum light transmittance in the hollow hole 300 increases with the increase of the length of one edge of the square hollow hole 300; when the length of one edge of the square hollow hole 300 is not less than 12 μm, the maximum light transmittance in the hollow hole 300 decreases as the length of one edge of the square hollow hole 300 increases. When the length of one edge of the square hollow hole 300 is 10 micrometers to 12 micrometers, the maximum light transmittance in the hollow hole 300 is more than 35%.

Fig. 38 shows the average light transmittance in the hollow holes 300 when the hollow holes 300 are different in size, and the average light transmittance of the liquid crystal display panel when the hollow holes 300 are different in size. Referring to fig. 38, when the length of one edge of the square hollow hole 300 is 10 micrometers, the maximum light transmittance of the liquid crystal display panel in the hollow hole 300 reaches a maximum value; and when the length of one edge of the square hollow hole 300 is 8 micrometers, 12 micrometers or 14 micrometers, the average light transmittance of the liquid crystal display panel in the hollow hole 300 is more than 15%, and the liquid crystal display panel is kept at a higher level. When the length of one edge of the square hollow hole 300 reaches more than 10 micrometers, the overall light transmittance of the liquid crystal display panel decreases as the length of one edge of the square hollow hole 300 increases.

Based on the above test of the liquid crystal display panel with the single square hollow hole 300, when the diameter of the square hollow hole 300 is 9-13 micrometers, the liquid crystal display panel can obtain larger light transmittance in the hollow hole 300 area.

In one embodiment of the present disclosure, the hollowed-out hole 300 is square in shape, and the hollowed-out hole 300 has a diameter of 10-12 microns.

In the present disclosure, a liquid crystal display panel with the second electrode 1082 having the hollow holes 300 distributed in an array may be manufactured, referring to fig. 39, the hollow holes 300 are square in shape, and the included angle between the hollow hole row a and the hollow hole column B is 90 °. That is, in the liquid crystal display panel, the hollow holes 300 may be densely arranged in a square shape. In the liquid crystal display panel for testing, an alignment layer may not be provided, and an included angle between upper and lower polarizers of the liquid crystal display panel is 90 °.

The present disclosure also tests the transmittance of the liquid crystal display panel at different driving voltages with different second electrodes 1082. In fig. 40 to 42, dxSy indicates that the length D of one edge of the hollowed-out hole is x micrometers and the spacing S is y micrometers. Fig. 43 shows a test photograph of a liquid crystal display panel having a different second electrode. The photograph at the intersection of Dx row and Sy column is a test photograph of a liquid crystal display panel with one edge of the hollowed-out hole with length of x micrometers and the distance between the hollowed-out holes of y micrometers.

Referring to fig. 40 to 42, among the respective liquid crystal display panels, when the size of the hollow holes 300 is fixed, the liquid crystal display panel having a pitch of 2 μm between the hollow holes 300 has the lowest start voltage Vth, wherein the start voltage Vth is a voltage applied to the first electrode 1081 and the second electrode 1082 such that the liquid crystal starts to fall down. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 9V, the liquid crystal display panel having the pitch of 2 μm between the hollow holes 300 has the highest light transmittance. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 15V, the liquid crystal display panel having the 3 μm pitch between the hollow holes 300 has the highest light transmittance. Referring to each of the data in fig. 40 to 42, when the interval between the hollowed holes 300 is fixed, the larger the size of the hollowed holes 300 is, the larger the transmittance of the liquid crystal display panel is. Referring to fig. 43, when the array of hollowed holes is arranged, each hollowed hole position exhibits a distinct four-domain characteristic.

In some embodiments of the present disclosure, the hollowed-out holes 300 are square, and the first hollowed-out holes are densely distributed in square. The length of one edge of the hollowed-out hole 300 is 9-11 micrometers, and the interval between the first hollowed-out holes is 2-4 micrometers.

Illustratively, in one embodiment of the present disclosure, one edge of the hollowed-out hole 300 has a length of 11 microns, and a distance between centers of two adjacent first hollowed-out holes 301 is 14 microns.

Still further exemplary, in one embodiment of the present disclosure, one edge of the hollowed-out hole 300 has a length of 9 micrometers, and a distance between centers of two adjacent first hollowed-out holes 301 is 11 micrometers.

In the present disclosure, a liquid crystal display panel with the second electrode 1082 having the hollow holes 300 distributed in an array may also be manufactured, referring to fig. 44, the hollow holes 300 are square in shape, and the included angle between the hollow hole row a and the hollow hole column B is 60 °. That is, in the liquid crystal display panel, the hollow holes 300 may be densely arranged in a regular hexagon. In the liquid crystal display panel for testing, an alignment layer may not be provided, and an included angle between upper and lower polarizers of the liquid crystal display panel is 90 °.

The present disclosure also tested the transmittance of the liquid crystal display panel at different driving voltages with different second electrodes 1082, and the results are shown in fig. 45 to 47. In fig. 45 to 47, dxSy indicates that a length D of one edge of each hollow hole is x micrometers and a spacing S is y micrometers, where the spacing is a difference between a length of a center of two adjacent hollow holes and a length of one edge of one hollow hole. Fig. 48 shows a test photograph of a liquid crystal display panel having a different second electrode. The photograph at the intersection of Dx row and Sy column is a liquid crystal display panel with hollowed-out holes with diameter of x micrometers and space of y micrometers.

Referring to fig. 45 to 47, among the respective liquid crystal display panels, when the size of the hollow holes 300 is fixed, the liquid crystal display panel having a pitch of 2 micrometers between the hollow holes 300 has the lowest start voltage Vth, wherein the start voltage Vth is a voltage applied to the first electrode 1081 and the second electrode 1082 such that the liquid crystal starts to fall down. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 9V, the liquid crystal display panel having the pitch of 2 μm between the hollow holes 300 has the highest light transmittance. When the voltage difference applied to the first electrode 1081 and the second electrode 1082 is 15V, the liquid crystal display panel having the 3 μm pitch between the hollow holes 300 has the highest light transmittance. As can be seen from the data of fig. 45 to 47, when the space between the hollow holes 300 is fixed, the larger the size of the hollow holes 300 is, the larger the transmittance of the liquid crystal display panel is. Referring to fig. 48, when the array of hollowed holes is arranged, each hollowed hole position exhibits a distinct four-domain characteristic.

In some embodiments of the present disclosure, the hollowed-out holes 300 are square and densely arranged in a regular hexagon. The length of one edge of the hollow holes 300 is 9-11 micrometers, and the interval between the first hollow holes is 2-4 micrometers.

Illustratively, in one embodiment of the present disclosure, one edge of the hollowed-out hole 300 has a length of 10 microns, and a distance between centers of two adjacent first hollowed-out holes 301 is 13 microns.

In one embodiment of the present disclosure, the hollowed-out hole 300 is square; the angle between one edge of the hollowed-out hole 300 and the first direction C is in the range of 0-10 °.

Three different liquid crystal display panels were prepared to test the difference in color shift between the different display panels, four samples were prepared for each liquid crystal display panel. The first liquid crystal display panel is provided with an orientation layer, and the second electrode is a slit electrode. The second liquid crystal display panel is not provided with an orientation layer, the second electrode is provided with hollowed holes distributed in an array mode, and the hollowed holes are circular in shape. The third liquid crystal display panel is not provided with an orientation layer, the second electrode is provided with hollowed holes distributed in an array, and the hollowed holes are square in shape.

The color shift values of three different liquid crystal display panels were tested at different viewing angles, and the results are shown in fig. 49 to 51. Fig. 49 shows a test result of the first lcd panel; FIG. 50 is a test result of a second liquid crystal display panel; fig. 51 shows a test result of a third liquid crystal display panel. As can be seen from comparing fig. 49 to 51, when the second electrode is provided with the hollow hole, the liquid crystal display panel has a lower color deviation value, which is about half of the color deviation value of the first liquid crystal display panel. Moreover, the color deviation values of the second liquid crystal display panel and the third liquid crystal display panel at different visual angles at the left side and the right side are not greatly different, and the color deviation values of the first liquid crystal display panel at different visual angles at the left side and the right side are greatly different. This shows that the array substrate provided by the present disclosure can not only avoid setting an alignment layer, reduce the cost of the liquid crystal display panel and improve the yield, but also reduce the color shift of the liquid crystal display panel.

The disclosed embodiments also provide a liquid crystal display panel including any one of the liquid crystal display panels described in the array substrate embodiments above. The liquid crystal display panel can be a computer screen, a mobile phone screen or other types of liquid crystal display panels. Since the liquid crystal display panel has any one of the array substrates described in the above embodiment of the array substrate, the liquid crystal display panel has the same beneficial effects, and the disclosure is not repeated here.

In one embodiment of the disclosure, the liquid crystal display panel further comprises a color film substrate, wherein the color film substrate and the array substrate are arranged in a box-to-box manner; a liquid crystal layer is arranged between the array substrate and the color film substrate.

Optionally, the liquid crystal in the liquid crystal layer is a negative liquid crystal.

Optionally, the liquid crystal display panel is a vertically aligned liquid crystal display panel; when no voltage is applied between the first electrode and the second electrode, the angle between the long axes of the liquid crystal molecules in the liquid crystal layer and the plane of the array substrate may be 85-90 °. In one embodiment of the present disclosure, when no voltage is applied between the first electrode and the second electrode, the long axes of the liquid crystal molecules in the liquid crystal layer are perpendicular to the plane of the array substrate.

Illustratively, in one embodiment of the present disclosure, the liquid crystal display panel is a vertically aligned ADS liquid crystal display panel, which may have advantages of both a wide viewing angle and high light transmittance of the ADS display panel and a high contrast of a VA (vertically aligned) display panel, and also achieve an effect of achieving multi-domain characteristics in a vertically aligned mode using a fringe electric field.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. An array substrate comprises a substrate, a first electrode, an insulating medium layer and a second electrode which are sequentially stacked; wherein, the second electrode is provided with at least one hollowed-out hole;

the hollow holes are round, and the diameters of the hollow holes are within the range of 10-14 microns;

Or the hollowed-out hole is square, and the size of one edge of the hollowed-out hole is in the range of 9-13 microns;

the hollow holes comprise first hollow holes, and the distance between two adjacent first hollow holes is within the range of 2-4 microns; the distance between two hollowed holes refers to the minimum value of the distance between any point on the edge of one hollowed hole and any point on the edge of the other hollowed hole;

the hollow hole further comprises a second hollow hole, and the second hollow hole is arranged close to the outer side edge of the second electrode; the distance between the second hollowed-out hole and the adjacent first hollowed-out hole is smaller than the distance between the adjacent two first hollowed-out holes;

the first hollowed holes are arranged into at least one hollowed hole row and at least one hollowed hole column; the hollowed-out hole row comprises a plurality of first hollowed-out holes which are sequentially adjacent and are linearly arranged along a first direction; the hollowed-out hole columns comprise a plurality of first hollowed-out holes which are adjacent in sequence and are arranged in a straight line along a second direction; the first direction and the second direction are parallel to the plane of the substrate base plate and are intersected.

2. The array substrate of claim 1, wherein the first direction and the second direction have an angle of 90 ° or 60 °.

3. The array substrate of claim 1, wherein the hollowed-out hole is square; an included angle between one edge of the hollowed-out hole and the first direction is within a range of 0-10 degrees.

4. The array substrate of claim 1, wherein an included angle between the first direction and the second direction is 90 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 11 microns, and the distance between the centers of two adjacent first hollowed holes is 14 microns.

5. The array substrate of claim 1, wherein an included angle between the first direction and the second direction is 90 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 9 microns, and the distance between the centers of two adjacent first hollowed holes is 11 microns.

6. The array substrate of claim 1, wherein an included angle between the first direction and the second direction is 60 °; the hollowed-out holes are square; the length of one edge of each hollowed hole is 10 microns, and the distance between the centers of two adjacent first hollowed holes is 13 microns.

7. The array substrate of claim 1, wherein an included angle between the first direction and the second direction is 90 °; the hollowed-out hole is circular; the diameter of each hollowed hole is 11 microns, and the distance between the centers of two adjacent first hollowed holes is 14 microns.

8. The array substrate of claim 1, wherein an included angle between the first direction and the second direction is 60 °; the hollowed-out hole is circular; the diameter of each hollowed hole is 13 microns, and the distance between the centers of two adjacent first hollowed holes is 16 microns.

9. The array substrate according to any one of claims 1 to 8, wherein,

10. The array substrate of claim 1, wherein the first electrode and the second electrode are transparent electrodes.

11. A liquid crystal display panel, comprising:

the array substrate of any one of claims 1 to 10;

12. The liquid crystal display panel according to claim 11, wherein the liquid crystal in the liquid crystal layer is a negative liquid crystal.

13. The liquid crystal display panel according to claim 11, wherein an included angle between a long axis direction of liquid crystal molecules in the liquid crystal layer and a plane of the array substrate is between 85 ° and 90 ° when no voltage is applied between the first electrode and the second electrode.