CN115345112B

CN115345112B - Integrated circuit diagram generation method and device, electronic equipment and storage medium

Info

Publication number: CN115345112B
Application number: CN202210987823.2A
Authority: CN
Inventors: 管文超; 郭建国; 张剑云
Original assignee: Shanghai Jihaiyingxin Technology Co ltd
Current assignee: Shanghai Lingfan Microelectronics Co ltd
Priority date: 2022-08-17
Filing date: 2022-08-17
Publication date: 2024-03-26
Anticipated expiration: 2042-08-17
Also published as: CN115345112A

Abstract

The embodiment of the application provides a method, a device, electronic equipment and a storage medium for generating an integrated circuit diagram, wherein the method comprises the following steps: traversing the original data in the original integrated circuit diagram; according to the mapping relation between the original data and the target data, the original data is adjusted to be the target data; and generating a target integrated circuit diagram according to the target data, wherein the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes. By adopting the technical scheme provided by the embodiment of the application, after the integrated circuit diagram is migrated from the original process to the target process, the class and attribute information of various objects in the original integrated circuit diagram can be reserved, so that a designer can conveniently analyze and adjust the target integrated circuit diagram.

Description

Integrated circuit diagram generation method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a method and apparatus for generating an integrated circuit diagram, an electronic device, and a storage medium.

Background

With the abundance of integrated circuit fabrication processes and the development of process nodes, integrated circuit design companies have more process options. In the process of developing new products, integrated circuit design companies shift the existing mature integrated circuit diagram from one process to another, so that the design time of the integrated circuit diagram can be effectively shortened, and the project progress can be accelerated.

A circuit diagram migration method in the prior art comprises the following steps: deriving a geometric data standard (Geometry Data Standard, GDS) file corresponding to the original integrated circuit diagram in an electronic design automation (Electronic design automation, EDA) tool; then, the GDS file is adjusted according to the target process, so that the adjusted GDS file accords with the target process; and finally, importing the adjusted GDS file into an EDA tool to generate a target integrated circuit diagram, so that the design time of the target integrated circuit diagram is effectively shortened.

However, in the process of exporting the GDS file in the EDA tool, class and attribute information of various objects in the original integrated circuit diagram is lost, so that the regenerated target integrated circuit diagram is only a combination of graphics, and can only be operated as a whole, which is inconvenient for modifying the target integrated circuit.

Disclosure of Invention

In view of this, the present application provides a method, apparatus, electronic device and storage medium for generating an integrated circuit diagram, so as to solve the problem that in the prior art, in the process of exporting a GDS file in an EDA tool, class and attribute information of various objects in an original integrated circuit diagram may be lost, so that a regenerated target integrated circuit diagram is only a combination of diagrams, and only can be operated as a whole, which is inconvenient for modifying a target integrated circuit.

In a first aspect, an embodiment of the present application provides a method for generating an integrated circuit diagram, including:

traversing the original data in the original integrated circuit diagram;

according to the mapping relation between the original data and the target data, the original data is adjusted to be the target data;

and generating a target integrated circuit diagram according to the target data.

In one possible implementation, the original integrated circuit diagram and the target integrated circuit diagram correspond to one or more combinations of different process design suites PDK, device property profiles CDF, layer matching files Layermap.

In one possible implementation manner, the original integrated circuit diagram and the target integrated circuit diagram correspond to different processes, the original integrated circuit diagram includes first original data associated with the processes, and the adjusting the original data into target data according to the mapping relationship between the original data and the target data includes:

and scaling the first original data according to the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram to obtain first target data.

By adopting the technical scheme provided by the embodiment of the application, when the original process and the target process correspond to different processes, in the process of transferring the original integrated circuit diagram from the original process to the target process, the first original data can be scaled according to the change of the process so as to meet the process requirement of the target process. For example, the first raw data is device data, and the device data in the original integrated circuit diagram can be scaled according to a change in the process during the process of migrating the original integrated circuit diagram from the original process to the target process.

In one possible implementation manner, the scaling the first raw data according to the process scaling factor between the raw integrated circuit diagram and the target integrated circuit diagram to obtain first target data includes:

scaling the first original data according to the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram to obtain intermediate data;

and according to the lattice point step length of the target integrated circuit diagram, rounding up or rounding down the intermediate data to be integral multiple of the lattice point step length, and obtaining first target data.

By adopting the technical scheme provided by the embodiment of the application, when the original process and the target process correspond to different processes, in the process of transferring the original integrated circuit diagram from the original process to the target process, not only the first original data can be scaled according to the change of the process, but also the first target data transferred to the target process can meet the requirement of integral multiple of the lattice step length, namely on-grid. For example, the first original data is the width and the length of the MOS transistor, and in the process of migrating the original integrated circuit diagram from the original process to the target process, the width and the length of the MOS transistor in the original integrated circuit diagram can be scaled according to the change of the process, and the width and the length of the MOS transistor migrated to the target process can be made to meet the requirement of integral multiple of the lattice step.

In one possible implementation manner, the rounding up or rounding down the intermediate data to an integer multiple of the lattice step according to the lattice step of the target integrated circuit diagram, to obtain first target data includes:

if the difference value between the intermediate data and the integral multiple of the lattice point step length is smaller than the difference value between the intermediate data and the integral multiple of the lattice point step length, the intermediate data is rounded up to the integral multiple of the lattice point step length, and first target data are obtained;

and if the difference value between the intermediate data and the integral multiple of the lattice point step length is larger than the difference value between the intermediate data and the integral multiple of the lattice point step length, the intermediate data is rounded up to the integral multiple of the lattice point step length, and the first target data is obtained.

By adopting the technical scheme provided by the embodiment of the application, when the original process and the target process correspond to different processes, in the process of transferring the original integrated circuit diagram from the original process to the target process, not only can the first target data transferred to the target process meet the requirement of integral multiple of the lattice step length, but also the first target data can be ensured to be the integral multiple of the lattice step length closest to the first original data after scaling.

In one possible implementation manner, the original integrated circuit diagram includes second original data, and the second original data in the original integrated circuit diagram is the same as second target data in the target integrated circuit diagram, and the adjusting the original data into the target data according to the mapping relationship between the original data and the target data includes:

and taking the second original data as the second target data.

By adopting the technical scheme provided by the embodiment of the application, in the process of migrating the original integrated circuit diagram from the original process to the target process, the second original data which is not related to the process does not need to be considered, the second original data in the original process is directly used as the second target data in the target process, and the second original data is ensured not to be lost in the process of migrating the process. For example, the second original data is information such as text annotation, and in the process of migrating the original integrated circuit diagram from the original process to the target process, the information such as text annotation in the original integrated circuit diagram can be ensured not to be lost.

In one possible implementation manner, the original integrated circuit diagram includes third original data, and the third original data in the original integrated circuit diagram corresponds to third target data in the target integrated circuit diagram, and the adjusting the original data into the target data according to the mapping relationship between the original data and the target data includes:

And adjusting the third original data into the third target data according to the corresponding relation between the third original data and the third target data.

By adopting the technical scheme provided by the embodiment of the application, in the process of migrating the original integrated circuit diagram from the original process to the target process, the third original data in the original process is replaced by the third target data in the target process so as to meet the requirements of the target process.

In one possible implementation manner, before the adjusting the original data into the target data according to the mapping relationship between the original data and the target data, the method further includes:

and configuring the mapping relation between the original data and the target data according to the design process of the original integrated circuit diagram and the target integrated circuit diagram.

In one possible implementation, the raw data includes raw parameterized cell Pcell data, raw wiring pattern data, raw via data, and/or raw tag data;

the target data comprises target parameterization cell data, target connection line graph data, target through hole data and/or target label data.

By adopting the technical scheme provided by the embodiment of the application, the reconstructed target integrated circuit diagram can be ensured to comprise parameterized cell data, wiring graph data, through hole data and label data, and if the data are absent, the target integrated circuit diagram cannot be accurately generated.

In a second aspect, an embodiment of the present application provides an apparatus for generating an integrated circuit diagram, including:

the traversing unit is used for traversing the original data in the original integrated circuit diagram;

the adjusting unit is used for adjusting the original data into target data according to the mapping relation between the original data and the target data;

and the generating unit is used for generating a target integrated circuit diagram according to the target data, wherein the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes.

In one possible implementation, the apparatus further includes:

and the configuration unit is used for configuring the mapping relation between the original data and the target data according to the design process of the original integrated circuit diagram and the target integrated circuit diagram.

In a third aspect, an embodiment of the present application provides an electronic device, including:

a processor;

a memory;

and a computer program, wherein the computer program is stored in the memory, the computer program comprising instructions that, when executed by the processor, cause the electronic device to perform the method of any of the first aspects.

In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, where the computer readable storage medium includes a stored program, where when the program runs, the program controls a device in which the computer readable storage medium is located to execute the method of any one of the first aspects.

By adopting the technical scheme provided by the embodiment of the application, after the integrated circuit diagram is migrated from the original process to the target process, the class and attribute information of various objects in the original integrated circuit diagram can be reserved, so that a designer can conveniently analyze and adjust the target integrated circuit diagram.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a method for generating an integrated circuit diagram according to an embodiment of the present application;

fig. 2 is a schematic diagram of a mapping relationship between an original PDK and a target PDK according to an embodiment of the present application;

fig. 3 is a schematic diagram of a mapping relationship between original data and target data according to an embodiment of the present application;

fig. 4 is a schematic diagram of a mapping relationship between an original Pcell and a target Pcell corresponding to a device X according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a mapping relationship between an original connection pattern X and a target connection pattern X according to an embodiment of the present application;

Fig. 6 is a schematic diagram of a mapping relationship between an original through hole X and a target through hole X according to an embodiment of the present application;

fig. 7 is a schematic diagram of a mapping relationship between an original tag X and a target tag X according to an embodiment of the present application;

FIG. 8 is a block diagram of an apparatus for integrated circuit diagram generation according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Referring to fig. 1, a flowchart of a method for generating an integrated circuit diagram is provided in an embodiment of the present application. As shown in fig. 1, it mainly includes the following steps.

Step S101: traversing the raw data in the raw integrated circuit graph.

For ease of illustration, in embodiments of the present application, the pre-migration, existing integrated circuit diagram is referred to as the "original integrated circuit diagram"; the integrated circuit diagram generated after migration is referred to as a "target integrated circuit diagram". In some possible implementations, the original integrated circuit diagram may also be referred to as an original layout; the target integrated circuit map may also be referred to as a target layout. It is understood that the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes, wherein "different design processes" refers to different design rules, which may correspond to the same process or different processes.

Illustratively, the original integrated circuit diagram is a 55nm design process for company A and the target integrated circuit diagram is a 55nm design process for company B; the original integrated circuit diagram is 55nm design process of company A, and the target integrated circuit diagram is 40nm design process of company B; the original integrated circuit diagram is a 40nm process of company A, and the target integrated circuit diagram is a 55nm process of company B; the original integrated circuit diagram is 55nm design process of company A, and the target integrated circuit diagram is 40nm design process of company A, etc.

In the EDA tool, the original integrated circuit map includes corresponding original data packets and the target integrated circuit map includes corresponding target data packets. It can be understood that the original data packet is a data packet conforming to the design rule of the original process (the design process corresponding to the original integrated circuit diagram); the target data packet is a data packet conforming to the design rule of the target process (the design process corresponding to the target integrated circuit diagram). It will be appreciated that in order to migrate the original integrated circuit diagram from the original process to the target process, the original data in the original data packet needs to be adjusted to target data that complies with the design rules of the target process. Thus, in the present embodiment, the raw data in the raw integrated circuit diagram is traversed first.

In particular implementations, the original data packet and the target data packet may be a process design suite (Process Design Kit, PDK), a device property description file (Component Description Format, CDF), and/or a layer matching file (Layermap). Correspondingly, the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes, and specifically can be: the original integrated circuit diagram and the target integrated circuit diagram correspond to different process design suites PDK, device property profiles CDF and/or layer matching files Layermap. The PDK is a set of data packets reflecting the process defined by a wafer factory, and defines symbols and simulation models of devices such as resistor and capacitor of a transistor, layers for layout design, parameters of through holes, design rules and the like, and is the basis for design companies to do integrated circuit design and physical verification. The CDF defines the type, name, parameters of the device, and parameter call relationship function sets, device models, various view formats of the device, etc.

Step S102: and adjusting the original data into target data according to the mapping relation between the original data and the target data.

In the embodiment of the application, the original data packet corresponding to the original process and the target data packet corresponding to the target process have a specific mapping relationship. Accordingly, the original data in the original data packet and the target data in the target data packet have a specific mapping relation. Therefore, the original data conforming to the original process can be adjusted to the target data conforming to the target process according to the mapping relation between the original data and the target data.

Referring to fig. 2, a schematic diagram of a mapping relationship between an original PDK and a target PDK is provided in an embodiment of the present application. The original PDK is the PDK corresponding to the original integrated circuit, and the target PDK is the PDK corresponding to the target integrated circuit. As shown in fig. 2, the original data in the original PDK corresponds one-to-one with the target data in the target PDK. Specifically, model a, parameter a_1/parameter a_2/… …, layer name B, and via C in the original PDK correspond to model a, parameter a_1/parameter a_2/… …, layer name B, and via C, respectively, in the target PDK.

In one possible implementation, the original data packet includes multiple types of original data that are not used, and correspondingly, the target data packet includes multiple different types of target data. Specifically, a portion of the raw data in the raw data packet is associated with a process, such as coordinates, parameters, etc. of the device, and is hereinafter referred to as "first raw data", and correspondingly, the target data corresponding to the first raw data is referred to as "first target data"; a portion of the original data in the original data packet is identical to the corresponding target data in the target data packet, such as a device name, a rotation value, etc., and is hereinafter referred to as "second original data", and correspondingly, the target data corresponding to the second original data is referred to as "second target data"; a portion of the original data in the original data packet corresponds to corresponding target data in the target data packet, such as a model corresponding to a device, etc., and is hereinafter referred to as "third original data", and correspondingly, the target data corresponding to the third original data is referred to as "third target data".

In one possible implementation, the original process and the target process correspond to different processes. When the original data is the first original data, according to the mapping relation between the original data and the target data, the original data is adjusted to the target data, which comprises the following steps: and scaling the first original data according to the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram to obtain first target data. Specifically, the first target data=the first raw data is the process scaling factor. The process scaling factor is the process scaling factor between the original process and the target process, i.e. the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram. For example, the original process is 40m and the target process is 20nm, and the process scaling ratio=target process/original process=20 nm/40 nm=0.5. In summary, by adopting the technical scheme provided by the embodiment of the application, the scaling of the first data associated with the process can be satisfied when the process is changed.

The Grid step size (Grid) is a specific integer multiple of the unit step size (typically 1 nm). To ensure that the integrated circuit diagram passes design rule verification and normal flow, the portion of data in the integrated circuit diagram typically needs to be an integer multiple of Grid, referred to as on-Grid. For example, the width and length of the MOS transistor in the integrated circuit diagram need to be integer multiples of the lattice step size. It can be appreciated that after the first raw data is scaled according to the process scaling factor, the obtained first target data may not meet the requirement of the grid point step size in the target integrated circuit diagram. In other words, the first target data is not an integer multiple of the lattice step size of the target integrated circuit graph, which may result in the target integrated circuit graph failing to pass the design rule verification and the normal flow.

In one possible implementation, the scaling the first original data according to the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram to obtain first target data includes: scaling the first original data according to the process scaling factor between the original integrated circuit diagram and the target integrated circuit diagram to obtain intermediate data; and according to the lattice step length of the target integrated circuit diagram, rounding up or rounding down the intermediate data to be integral multiple of the lattice step length, and obtaining the first target data. That is, after the first original data is scaled according to the process scaling factor, the scaled data is rounded to an integer multiple of the lattice step size, and the rounded value is taken as the first target data.

In one possible implementation, the intermediate data should be rounded nearby to obtain the first target data closest to the intermediate data. Specifically, according to a lattice step length of a target integrated circuit diagram, rounding up or rounding down intermediate data to be integer times of the lattice step length, obtaining first target data, including: if the difference value between the intermediate data and the integral multiple of the lattice point step length is smaller than the difference value between the intermediate data and the integral multiple of the lattice point step length, the intermediate data is rounded up to the integral multiple of the lattice point step length, and the first target data is obtained. That is, when the intermediate data is closer to the rounded-up value, the intermediate data is rounded-up. If the difference value between the intermediate data and the integral multiple of the lattice point step length is larger than the difference value between the intermediate data and the integral multiple of the lattice point step length, the intermediate data is rounded up to the integral multiple of the lattice point step length, and the first target data is obtained. That is, when the intermediate data is closer to the rounded-down value, the intermediate data is rounded-down.

It should be noted that, in the above embodiment, the original process and the target process correspond to different processes, and the process scaling factor is not equal to 1. It can be understood that when the original process and the target process correspond to the same process, the process scaling factor is equal to 1, and the first original data is the same as the first target data, so that the first original data can be processed according to the processing mode of the second original data. The processing mode of the second original data is explained below.

Specifically, when the original data is the second original data, since the second original data in the original integrated circuit diagram is the same as the second target data in the target integrated circuit diagram, the adjusting the original data to the target data according to the mapping relationship between the original data and the target data includes: and taking the second original data as second target data. That is, no modification of the second original data is required in the original data packet. In a specific implementation, the second original data may be text description information (e.g., a device name, etc.), and in this embodiment of the present application, after the integrated circuit diagram is migrated from the original process to the target process, the text description information in the original integrated circuit is retained in the target integrated circuit diagram, so that a designer may conveniently analyze the target integrated circuit diagram.

When the original data is the third original data, the third original data in the original integrated circuit diagram corresponds to the third target data in the target integrated circuit diagram, so that the original data is adjusted to the target data according to the mapping relation between the original data and the target data, which comprises the following steps: and adjusting the third original data into third target data according to the corresponding relation between the third original data and the third target data. That is, the third original data is directly replaced with the third target data without performing calculation.

For ease of understanding, the data handling process of the migration of the original integrated circuit diagram from the original process to the target process is described in detail below in connection with a specific implementation.

Referring to fig. 3, a schematic diagram of a mapping relationship between original data and target data is provided in an embodiment of the present application. As shown in fig. 3, the original data in the original integrated circuit diagram corresponds to the target data in the target integrated circuit diagram one by one. Specifically, parameterized cells (Pcell), wiring patterns, vias, and tags in the original integrated circuit diagram correspond to Pcell, wiring patterns, vias, and tags in the target integrated circuit diagram, respectively. Where Pcell refers to a graphically represented device cell whose parameters can be set. For ease of illustration, the Pcell, the wiring pattern, the via, and the tag in the original integrated circuit diagram will be referred to as an original Pcell, an original wiring pattern, an original via, and an original tag, respectively; the Pcell, the wiring pattern, the through hole and the label in the target integrated circuit diagram are respectively called a target Pcell, a target wiring pattern, a target through hole and a target label. It can be appreciated that in the process of migrating the original integrated circuit diagram from the original process to the target process, the original Pcell, the original wiring pattern, the original via and the original tag in the original integrated circuit diagram need to be adjusted to the corresponding target Pcell, the target wiring pattern, the target via and the target tag according to the method shown in step S102. The following description will be given separately.

Referring to fig. 4, a schematic diagram of a mapping relationship between an original Pcell and a target Pcell corresponding to a device X according to an embodiment of the present application is provided. As shown in fig. 4, the original Pcell corresponding to the device X includes a model, a device name, coordinates, rotation values, and parameters (e.g., a length and a width of the device, etc.). The coordinates and parameters in the original Pcell are the original data associated with the process, i.e., the coordinates and parameters in the original Pcell are the first original data. Therefore, in the data processing process, multiplying the coordinates in the original Pcell by the process scaling factor to obtain the coordinates in the target Pcell; and multiplying the parameters in the original Pcell by the process scaling factor to obtain the parameters in the target Pcell. Of course, in some possible implementations, after multiplying the coordinates and/or parameters in the original Pcell by the process scaling factor, the coordinates and/or parameters may be rounded up or rounded down to be an integer multiple of the lattice step, which is not described in detail in the embodiments of the present application. The device name and the rotation number in the original Pcell are the same as those in the target Pcell, namely the device name and the rotation number in the original Pcell are the second original data. Therefore, in the data processing process, the device name and the rotation value in the original Pcell can be directly used as the device name and the rotation value in the target Pcell, namely, the device name and the rotation value in the original Pcell are not modified. The model in the original Pcell corresponds to the model in the target Pcell, i.e., the model in the original Pcell is the third original data. Therefore, in the data processing process, the model in the original Pcell can be replaced by the model in the target Pcell according to the corresponding relation between the model in the original Pcell and the model in the target Pcell. Illustratively, the model in the original Pcell is the SPICE software of the Vscice version, and the model in the target Pcell is the SPICE software of the Hscice version. In the embodiment of the application, the model in the original Pcell is replaced by the model in the target Pcell, namely the SPICE software of the Vstand version is replaced by the SPICE software of the Hstand version. SPICE (Simulation Program with Integrated Circuit Emphasis, a simulated circuit simulator) was created by the california university berkeley division, which developed into a global standard integrated circuit simulator.

It should be noted that, in fig. 4, only the device X is taken as an example to illustrate the mapping relationship between the original Pcell and the target Pcell, which should not be taken as a limitation of the protection scope of the present application. For example, there are other devices in the original integrated circuit diagram in addition to device X; alternatively, other types of data may be present in the device X, which is not particularly limited by the embodiments of the present application.

Referring to fig. 5, a schematic diagram of a mapping relationship between an original connection pattern X and a target connection pattern X according to an embodiment of the present application is provided. As shown in fig. 5, the original connection graph X includes vertex coordinates and layer names. The vertex coordinates are the original data associated with the process, i.e. the vertex coordinates in the original connection pattern X are the first original data. Therefore, in the data processing process, the vertex coordinates in the original link graph X are multiplied by the process scaling factor to obtain the vertex coordinates in the target link graph X. Of course, in some possible implementations, after the vertex coordinates in the original connection graph X are multiplied by the process scaling factor, the vertex coordinates may be rounded up or rounded down to be integer multiples of the lattice step size, which is not described in detail in the embodiments of the present application. The layer name in the original connection graph X corresponds to the layer name in the target connection graph X, namely the layer name in the original connection graph X is the third original data. Therefore, in the data processing process, the layer name in the original connection graph X can be replaced by the layer name in the target connection graph X according to the corresponding relationship between the layer name in the original connection graph X and the layer name in the target connection graph X.

It should be noted that, in fig. 5, the mapping relationship between the original wiring pattern X and the target wiring pattern X is described by taking the original wiring pattern X as an example, which should not be taken as a limitation of the protection scope of the present application. For example, in the original integrated circuit diagram, there are other wiring patterns in addition to the original wiring pattern X; alternatively, other types of data may exist in the original wiring pattern X, which is not particularly limited in the embodiment of the present application.

Referring to fig. 6, a schematic diagram of a mapping relationship between an original via X and a target via X is provided in an embodiment of the present application. As shown in fig. 6, the original data corresponding to the original via X includes coordinates, via names, rows, and columns. The coordinates of the original through hole X are the original data associated with the process, i.e., the coordinates in the original through hole X are the first original data. Therefore, in the data processing process, the coordinates of the original through hole X are multiplied by the process scaling factor to obtain the coordinates of the target through hole X. Of course, in some possible implementations, after multiplying the coordinates of the original through hole X by the process scaling factor, the coordinates may be rounded up or rounded down to be an integer multiple of the lattice step, which is not described in detail in the embodiments of the present application. The number of rows and the number of columns of the original through holes X are the same as those of the target through holes X, namely the number of rows and the number of columns of the original through holes X are second original data. Therefore, in the data processing process, the number of rows and columns of the original through holes X can be directly used as the number of rows and columns of the target through holes X, that is, the number of rows and columns of the original through holes X are not modified. The through hole name of the original through hole X corresponds to the through hole name of the target through hole X, i.e., the through hole name of the original through hole X is the third original data. Therefore, in the data processing process, the through hole name of the original through hole X may be replaced with the through hole name of the target through hole X according to the correspondence between the through hole name of the original through hole X and the through hole name of the target through hole X.

It should be noted that, in fig. 6, the mapping relationship between the original through hole X and the target through hole X is illustrated by taking the through hole X as an example, and should not be taken as a limitation of the protection scope of the present application. For example, there are other vias in the original integrated circuit diagram in addition to via X; alternatively, the via X may also include other types of data, which are not particularly limited in the embodiments of the present application.

Referring to fig. 7, a schematic diagram of a mapping relationship between an original tag X and a target tag X according to an embodiment of the present application is provided. As shown in fig. 7, the original data corresponding to the original tag X includes coordinates, height, tag text, and layer name. The coordinates and the heights of the original label X are the original data associated with the process, that is, the coordinates and the heights of the original label X are the first original data. Therefore, in the data processing process, the coordinates and the height of the original tag X are multiplied by the process scaling factor to obtain the coordinates and the height of the target tag X. Of course, in some possible implementations, after multiplying the coordinates and the height of the original label X by the process scaling factor, the original label X may be rounded up or rounded down to be an integer multiple of the lattice step, which is not described in detail in the embodiments of the present application. The tag characters of the original tag X are the same as those of the target tag X, namely the tag characters of the original tag X are the second original data. Therefore, in the data processing process, the tag text of the original tag X can be directly used as the tag text of the target tag X, i.e. the tag text of the original tag X is not modified. The layer name of the original label X corresponds to the layer name of the target label X, namely the layer name of the original label X is the third original data. Therefore, in the data processing process, the layer name of the original tag X can be replaced by the layer name of the target tag X according to the corresponding relationship between the layer name of the original tag X and the layer name of the target tag X.

It should be noted that, in fig. 7, the mapping relationship between the original tag X and the target tag X is illustrated by taking the tag X as an example, which should not be taken as a limitation of the protection scope of the present application. For example, there are other tags in the original integrated circuit diagram in addition to tag X; alternatively, tag X may also include other types of data, which are not particularly limited by the embodiments of the present application.

It can be appreciated that the above data processing processes are all implemented in the EDA tool, and after the integrated circuit diagram is migrated from the original process to the target process, class and attribute information of various objects (Pcell, wiring pattern, via, tag, etc.) in the original integrated circuit diagram can be maintained, so as to facilitate the designer to analyze and adjust the target integrated circuit diagram.

Step S103: and generating a target integrated circuit diagram according to the target data.

Specifically, after the original data conforming to the original process in the original integrated circuit diagram is replaced with the target data conforming to the target process, the target integrated circuit diagram can be generated according to the target data, and the migration of the original integrated circuit diagram from the original process to the target process is completed. It should be noted that the above steps S101-S103 are all implemented inside the EDA tool, so that class and attribute information of various objects (Pcell, wiring patterns, vias, tags, etc.) in the original integrated circuit diagram can be preserved.

In particular implementations, after the target integrated circuit diagram is generated, design rule verification (Design Rule Check, DRC) and layout circuit verification (Layout vs Schematic, LVS) may be performed on the target integrated circuit diagram. The DRC is used for carrying out design rule checking, such as line width checking, space checking and the like, on physical graphics in the layout so as to ensure normal manufacturing of the chip; the LVS is used for comparing the layout with the circuit netlist so as to ensure that the circuit which is sliced out is consistent with the circuit which is actually designed. The designer may modify the target integrated circuit diagram according to the verification results of DRC and LVS, which is not particularly limited in the embodiments of the present application.

Corresponding to the method embodiment, the embodiment of the application also provides a device for generating the integrated circuit diagram.

Referring to fig. 8, a block diagram of an apparatus for generating an integrated circuit diagram is provided in an embodiment of the present application. As shown in fig. 8, the apparatus includes:

A traversing unit 801, configured to traverse the original data in the original integrated circuit diagram.

An adjusting unit 802, configured to adjust the original data to the target data according to the mapping relationship between the original data and the target data.

And the generating unit 803 is configured to generate a target integrated circuit diagram according to the target data, where the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes.

Specifically, after the original data conforming to the original process in the original integrated circuit diagram is replaced with the target data conforming to the target process, the target integrated circuit diagram can be generated according to the target data, and the migration of the original integrated circuit diagram from the original process to the target process is completed.

In one possible implementation, the apparatus further includes: and the configuration unit is used for configuring the mapping relation between the original data and the target data according to the design process of the original integrated circuit diagram and the target integrated circuit diagram.

It should be noted that, for the sake of brevity, details of the device embodiments provided in the embodiments of the present application may be referred to in the description of the method embodiments described above, and are not described herein again.

Corresponding to the above embodiment, the present application also provides an electronic device.

Referring to fig. 9, a schematic structural diagram of an electronic device according to an embodiment of the present application is provided. As shown in fig. 9, the electronic device 900 may include: processor 901, memory 902, and communication unit 903. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the embodiments of the invention, and that it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.

Wherein, the communication unit 903 is configured to establish a communication channel, so that the storage device may communicate with other devices.

The processor 901 is a control center of the storage device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and/or processes data by running or executing software programs and/or modules stored in the memory 902 and calling data stored in the memory. The processor may be comprised of integrated circuits (integrated circuit, ICs), such as a single packaged IC, or may be comprised of packaged ICs that connect multiple identical or different functions. For example, the processor 901 may include only a central processing unit (central processing unit, CPU). In the embodiment of the invention, the CPU can be a single operation core or can comprise multiple operation cores.

The memory 902, for storing instructions for execution by the processor 901, the memory 902 may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

The execution of the instructions in memory 902, when executed by processor 901, enables electronic device 900 to perform some or all of the steps of the method embodiments described above.

In a specific implementation, the present application further provides a computer storage medium, where the computer storage medium may store a program, where the program may include some or all of the steps in the embodiments provided herein when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.

In a specific implementation, the embodiment of the application further provides a computer program product, where the computer program product contains executable instructions, and when the executable instructions are executed on a computer, the executable instructions cause the computer to perform some or all of the steps in the above method embodiments.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In several embodiments provided by the present invention, any of the functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely exemplary embodiments of the present invention, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present invention, which should be covered by the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of integrated circuit map generation, comprising:

importing the mapping relation between the original data and the target data to an EDA tool;

the original data comprises any one or more combinations of first original data and second original data; the target data comprises any one or more combinations of first target data and second target data; the mapping relation comprises the following steps: when the original data is first original data, scaling the first original data according to a process scaling factor between an original integrated circuit diagram and a target integrated circuit diagram to obtain intermediate data, and rounding up or rounding down the intermediate data to be integral multiples of a lattice step length according to the lattice step length of the target integrated circuit diagram to obtain first target data; when the original data is second original data, the second original data in the original integrated circuit diagram and second target data in the target integrated circuit diagram are kept the same; the second original data comprises a rotation value and/or a device name;

Traversing raw data in a raw integrated circuit diagram in the EDA tool;

according to the mapping relation between the original data and the target data in the EDA tool, the original data is adjusted to be the target data;

and generating a target integrated circuit diagram in the EDA tool according to the target data.

2. The method of claim 1, wherein the original integrated circuit map and the target integrated circuit map correspond to one or more combinations of different process design suites PDK, device property profiles CDF, layer matching files Layermap.

3. The method of claim 1, wherein the rounding up or rounding down the intermediate data to an integer multiple of the lattice step size according to the lattice step size of the target integrated circuit graph, to obtain the first target data, comprises:

4. The method of claim 1, wherein the original integrated circuit diagram includes third original data, and the third original data in the original integrated circuit diagram corresponds to third target data in the target integrated circuit diagram, and wherein adjusting the original data to the target data according to a mapping relationship between the original data and the target data includes:

5. The method of claim 1, wherein prior to adjusting the original data to target data according to a mapping relationship of the original data and the target data, the method further comprises:

6. The method according to any one of claims 1 to 5, wherein,

the original data comprise original parameterized cell data, original connection line graph data, original through hole data and/or original label data;

7. An apparatus for generating an integrated circuit map, comprising:

an importing unit for importing the mapping relation of the original data and the target data to the EDA tool;

A traversing unit for traversing the raw data in the raw integrated circuit diagram in the EDA tool;

the adjusting unit is used for adjusting the original data into target data according to the mapping relation between the original data and the target data in the EDA tool;

and the generating unit is used for generating a target integrated circuit diagram in the EDA tool according to the target data, wherein the original integrated circuit diagram and the target integrated circuit diagram correspond to different design processes.

8. The apparatus of claim 7, wherein the apparatus further comprises:

9. An electronic device, comprising:

a processor;

a memory;

and a computer program, wherein the computer program is stored in the memory, the computer program comprising instructions that, when executed by the processor, cause the electronic device to perform the method of any one of claims 1 to 6.

10. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored program, wherein the program when run controls a device in which the computer readable storage medium is located to perform the method according to any one of claims 1 to 6.