CN115277499B

CN115277499B - Delay parameter determination method and device of MAC (media access control) equipment, hardware platform and medium

Info

Publication number: CN115277499B
Application number: CN202210859600.8A
Authority: CN
Inventors: 张一弘; 程茂; 彭元志; 毛玉泽; 栾学广
Original assignee: Kedong Guangzhou Software Technology Co Ltd
Current assignee: Kedong Guangzhou Software Technology Co Ltd
Priority date: 2022-07-20
Filing date: 2022-07-20
Publication date: 2023-07-11
Anticipated expiration: 2042-07-20
Also published as: CN115277499A

Abstract

The invention discloses a delay parameter determining method, a device, a hardware platform and a medium of MAC equipment. The method comprises the following steps: controlling MAC equipment in a hardware platform to be tested to perform closed-loop receiving and transmitting test under a plurality of alternative delay parameters, and acquiring test results corresponding to each alternative delay parameter; in the hardware platform to be tested, the MAC equipment is connected with the PHY equipment through an Ethernet media interface, and the alternative delay parameters comprise a sending clock delay and a receiving clock delay; arranging the test results according to the numerical relation among the alternative delay parameters to obtain a result matrix, and acquiring a stable test result according to the difference among the test results in the result matrix; and acquiring target alternative delay parameters matched with the stable test result, and performing clock offset soft setting on the MAC equipment by using the target alternative delay parameters. By adopting the technical scheme, the delay parameter optimization in the clock offset soft setting of the MAC equipment can be ensured.

Description

Delay parameter determination method and device of MAC (media access control) equipment, hardware platform and medium

Technical Field

The present invention relates to the field of computer communications technologies, and in particular, to a method, an apparatus, a hardware platform, and a medium for determining a delay parameter of a MAC device.

Background

The MAC (Media Access Control, media access control Layer) and PHY (Physical Layer) of the ethernet are connected through an ethernet media interface, but when the ethernet media interface establishes communication, a clock edge and a data edge are synchronously turned over, so that a receiving end cannot stably sample. Therefore, in order to ensure stable sampling at the receiving end, a proper delay time is required to be added to the clock signal.

The existing clock delay method mainly comprises two methods of hardware delay and software delay. The hardware method is to increase the routing amount of the PCB (Printed Circuit Board ), and the software method is to perform soft setting of clock offset in the MAC or PHY through corresponding parameters calculated by engineers for different hardware.

However, the existing hardware method has large resource consumption, in the existing software method, the same set of software can only work on the same set of hardware platform, and when different hardware individuals in the same set of hardware platform have differences, the delay effect of the clock signal can be influenced.

Disclosure of Invention

The invention provides a delay parameter determining method, a device, a hardware platform and a medium of MAC equipment, which can ensure the optimization of delay parameters in clock offset soft setting of the MAC equipment.

According to an aspect of the present invention, there is provided a delay parameter determining method of a MAC device, the method including:

controlling MAC equipment in a hardware platform to be tested to perform closed-loop receiving and transmitting test under a plurality of alternative delay parameters, and acquiring test results corresponding to each alternative delay parameter;

in the hardware platform to be tested, the MAC equipment is connected with the PHY equipment through an Ethernet media interface, and the alternative delay parameters comprise a sending clock delay and a receiving clock delay;

arranging the test results according to the numerical relation among the alternative delay parameters to obtain a result matrix, and acquiring a stable test result according to the difference among the test results in the result matrix;

and acquiring target alternative delay parameters matched with the stable test result, and performing clock offset soft setting on the MAC equipment by using the target alternative delay parameters.

According to another aspect of the present invention, there is provided a delay parameter determining apparatus of a MAC device, including:

the test result acquisition module is used for controlling the MAC equipment in the hardware platform to be tested to carry out closed-loop receiving and transmitting test under a plurality of alternative delay parameters and acquiring test results corresponding to the alternative delay parameters;

In the hardware platform to be tested, the MAC equipment is connected with the physical layer PHY equipment through an Ethernet media interface, and the alternative delay parameters comprise a sending clock delay and a receiving clock delay;

the stable test result acquisition module is used for arranging the test results according to the numerical relation among the alternative delay parameters to obtain a result matrix, and acquiring a stable test result according to the difference among the test results in the result matrix;

and the soft setting module is used for acquiring target alternative delay parameters matched with the stable test result and performing soft setting of clock offset on the MAC equipment by using the target alternative delay parameters.

According to another aspect of the present invention, there is provided a hardware platform, where the hardware platform includes a media access control layer MAC device and a physical layer device, where the MAC device is connected to the PHY device through an ethernet media interface;

on the hardware platform, at least one processor is configured; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method for determining a delay parameter of a MAC device according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the method for determining a delay parameter of a MAC device according to any one of the embodiments of the present invention when executed.

According to the technical scheme, the closed loop transceiving test results of the MAC equipment in the hardware platform to be tested under the multiple alternative delay parameters are obtained and are arranged to obtain the result matrix, the dense successful result area is divided in the result matrix, the stable test result is determined, the matched target alternative delay parameters are obtained to carry out the soft setting of clock offset on the MAC equipment, the obtained target alternative delay parameters can be optimized, and the communication effect between the MAC equipment and the PHY equipment can be effectively improved after the target alternative delay parameters are used for the soft setting of clock offset.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a delay parameter determining method of a MAC device according to a first embodiment of the present invention;

fig. 2a is a flowchart of a delay parameter determining method of a MAC device according to a second embodiment of the present invention;

FIG. 2b is a schematic diagram of the partitioning of a dense successful result area provided in an embodiment of the present invention;

FIG. 2c is a schematic diagram of the central location partitioning of a dense successful result area provided in an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a delay parameter determining apparatus of a MAC device according to a third embodiment of the present invention;

fig. 4 is a schematic structural diagram of a hardware platform for implementing a delay parameter determining method of a MAC device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a method for determining a delay parameter of a MAC device according to an embodiment of the present invention, where the method may be performed by a delay parameter determining apparatus of a MAC device, and the delay parameter determining apparatus of the MAC device may be implemented in hardware and/or software, and the delay parameter determining apparatus of the MAC device may be configured in a computer or a server having a data processing function, where the MAC device is connected to a PHY device through an ethernet media interface. As shown in fig. 1, the method includes:

S110, controlling MAC equipment in the hardware platform to be tested to carry out closed loop receiving and transmitting test under a plurality of alternative delay parameters, and obtaining test results corresponding to each alternative delay parameter.

In the hardware platform to be tested, the MAC device is connected with the PHY device through an Ethernet media interface, and the alternative delay parameters comprise a sending clock delay and a receiving clock delay.

As described above, when the MAC device and the PHY device are connected through the ethernet media interface in the hardware platform, the clock edge and the data edge are turned synchronously, so that the clock edge can be aligned to the stable interval of the data bus through performing soft setting of the transmit clock delay and the receive clock delay in the MAC.

That is, a clock offset of a transmission clock delay is added to a pin corresponding to a transmission clock signal inside the MAC device, and a clock offset of a reception clock delay is added to a pin corresponding to a reception clock signal inside the MAC device.

Accordingly, a transmit clock delay may be understood as the delay time of a transmit clock edge relative to a transmit data edge, and a receive clock delay may be understood as the delay time of a receive clock edge relative to a receive data edge.

In the prior art, the sending clock delay and the receiving clock delay are calculated for each independent hardware platform by a hardware engineer, and the sending clock delay and the receiving clock delay are solidified into the MAC equipment as initialization parameters. In this embodiment, the inventor creatively proposes a general implementation method capable of determining optimal sending clock delay and receiving clock delay for the MAC device in any hardware platform, so as to thoroughly avoid the investment of labor cost of hardware engineers.

The closed loop transceiving test can be understood as that after the MAC device sends a data packet to the PHY device, the MAC device verifies whether the whole communication process is sequentially performed by verifying whether the sent data packet can be successfully received after returning to the MAC device again through the PHY device. It can be understood that when the delay of the sending clock and the delay of the receiving clock in a certain alternative delay parameter are selected reasonably, after the alternative delay parameter is used for soft setting of the MAC device, the communication process can be completed normally; otherwise, the communication process cannot be completed normally.

In this embodiment, by controlling the MAC device in the hardware platform to be tested to perform the closed loop transceiving test under the multiple alternative delay parameters and obtaining the test results corresponding to the alternative delay parameters, it is possible to first screen which specific alternative delay parameters in the multiple alternative delay parameters are available for performing soft setting of the MAC device.

Alternatively, the above-mentioned multiple candidate delay parameters may be obtained in advance through actual experience, or all possible combinations of the transmission clock delay and the reception clock delay may be traversed in the whole range of values according to the range of values of the transmission clock delay and the reception clock delay, which is not limited in this embodiment as the candidate delay parameters.

In a specific example, the plurality of alternative delay parameters may be constructed from a transmit clock delay interval, a transmit delay increment step, a receive clock delay interval, and a receive delay increment step.

Accordingly, the test results corresponding to each of the alternative delay parameters may be test results of successful communications or test results of failed communications. The test result of successful communication may be understood that the MAC device successfully receives the same received data packet as the transmitted data packet within the effective communication time, and the test result of failed communication may be understood that the MAC device does not successfully receive the data packet within the effective communication time, or that the error rate of the received data packet is higher than that of the transmitted data packet.

S120, arranging the test results according to the numerical relation among the alternative delay parameters to obtain a result matrix, and obtaining a stable test result according to the difference among the test results in the result matrix.

The stable test result is a test result of successful communication, and the stable test result can be understood that the test result will not change after a certain delay deviation occurs between the sending clock delay and the receiving clock delay in the alternative delay parameters corresponding to the test result.

It can be understood that after the test results corresponding to each alternative delay parameter are obtained, all the test results of successful communication can be screened out from the test results, and then one test result can be randomly selected from the test results of successful communication, and the alternative delay parameter corresponding to the test result is used for performing clock offset soft setting on the MAC device.

However, the inventor further considers that if there is a test result of communication failure among test results of one or more alternative delay parameters adjacent to the alternative delay parameter selected for soft setting, in subsequent use, the communication effect of the MAC device may be responded due to various environmental factors or hardware aging factors, etc. Therefore, the alternative delay parameter for performing soft setup requires selecting a stable test result from all the test results of successful communication, so as to ensure that the test results within a certain range around the stable test result are all the test results of successful communication.

Accordingly, the sending clock delay and the receiving clock delay in the alternative delay parameters can be respectively sequenced in two dimensions according to the sequence from big to small (or from small to big), and the test results are organized according to the sequencing results to obtain a result matrix, for example, the test result of successful communication is set to be 1, the test result of failed communication is set to be 0, and the like, so that the stable test result can be selected according to the space arrangement rule of the test results of each successful communication in the result matrix.

Accordingly, in an optional implementation manner of this embodiment, the arranging the test results according to the numerical relation between the candidate delay parameters to obtain the result matrix may include:

determining the total number of the transmission clock delays according to the transmission clock delay interval and the transmission delay increment step length, and determining the total number of the reception clock delays according to the reception clock delay interval and the reception delay increment step length; constructing a two-dimensional matrix according to the total number of the sending clock delays and the total number of the receiving clock delays; and taking the arrangement sequence of the delay edges of the sending clock and the receiving clock from small to large as the arrangement sequence of row and column elements in the two-dimensional matrix, and filling each test result into the two-dimensional matrix to obtain a result matrix.

According to the difference among the test results in the result matrix, the obtaining of the stable test result may include:

acquiring a dense successful result area consisting of a plurality of successfully communicated test results in the result matrix; and determining matrix elements matched with the central positions of the densely successful result areas as stable test results.

S130, acquiring target alternative delay parameters matched with the stable test result, and performing clock offset soft setting on the MAC equipment by using the target alternative delay parameters.

Specifically, the delay time of the sending clock and the delay time of the receiving clock matched with the stable test result are obtained as target alternative delay parameters, clock delay software in the MAC equipment is configured by using the target alternative delay parameters, and the soft setting of clock offset is completed.

In an alternative implementation of this embodiment, the ethernet media interface may be an RGMII (Reduced Gigabit Media Independent Interface, gigabit media independent interface).

Correspondingly, the communication mode between the MAC equipment and the PHY equipment is as follows: through RGMII communication, the MAC device transmits the data packet and the corresponding clock signal to the PHY device through RGMII, and the PHY device can convert the received data packet and then further transmit the data packet outwards; similarly, after receiving the data packet sent from the outside, the PHY device performs conversion processing, and sends the processed data packet and a corresponding clock signal to the MAC device through RGMII.

Example two

Fig. 2a is a flowchart of a delay parameter determining method of a MAC device according to a second embodiment of the present invention, where based on the foregoing embodiment, the method includes performing closed loop transceiving test on a MAC device in a hardware platform to be tested under a plurality of alternative delay parameters, and obtaining test results corresponding to each alternative delay parameter, and embodying the test results to construct a plurality of alternative delay parameters according to a transmission clock delay interval, a transmission delay increment step size, a reception clock delay interval, and a reception delay increment step size; after performing soft setting of clock offset on the MAC equipment by using each alternative delay parameter, controlling the MAC equipment to send a target test data packet in a closed loop mode; and acquiring test results of successful or failed communication corresponding to each alternative delay parameter according to the receiving condition of the target test data packet of the MAC equipment under each alternative delay parameter.

Meanwhile, a dense successful result area formed by a plurality of successful communication test results is obtained in the result matrix, and is embodied in the result matrix, the longest continuous successful result row sequence corresponding to each matrix row is obtained in a traversing mode, and each continuous successful result row sequence is formed by a plurality of continuous successful communication test results; acquiring a start column clock delay and a stop column clock delay respectively corresponding to each longest continuous successful result row sequence; selecting a plurality of continuous target matrix rows to form an alternative area according to the initial column clock delay and the final column clock delay; acquiring the maximum initial column clock delay and the minimum termination column clock delay from the initial column clock delay and the termination column clock delay of each target matrix row; a dense successful result region is partitioned in the candidate region using a maximum starting column clock delay and a minimum ending column clock delay.

Accordingly, as shown in fig. 2a, the method comprises:

s210, constructing a plurality of alternative delay parameters according to the transmission clock delay interval, the transmission delay increment step length, the receiving clock delay interval and the receiving delay increment step length.

The debugger can determine a transmission clock delay interval, a transmission delay increment step length, a reception clock delay interval and a reception delay increment step length according to historical experience, and according to the transmission delay increment step length and the reception delay increment step length, all delay time meeting the corresponding increment step length in the transmission clock delay interval and the reception clock delay interval is taken as transmission clock delay time and reception clock delay time, and each transmission clock delay time and each reception clock delay time are combined in pairs to be taken as an alternative delay parameter, but the method is not limited to a construction mode of the alternative delay parameter.

By way of example, if the transmit clock delay interval of the MAC device is between 2ns (nanoseconds) and 7ns and the transmit delay increment step is 1ns, the transmit clock delay times may be 2ns, 3ns, 4ns, 5ns, 6ns, and 7ns; if the receive clock delay interval of the MAC device is between 4ns and 6.5ns and the receive delay increment step is 0.5ns, then the receive clock delay times may be 4ns, 4.5ns, 5ns, 5.5ns, 6ns, and 6.5ns. Further, the selection of the alternative delay parameters may be as shown in table 1, where each blank cell in table 1 represents an alternative delay parameter, such as the second row and the second column, that is, represents that the alternative delay parameter is 2ns for transmission delay and 4ns for reception delay.

TABLE 1

S220, performing clock offset soft setting on the MAC equipment by using each alternative delay parameter.

After constructing the alternative delay parameters, a soft setting of the clock offset with each alternative delay parameter may be performed in the MAC device.

And S230, the control MAC device sends the target test data packet to the PHY device in a closed loop mode through the Ethernet media interface.

Optionally, the controlling the MAC device to send the target test packet in a closed loop manner may specifically include:

and the control MAC device sends the target test data packet to the PHY device through the Ethernet media interface, wherein the communication mode of the PHY device is preset to be a loop mode.

The loop back mode of the PHY device can be understood as: after the MAC device sends the data packet to the PHY device, the PHY does not perform external forwarding work, but directly returns the received data packet to the MAC device after processing, namely, a communication loop between the MAC device and the PHY device is formed.

The data length of the target test data packet can be preset according to actual conditions, so long as the data length is not larger than the maximum data unit which can be transmitted by the MAC device. In practical application, the data length of the target test data packet can be directly set as the maximum data unit which can be transmitted by the MAC equipment.

The purpose of selecting the largest data unit that can be transmitted by the MAC device as the target test data in the target test data packet is to: and when the target delay parameter is tested, selecting the maximum data unit for transmission, and if the maximum data unit still keeps the data information intact in the data packet returned by the PHY finally received by the MAC equipment, proving that the selected target delay parameter can support any data packet sent or received by the MAC equipment.

S240, according to the receiving condition of the target test data packet of the MAC equipment under each alternative delay parameter, obtaining the test result of successful or failed communication corresponding to each alternative delay parameter.

As described above, if the data packet received by the MAC device is the same as the data information of the transmitted target test data packet, the selected alternative delay parameter representing the test can be successfully communicated, and similarly, if the data packet received by the MAC device is different from the data information of the transmitted target test data packet or cannot be successfully received, the selected alternative delay parameter representing the test leads to communication failure.

The advantages of this arrangement are that: the MAC equipment is controlled to perform the test in a closed-loop mode, so that the test efficiency can be improved, and the accuracy of the test result can be improved by selecting the maximum data unit which can be transmitted by the MAC equipment as the target test data in the target test data packet.

S250, determining the total number of the sending clock delays according to the sending clock delay interval and the sending delay increment step length, and determining the total number of the receiving clock delays according to the receiving clock delay interval and the receiving delay increment step length.

Illustratively, the description continues in this step with the alternative delay parameters shown in Table 1. As shown in table 1, the total number of transmit clock delays is 6 and the total number of receive clock delays is 6.

S260, constructing a two-dimensional matrix according to the total number of the sending clock delays and the total number of the receiving clock delays.

In the previous example, if the total number of transmit clock delays is 6 and the total number of receive clock delays is 6, a two-dimensional matrix of 6*6 can be constructed. The present embodiment is not limited to this, and the total number of transmission clock delays may be used as the number of row elements of the two-dimensional matrix, the total number of reception clock delays may be used as the number of column elements of the two-dimensional matrix, or the total number of transmission clock delays may be used as the number of column elements of the two-dimensional matrix, and the total number of reception clock delays may be used as the number of row elements of the two-dimensional matrix.

S270, taking the arrangement sequence of the delay edge of the sending clock and the delay edge of the receiving clock from small to large as the arrangement sequence of row and column elements in the two-dimensional matrix, and filling each test result into the two-dimensional matrix to obtain a result matrix.

Optionally, if the test result is successful communication, filling the corresponding position in the two-dimensional matrix with 1; if the test result is failure communication, the corresponding position in the two-dimensional matrix can be filled with 0. The arrangement order of the row and column elements in the two-dimensional matrix may refer to the transmission clock delay and the reception clock delay order in the first row and the first column in table 1.

By way of example, an alternative result matrix may be represented in the form:

s280, traversing and acquiring the longest continuous successful result row sequence corresponding to each matrix row in the result matrix, wherein each continuous successful result row sequence consists of a plurality of continuous successful communication test results.

The result matrix shown in the previous example, the longest continuous successful result row sequence corresponding to the first row is a third column of the first row, a fourth column of the first row and a fifth column of the first row; the longest continuous successful result row sequence corresponding to the second row is a second row, a second column, a second row, a third column, a second row, a fourth column and a second row, a fifth column; the acquisition mode of the longest continuous successful result row corresponding to each other matrix row is the same as the mode.

S290, acquiring a start column clock delay and a stop column clock delay corresponding to each longest continuous successful result row sequence respectively.

Further, the initial column clock delay corresponding to the longest continuous successful result line of the above result matrix is 4ns, the final column clock delay corresponding to the longest continuous successful result line of the second row is 6ns, the initial column clock delay corresponding to the longest continuous successful result line of the above result matrix is 3ns, the final column clock delay is 6ns, and the acquisition manners of the initial column clock delay and the final column clock delay corresponding to the longest continuous successful result line of other matrix lines are the same as the above manners.

S2100, selecting a plurality of continuous target matrix rows to form an alternative area according to each initial column clock delay and each final column clock delay.

The initial column clock delay difference value and the final column clock delay difference value between the target matrix rows are both within a preset threshold.

Further, if the threshold value of the start column clock delay difference value is preset to 1ns and the threshold value of the end column clock delay difference value is preset to 2ns, the first row, the fourth row, the fifth row and the sixth row cannot be in the same candidate region because the start column clock delay difference value needs to be compared two by two for the longest consecutive successful result rows in the candidate region. The matrix may be formed into two candidate regions meeting the requirements, the first being a candidate region formed by the longest consecutive successful result lines of the first row to the third row and the second being a candidate region formed by the longest consecutive successful result lines of the second row to the fifth row.

Further, the candidate region containing the most test results may be selected as the candidate region eventually used for dividing the densely successful result region, and thus, the present embodiment selects the candidate region composed of the longest consecutive successful result rows of the second row to the fifth row as the candidate region eventually used for dividing the densely successful result region, but is not limited to the above selection manner, and the selection manner of the candidate region is not limited herein.

S2110, the maximum start column clock delay and the minimum end column clock delay are acquired from among the start column clock delay and the end column clock delay of each target matrix row.

S2120, using the maximum starting column clock delay and the minimum ending column clock delay, a dense successful result region is partitioned in the candidate region.

Further, a maximum starting column clock delay and a minimum ending column clock delay may be used in the candidate region to partition a dense successful result region. For ease of understanding, an alternative partitioning diagram of the dense successful result area is shown in FIG. 2 b. As shown in fig. 2b, the solid line area represents an alternative area for dividing the densely successful result area, and the dotted line area represents the finally divided densely successful result area.

S2130, determining a matrix element matching the center position of the dense successful result area as a stable test result.

It can be understood that the matrix element at the central position of the dense successful result area is selected to be used as a stable test result, and the stability of communication can be ensured to the greatest extent even if a certain deviation is generated in the delay time in the actual clock delay software application process.

An alternative central location partitioning diagram of the dense successful result area is shown in fig. 2 c. As shown in fig. 2c, the solid line area is a dense successful result area, and the intersection point of the broken lines is the center position of the dense successful result area. In this embodiment, the center position of the intensive success result is located between four matrix elements, and under the condition that a specific matrix element cannot be acquired, a tester can preset an algorithm in clock delay software according to historical experience, and can select one matrix element from the four matrix elements; if the intersection point is located on a matrix element in the dense successful result area, the matrix element is selected.

The advantages of this arrangement are that: by adopting the stable test result acquisition mode provided by the embodiment of the invention, a relatively stable test result can be acquired, and when the target alternative delay parameter matched with the acquired stable test result is applied to clock delay software, the stability of communication between the MAC equipment and the PHY equipment can be improved.

S2140, obtaining a target alternative delay parameter matched with the stable test result, and performing clock offset soft setting on the MAC equipment by using the target alternative delay parameter.

According to the technical scheme provided by the embodiment of the invention, the MAC equipment is controlled to test in a closed-loop mode by selecting the maximum data unit which can be transmitted by the MAC equipment as the target test data in the target test data packet, so that the test efficiency can be improved and the accuracy of the test result can be improved.

Example III

Fig. 3 is a schematic structural diagram of a delay parameter determining apparatus of a MAC device according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: a test result acquisition module 310, a stable test result acquisition module 320, and a soft setup module 330.

The test result obtaining module 310 is configured to control the MAC device in the hardware platform to be tested to perform a closed loop transceiving test under a plurality of alternative delay parameters, and obtain a test result corresponding to each alternative delay parameter.

The stable test result obtaining module 320 is configured to arrange each test result according to a numerical relation between each candidate delay parameter, obtain a result matrix, and obtain a stable test result according to a difference between each test result in the result matrix.

The soft setting module 330 is configured to obtain a target alternative delay parameter that matches the stability test result, and perform soft setting of clock offset on the MAC device using the target alternative delay parameter.

Based on the above embodiments, the test result obtaining module 310 may include:

an alternative delay parameter construction unit, configured to construct a plurality of alternative delay parameters according to a transmission clock delay interval, a transmission delay increment step size, a reception clock delay interval, and a reception delay increment step size;

the target test data packet sending unit is used for controlling the MAC equipment to send the target test data packet in a closed loop mode after performing soft setting of clock offset on the MAC equipment by using each alternative delay parameter;

The test result acquisition unit is used for acquiring test results of successful or failed communication corresponding to each alternative delay parameter according to the receiving condition of the target test data packet of the MAC equipment under each alternative delay parameter.

On the basis of the above embodiments, the target test packet sending unit may be specifically configured to:

the control MAC device sends the target test data packet to the PHY device through the Ethernet media interface;

wherein the communication mode of the PHY device is preset to a loop mode.

Based on the above embodiments, the stability test result obtaining module 320 may include: and a result matrix acquisition unit and a stable test result acquisition unit.

On the basis of the above embodiments, the result matrix acquiring unit may be specifically configured to:

determining the total number of the transmission clock delays according to the transmission clock delay interval and the transmission delay increment step length, and determining the total number of the reception clock delays according to the reception clock delay interval and the reception delay increment step length;

constructing a two-dimensional matrix according to the total number of the sending clock delays and the total number of the receiving clock delays;

and taking the arrangement sequence of the delay edges of the sending clock and the receiving clock from small to large as the arrangement sequence of row and column elements in the two-dimensional matrix, and filling each test result into the two-dimensional matrix to obtain a result matrix.

On the basis of the above embodiments, the stability test result obtaining unit may include:

a dense successful result area acquisition subunit, configured to acquire, in the result matrix, a dense successful result area composed of a plurality of test results of successful communications;

and the stable test result acquisition subunit is used for determining matrix elements matched with the central positions of the intensive successful result areas as stable test results.

Based on the above embodiments, the dense successful result area acquisition subunit may be specifically configured to:

traversing to obtain the longest continuous successful result line sequence corresponding to each matrix line in the result matrix, wherein each continuous successful result line sequence consists of a plurality of continuous successful communication test results;

acquiring a start column clock delay and a stop column clock delay respectively corresponding to each longest continuous successful result row sequence;

selecting a plurality of continuous target matrix rows to form an alternative area according to the initial column clock delay and the final column clock delay;

the initial column clock delay difference value and the final column clock delay difference value between the target matrix rows are both within a preset threshold;

Acquiring the maximum initial column clock delay and the minimum termination column clock delay from the initial column clock delay and the termination column clock delay of each target matrix row;

a dense successful result region is partitioned in the candidate region using a maximum starting column clock delay and a minimum ending column clock delay.

Based on the above embodiments, the data length of the target test data packet is the maximum data unit that can be transmitted by the MAC device;

and/or, the Ethernet media interface is RGMII.

The delay parameter determining device of the MAC equipment provided by the embodiment of the invention can execute the delay parameter determining method of the MAC equipment provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the executing method.

Example IV

Fig. 4 shows a schematic diagram of a hardware platform 40 that may be used to implement an embodiment of the present invention. Hardware platforms are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The hardware platform may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the hardware platform 40 includes at least one processor 41, and a memory communicatively connected to the at least one processor 41, such as a Read Only Memory (ROM) 42, a Random Access Memory (RAM) 43, etc., in which the memory stores a computer program executable by the at least one processor, and the processor 41 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 42 or the computer program loaded from the storage unit 48 into the Random Access Memory (RAM) 43. In the RAM43, various programs and data required for the operation of the hardware platform 40 may also be stored. The processor 41, the ROM42 and the RAM43 are connected to each other via a bus 44. An input/output (I/O) interface 45 is also connected to bus 44.

Various components in hardware platform 40 are connected to I/O interface 45, including: an input unit 46 such as a keyboard, a mouse, etc.; an output unit 47 such as various types of displays, speakers, and the like; a storage unit 48 such as a magnetic disk, an optical disk, or the like; and a communication unit 49 such as a network card, modem, wireless communication transceiver, etc. The communication unit 49 allows the hardware platform 40 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

The processor 41 may be various general and/or special purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as the delay parameter determination method of the MAC device as described in the embodiments of the present invention. Namely:

In some embodiments, the delay parameter determination method of the MAC device may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 48. In some embodiments, part or all of the computer program may be loaded and/or installed onto the hardware platform 40 via the ROM42 and/or the communication unit 49. When the computer program is loaded into the RAM43 and executed by the processor 41, one or more steps of the above-described delay parameter determination method of the MAC device may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the delay parameter determination method of the MAC device by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a hardware platform having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or a trackball) through which a user can provide input to the hardware platform. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method for determining a delay parameter of a medium access control layer MAC device, comprising:

acquiring target alternative delay parameters matched with the stable test result, and performing soft setting of clock offset on the MAC equipment by using the target alternative delay parameters;

wherein, according to the difference between each test result in the result matrix, obtain the stable test result, include:

acquiring a dense successful result area consisting of a plurality of successfully communicated test results in the result matrix;

determining matrix elements matched with the central position of the intensive successful result area as stable test results;

Wherein, in the result matrix, a dense successful result area composed of a plurality of successfully communicated test results is obtained, comprising:

2. The method of claim 1, wherein controlling the MAC device in the hardware platform under test to perform the closed loop transmit-receive test under the plurality of alternative delay parameters and obtaining the test result corresponding to each alternative delay parameter comprises:

Constructing a plurality of alternative delay parameters according to the transmission clock delay interval, the transmission delay increment step length, the receiving clock delay interval and the receiving delay increment step length;

after performing soft setting of clock offset on the MAC equipment by using each alternative delay parameter, controlling the MAC equipment to send a target test data packet in a closed loop mode;

and acquiring test results of successful or failed communication corresponding to each alternative delay parameter according to the receiving condition of the target test data packet of the MAC equipment under each alternative delay parameter.

3. The method of claim 2, wherein controlling the MAC device to transmit the targeted test data packet in a closed loop manner comprises:

wherein the communication mode of the PHY device is preset to a loop mode.

4. The method of claim 2, wherein ranking the test results according to a numerical relationship between the candidate delay parameters to obtain a result matrix comprises:

5. The method according to any of claims 2-4, wherein the data length of the target test packet is the maximum data unit that can be transmitted by the MAC device;

and/or, the Ethernet media interface is a gigabit media independent interface RGMII.

6. A delay parameter determining apparatus of a medium access control layer MAC device, comprising:

The soft setting module is used for acquiring target alternative delay parameters matched with the stable test result and performing soft setting of clock offset on the MAC equipment by using the target alternative delay parameters;

the stable test result acquisition module may include a test result acquisition unit;

wherein, test result acquisition unit includes:

a stable test result obtaining subunit, configured to determine, as a stable test result, a matrix element that matches the center position of the dense successful result area;

the dense successful result area obtaining subunit is specifically configured to:

7. The hardware platform is characterized by comprising a media access control layer (MAC) device and a physical layer device, wherein the MAC device is connected with the PHY device through an Ethernet media interface;

on the hardware platform, at least one processor is configured; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of determining a delay parameter of a MAC device as claimed in any one of claims 1 to 5.

8. A computer readable storage medium storing computer instructions for causing a processor to perform the method of determining a delay parameter of a MAC device as claimed in any one of claims 1 to 5.