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CN115206897A - 包括模制层的半导体封装件 - Google Patents

包括模制层的半导体封装件 Download PDF

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Publication number
CN115206897A
CN115206897A CN202210360930.2A CN202210360930A CN115206897A CN 115206897 A CN115206897 A CN 115206897A CN 202210360930 A CN202210360930 A CN 202210360930A CN 115206897 A CN115206897 A CN 115206897A
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CN
China
Prior art keywords
semiconductor chip
substrate
disposed
semiconductor
package
Prior art date
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Pending
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CN202210360930.2A
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English (en)
Inventor
柳慧桢
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN115206897A publication Critical patent/CN115206897A/zh
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Abstract

一种半导体封装件包括：第一半导体芯片，其具有安装区域和外伸区域；基板，其设置在第一半导体芯片的安装区域处的底表面上；以及模制层，其设置在基板上。模制层包括：第一模制图案，其设置在第一半导体芯片的外伸区域处的底表面上并且覆盖基板的侧壁；以及第二模制图案，其在第一模制图案上并且覆盖第一半导体芯片的侧壁。

Description

包括模制层的半导体封装件
相关申请的交叉引用
本申请要求于2021年4月9日在韩国知识产权局提交的韩国专利申请No.10-2021-0046425的优先权，其公开内容以引用方式全部并入本文中。
技术领域
本发明构思涉及半导体封装件，更具体地，涉及一种包括模制层的半导体封装件。
背景技术
半导体集成电路芯片通常设置在半导体封装件内以保护集成电路芯片并帮助它们连接到电子产品。通常，半导体封装件被配置为使得半导体芯片安装在印刷电路板(PCB)上并且使用接合引线或凸块将半导体芯片电连接到印刷电路板。
发明内容
一种半导体封装件包括：第一半导体芯片，其具有安装区域和外伸区域；基板，其在第一半导体芯片的安装区域处的底表面上；以及模制层，其在基板上。模制层包括：第一模制图案，其设置在第一半导体芯片的外伸区域处的底表面上并且覆盖基板的侧壁；以及第二模制图案，其设置在第一模制图案上并且覆盖第一半导体芯片的侧壁。
一种半导体封装件包括：插入基板；第一半导体芯片，其设置在插入基板上；以及模制层，其覆盖插入基板的侧壁。第一半导体芯片包括外伸区域和安装区域。模制层设置在第一半导体芯片的外伸区域处的底表面上。模制层的底表面与插入基板的底表面共面。
一种半导体封装件包括：插入基板；多个焊料端子，其设置在插入基板的底表面上；芯片堆叠件，其设置在插入基板的顶表面上，该芯片堆叠件包括第一下半导体芯片和设置在第一下半导体芯片上的多个第一上半导体芯片；多个第一凸块，其设置在插入基板和第一下半导体芯片之间；以及模制层，其设置在插入基板上。第一下半导体芯片在其中包括多个贯通电极。插入基板包括半导体晶片、多个通孔、多个布线结构和多个插入焊盘。第一下半导体芯片包括：安装区域，其设置在插入基板上；以及外伸区域，其与插入基板间隔开。模制层包括：第一模制图案，其设置在第一下半导体芯片的外伸区域处的底表面上并且覆盖插入基板的侧壁；以及第二模制图案，其设置在第一模制图案上并且覆盖第一下半导体芯片的侧壁和多个第一上半导体芯片的侧壁。第一模制图案的热膨胀系数大于半导体晶片的热膨胀系数。
附图说明
当结合附图考虑时，由于通过参考以下详细描述，本公开及其许多附带方面变得更好理解，因此将更容易获得本公开及其许多附带方面的更完整的理解，在附图中：
图1A是示出根据本公开的实施方式的半导体封装件的平面图；
图1B是沿着图1A的线I-I’截取的截面图；
图1C是示出图1B的区段A的放大图；
图2A是示出根据本公开的实施方式的半导体封装件的平面图；
图2B是沿着图2A的线II-II’截取的截面图；
图2C是示出根据本公开的实施方式的半导体封装件的截面图；
图2D是示出根据本公开的实施方式的半导体封装件的截面图；
图3是示出根据本公开的实施方式的半导体封装件的截面图；
图4A是示出根据本公开的实施方式的半导体封装件的截面图；
图4B是示出图4A的区段B的放大图；
图5A至图5K是示出根据本公开的实施方式的制造半导体封装件的方法的截面图。
具体实施方式
在本说明书中，相似的标号可指示相似的组件。以下现在将描述根据本公开的实施方式的半导体封装件及其制造方法。
图1A是示出根据本公开的实施方式的半导体封装件的平面图。图1B是沿着图1A的线I-I’截取的截面图。图1C是示出图1B的区段A的放大图。
参照图1A至图1C，半导体封装件可包括第一封装件1。第一封装件1可包括耦接焊料500、基板100、芯片堆叠件200、第二半导体芯片220和模制层300。第一封装件1还可包括第一凸块510、第二凸块520、底填充层400、第一钝化图案180和第二钝化图案182。
基板100可以是插入基板100。如图1B所示，插入基板100可包括半导体晶片110、通孔170、介电层120、布线结构130和插入焊盘150。插入基板100可以不包括诸如晶体管的集成电路。半导体晶片110可具有相对低的热膨胀系数(CTE)。例如，半导体晶片110的热膨胀系数(CTE)可为约3.2ppm/℃至约4.2ppm/℃。半导体晶片110可包括硅晶片、锗晶片或硅锗晶片。半导体晶片110可具有彼此相对的顶表面和底表面110b。通孔170可设置在半导体晶片110中。通孔170可包括诸如金属的导电材料。通孔170可彼此电分离。通孔170可穿透半导体晶片110的顶表面和底表面110b。插入基板100的底表面可以是半导体晶片110的底表面110b。
布线层可设置在半导体晶片110的顶表面上。布线层可包括介电层120和布线结构130。介电层120可包括多个层。介电层120可包括硅基介电材料，例如氧化硅、氮化硅、氮氧化硅和原硅酸四乙酯(TEOS)中的一种或多种。布线结构130可设置在介电层120中。布线结构130可包括导线和导电通孔。导线的主轴可基本上平行于半导体晶片110的底表面110b。导电通孔的主轴可基本上平行于半导体晶片110的底表面110b。导电通孔可连接到导线。布线结构130可包括诸如铜、钨、钛或其任何合金的金属。
插入焊盘150可设置在插入基板100的顶表面上。例如，插入焊盘150可设置在布线结构130上并耦接到布线结构130。布线结构130可包括第一布线结构和第二布线结构。两个插入焊盘150可通过第一布线结构彼此电连接。插入焊盘150之一可通过第二布线结构电连接到通孔170之一。第二布线结构可与第一布线结构电分离。短语“电连接到插入基板100”可意指“电连接到至少一个布线结构130”。表述“两个组件彼此电连接/耦接”可包括“两个组件彼此直接连接或通过其它导电组件彼此间接连接”的含义。
耦接焊料500可设置在插入基板100的底表面上并且可耦接到通孔170。耦接焊料500可包括焊球或一些其它形状的电连接触点。焊球可包括诸如锡(Sn)、银(Ag)、锌(Zn)或其任何合金的焊料材料。焊料焊盘105还可插设在耦接焊料500和通孔170之间。焊料焊盘105可包括与焊球的材料不同的材料。焊料焊盘105可包括诸如铜、金或镍的金属。
芯片堆叠件200可设置在插入基板100的边缘区域处的顶表面上。芯片堆叠件200可设置为多个。多个芯片堆叠件200中的每一个可包括第一下半导体芯片210A和第一上半导体芯片210B。在平面图中，第一下半导体芯片210A可具有安装区域R1和外伸区域R2。第一下半导体芯片210A的安装区域R1可设置在插入基板100的顶表面上。在平面图中，第一下半导体芯片210A的安装区域R1可与插入基板100重叠。第一下半导体芯片210A的安装区域R1可包括第一下半导体芯片210A的中心区域，但本发明构思未必限于此。在平面图中，第一下半导体芯片210A的外伸区域R2可与插入基板100间隔开。第一下半导体芯片210A的外伸区域R2可包括第一下半导体芯片210A的边缘区域。在平面图中，第一下半导体芯片210A的边缘区域可设置在第一下半导体芯片210A的中心区域和第一下半导体芯片210A的侧表面之间。
第一下半导体芯片210A可以是逻辑芯片或控制器芯片。第一下半导体芯片210A可控制多个第一上半导体芯片210B。第一下半导体芯片210A可包括第一集成电路。如图1C所示，第一下半导体芯片210A可包括第一下焊盘215A、第一贯通电极217A和第一上焊盘216A。第一集成电路可设置在第一下半导体芯片210A中。第一下焊盘215A可设置在第一下半导体芯片210A的安装区域R1处的底表面上。在平面图中，第一下焊盘215A可位于第一下半导体芯片210A的中心区域上。第一下焊盘215A可以不设置在第一下半导体芯片210A的外伸区域R2处的底表面上。第一下焊盘215A可电连接到第一集成电路。第一下焊盘215A的间距可小于耦接焊料500的间距P。
第一贯通电极217A可设置在第一下半导体芯片210A中。每个第一贯通电极217A可耦接到从第一下焊盘215A和第一集成电路中选择的至少一个。在平面图中，第一贯通电极217A可位于第一下半导体芯片210A的中心区域上。第一上焊盘216A可设置在第一下半导体芯片210A的顶表面上并且可耦接到第一贯通电极217A。在平面图中，第一上焊盘216A可位于第一下半导体芯片210A的中心区域上，但本发明构思未必限于此。第一下焊盘215A、第一贯通电极217A和第一上焊盘216A可各自包括金属。
第一上半导体芯片210B可设置在第一下半导体芯片210A上。每个芯片堆叠件200可包括多个第一上半导体芯片210B。在这种情况下，第一上半导体芯片210B可垂直地堆叠。在本说明书中，术语“垂直/垂直地”可意指“垂直/垂直于半导体晶片110的底表面110b”。第一上半导体芯片210B的类型可与第一下半导体芯片210A的类型不同。例如，第一上半导体芯片210B可以是存储器芯片。存储器芯片可包括高带宽存储器(HBM)芯片。
每个第一上半导体芯片210B可包括第二集成电路、第二下焊盘215B、第二贯通电极217B和第二上焊盘216B。第二集成电路可设置在每个第一上半导体芯片210B中。第二下焊盘215B和第二上焊盘216B可分别设置在与之对应的第一上半导体芯片210B的底表面和顶表面上。第二下焊盘215B和第二上焊盘216B可电连接到与之对应的第一上半导体芯片210B的第二集成电路。第二贯通电极217B可位于与之对应的第一上半导体芯片210B中，并且可耦接到第二下焊盘215B和第二上焊盘216B。第二贯通电极217B还可耦接到第二集成电路。最上面的一个第一上半导体芯片210B可包括第二集成电路和第二下焊盘215B，但可以不包括第二贯通电极217B或第二上焊盘216B。最上面的第一上半导体芯片210B的厚度可大于其它第一上半导体芯片210B的厚度。
在平面图中，第二下焊盘215B、第二贯通电极217B和第二上焊盘216B可设置在与之对应的第一上半导体芯片210B的中心区域上。第一上半导体芯片210B可在其边缘区域上设置有第二下焊盘215B、第二贯通电极217B或第二上焊盘216B。在这种情况下，第一上焊盘216A可设置在第一下半导体芯片210A的边缘区域处的顶表面上，并且可以不与第一贯通电极217A垂直地对准。每个第一下半导体芯片210A还可包括设置在第一上焊盘216A和第一贯通电极217A之间的再分布线。第一上焊盘216A可通过再分布线耦接到第一贯通电极217A。
第一凸块510可插设在插入基板100和第一下半导体芯片210A之间并电连接到插入基板100和第一下半导体芯片210A。在本说明书中，短语“电连接到半导体芯片”可意指“电连接到半导体芯片中的集成电路”。第一凸块510可相应地插设在第一下焊盘215A和插入焊盘150之间。在平面图中，第一凸块510可与第一下半导体芯片210A的中心区域重叠。第一凸块510可包括焊球。第一凸块510还可包括柱图案。第一凸块510的间距可小于耦接焊料500的间距P。
每个芯片堆叠件200还可包括上凸块530。上凸块530可插设在第一上半导体芯片210B之间并且可相应地耦接到第二下焊盘215B和第二上焊盘216B。上凸块530还可插设在第一下半导体芯片210A和最下面一个第一上半导体芯片210B之间，并且因此可耦接到第一上焊盘216A和最下面的第一上半导体芯片210B的第二下焊盘215B。第一上半导体芯片210B可通过上凸块530电连接到第一下半导体芯片210A和插入基板100。在平面图中，上凸块530可与第一上半导体芯片210B的中心区域垂直地重叠，但本发明构思未必限于此。
上凸块530的间距可小于耦接焊料500的间距P。每个上凸块530可包括焊料、柱或其组合。上凸块530可包括焊料材料或铜。另选地，上凸块530可被省略。在这种情况下，一个第一上半导体芯片210B的第二下焊盘215B可直接接合到与这一个第一上半导体芯片210B相邻的另一第一上半导体芯片210B的第二上焊盘216B。第一下半导体芯片210A可直接接合到最下面的第一上半导体芯片210B。
每个芯片堆叠件200还可包括底填充图案420。底填充图案420可设置在第一下半导体芯片210A和最下面的第一上半导体芯片210B之间的第一上间隙中以及第一上半导体芯片210B之间的第二上间隙中。每个底填充图案420可包封对应的上凸块530。底填充图案420可包括诸如环氧类聚合物的介电聚合物。
第二半导体芯片220可设置在插入基板100的中心区域处的顶表面上。在平面图中，第二半导体芯片220可与插入基板100完全重叠。在平面图中，第二半导体芯片220可位于芯片堆叠件200之间。例如，第二半导体芯片220可与第一下半导体芯片210A和第一上半导体芯片210B横向间隔开。短语“两个组件彼此横向地间隔开”可意指“两个组件彼此水平地间隔开”。术语“水平/水平地”可指示“平行于半导体晶片110的底表面110b”。第二半导体芯片220的类型可不同于第一下半导体芯片210A和第一上半导体芯片210B的类型。例如，第二半导体芯片220可包括逻辑芯片、缓冲芯片或片上系统(SOC)。第二半导体芯片220可以是例如功能不同于第一下半导体芯片210A的功能的逻辑芯片。第二半导体芯片220可以是例如专用集成电路(ASIC)芯片或应用处理器(AP)芯片。ASIC芯片可包括专用集成电路(ASIC)。第二半导体芯片220可包括中央处理单元(CPU)或图形处理单元(GPU)。
第二半导体芯片220可包括集成电路和芯片焊盘225。集成电路可设置在第二半导体芯片220中。芯片焊盘225可设置在第二半导体芯片220的底表面上并且可电连接到第二半导体芯片220的集成电路。第二半导体芯片220中的芯片焊盘225的数量可大于第一下半导体芯片210A中的第一下焊盘215A的数量。例如，第二半导体芯片220中的芯片焊盘225的数量可等于或大于单个第一下半导体芯片210A中的第一下焊盘215A的数量的两倍。
第二凸块520可插设在插入基板100和第二半导体芯片220之间。例如，第二凸块520可相应地耦接到插入焊盘150和第二半导体芯片220的芯片焊盘225。第二半导体芯片220可通过插入基板100电连接到芯片堆叠件200或耦接焊料500。第二凸块520可包括焊球。第二凸块520还可包括柱图案。第二凸块520的间距可小于耦接焊料500的间距P。
底填充层400可设置在芯片堆叠件200的底表面和第二半导体芯片220的底表面上。底填充层400可设置在插入基板100和芯片堆叠件200之间的第一间隙中，从而覆盖第一凸块510的侧壁。底填充层400可设置在插入基板100和第二半导体芯片220之间的第二间隙中，从而覆盖第二凸块520的侧壁。底填充层400可设置在第一下半导体芯片210A的外伸区域R2处的底表面上。底填充层400可具有与插入基板100间隔开的远端400Z。底填充层400的宽度可大于插入基板100的宽度W。除非另外指明，否则特定组件的宽度可在平行于半导体晶片110的底表面110b的方向上测量。底填充层400可包括诸如环氧类聚合物的介电聚合物。
模制层300可设置在插入基板100上。模制层300可包括第一模制图案310和第二模制图案320。第一模制图案310可设置在第一下半导体芯片210A的外伸区域R2处的底表面上。第一模制图案310可覆盖插入基板100的侧壁。第一模制图案310可与插入基板100的侧壁直接接触。在平面图中，第一模制图案310可至少部分地围绕插入基板100。第一模制图案310可保护插入基板100。模制层300可具有约6ppm/℃至20ppm/℃的热膨胀系数(CTE)。模制层300的热膨胀系数(CTE)可为CTEα1。CTEα1可以是温度低于玻璃化转变温度(Tg)时的热膨胀系数。
第一模制图案310可具有彼此相对的顶表面和底表面310b。第一模制图案310的底表面310b可以是模制层300的底表面。例如，第一模制图案310的顶表面可位于与介电层120的顶表面的水平基本上相同的水平处，但本发明构思未必限于此。短语“某些组件在水平上相同”可包括在制造工艺期间可能出现的可允许的公差。在本说明书中，术语“水平”可意指垂直水平(vertical level)。模制层300的底表面可与插入基板100的底表面共面。例如，第一模制图案310的底表面310b可与半导体晶片110的底表面110b共面。底填充层400可设置在第一模制图案310的顶表面上。例如，底填充层400的远端400Z可插设在第一模制图案310和第一下半导体芯片210A之间。
第一模制图案310可具有大于插入基板100的热膨胀系数(CTE)的热膨胀系数(CTE)。例如，第一模制图案310的热膨胀系数(CTE)可大于半导体晶片110的热膨胀系数(CTE)。例如，第一模制图案310的热膨胀系数(CTE)可在约6ppm/℃至约20ppm/℃的范围内。在这种情况下，第一模制图案310的热膨胀系数(CTE)可为CTEα1。第一模制图案310可包括第一介电聚合物。第一介电聚合物可包括例如环氧类模制化合物。第一介电聚合物可具有与底填充层400和底填充图案420的材料不同的材料。第一模制图案310还可包括第一填充物。第一填充物可设置在第一介电聚合物中。第一填充物可包括诸如二氧化硅的无机材料。
第二模制图案320可设置在第一模制图案310和插入基板100上。第二模制图案320可覆盖芯片堆叠件200的侧壁和第二半导体芯片220的侧壁。例如，第二模制图案320可覆盖第一下半导体芯片210A的侧壁和第一上半导体芯片210B的侧壁。第二模制图案320还可覆盖底填充层400。第二模制图案320可直接位于第一模制图案310的顶表面上。第二模制图案320的顶表面可与最上面的第一上半导体芯片210B的顶表面和第二半导体芯片220的顶表面共面。第二模制图案320还可覆盖芯片堆叠件200的顶表面和第二半导体芯片220的顶表面。芯片堆叠件200的顶表面中的每一个可以是最上面的第一上半导体芯片210B的顶表面。
第二模制图案320可包括第二介电聚合物。第二介电聚合物可包括例如环氧类模制化合物。第二介电聚合物可具有与底填充层400的材料和底填充图案420的材料不同的材料。第二模制图案320还可包括第二填充物。在本公开的一些实施方式中，第二模制图案320可包括与第一模制图案310的材料相同的材料。在本公开的一些实施方式中，第二模制图案320可包括与第一模制图案310的材料不同的材料。在这种情况下，第二介电聚合物可不同于第一介电聚合物，并且第二填充物可不同于第一填充物。例如，第二模制图案320可具有约6ppm/℃至约20ppm/℃的热膨胀系数(CTE)，但本发明构思未必限于此。在这种情况下，第二模制图案320的热膨胀系数(CTE)可为CTEα1。
第二模制图案320可与第一模制图案310具有基本上相同的宽度和长度。特定组件的长度可在平行于半导体晶片110的方向上测量。特定组件的长度方向可基本上垂直于特定组件的宽度方向。第二模制图案320可具有与第一模制图案310的外壁对齐的外壁。
根据本公开的一些实施方式，插入基板100可具有相对小的宽度W和相对小的长度L。例如，插入基板100的宽度W和长度L可小于模制层300的宽度和长度。插入基板100可具有相对小的平面面积。因此，插入基板100可具有增大的有效面积分数。插入基板100的有效面积分数可以是插入焊盘150的平面面积与插入基板100的平面面积之比。由于插入基板100具有小的平面面积，所以可能能够简化插入基板100的形成、布线结构130的形成和插入焊盘150的形成。
第一钝化图案180可设置在插入基板100的底表面和第一模制图案310的底表面310b上。第一钝化图案180可覆盖半导体晶片110的底表面110b和第一模制图案310的底表面310b。第一钝化图案180还可覆盖通孔170的下侧壁。第一钝化图案180的底表面可在与通孔170的底表面的水平基本上相同的水平处。第一钝化图案180的外壁可与模制层300的外壁对齐。第一钝化图案180可包括诸如氮化硅的介电材料。
第二钝化图案182可位于第一钝化图案180的底表面上并覆盖第一钝化图案180的底表面。第二钝化图案182的外壁可与第一钝化图案180的外壁和模制层300的外壁对齐。第二钝化图案182可包括与第一钝化图案180的材料不同的材料。第二钝化图案182可包括诸如光敏聚酰亚胺(PSPI)的有机介电材料。第一钝化图案180和第二钝化图案182可保护插入基板100。
图2A是示出根据本公开的一些实施方式的半导体封装件的平面图。图2B是沿着图2A的线II-II’截取的截面图。
参照图2A和图2B，半导体封装件可包括第一封装件1、焊料端子650、封装基板600、下底填充层410、加强件700和粘合层710。第一封装件1可与上面在图1A和图1B中讨论的那些基本上相同。例如，第一封装件1可包括耦接焊料500、插入基板100、芯片堆叠件200、第二半导体芯片220和模制层300。第一封装件1还可包括第一凸块510、第二凸块520、底填充层400、第一钝化图案180和第二钝化图案182。
封装基板600可包括例如印刷电路板(PCB)。在平面图中，封装基板600可具有中心区域和边缘区域。在平面图中，封装基板600的边缘区域可设置在封装基板600的侧表面和封装基板600的中心区域之间。
封装基板600可包括介电基层610、导电图案620和基板焊盘630。介电基层610可包括多层。另选地，介电基层610可以是单层。基板焊盘630可设置在封装基板600的顶表面上。导电图案620可位于介电基层610中并且可耦接到基板焊盘630。短语“电连接到封装基板600”可意指“电连接到至少一个导电图案620”。基板焊盘630和导电图案620可包括诸如铜、铝、钨和钛中的一种或多种的金属。
焊料端子650可设置在封装基板600的底表面上并且可电连接到导电图案620。外部电信号可被传送至焊料端子650。焊料端子650可包括焊球。
第一封装件1可位于封装基板600上。例如，插入基板100可设置在封装基板600的中心区域处的顶表面上。耦接焊料500可耦接到对应的基板焊盘630。因此，芯片堆叠件200和第二半导体芯片220可通过插入基板100电连接到封装基板600。
封装基板600可具有大于插入基板100的热膨胀系数(CTE)的热膨胀系数(CTE)。例如，封装基板600的热膨胀系数(CTE)可大于半导体晶片110的热膨胀系数(CTE)。封装基板600和半导体晶片110之间的热膨胀系数(CTE)差异可能引起施加到插入基板100的应力。应力可能集中在插入基板100的边缘区域上。应力可能导致模制层300或下底填充层410从插入基板100脱层。特定组件的宽度和长度越小，由热膨胀系数导致的应力越小。根据本公开的一些实施方式，插入基板100的宽度W和长度L可小于第一模制图案310的宽度和长度。因此，可能能够减小施加到插入基板100的边缘区域的应力。即使当半导体封装件重复地操作时，也可防止第一模制图案310从插入基板100脱层。
封装基板600和半导体晶片110之间的热膨胀系数(CTE)差异可能产生半导体封装件的翘曲。模制层300可具有大于插入基板100的热膨胀系数(CTE)的热膨胀系数(CTE)。例如，第一模制图案310的热膨胀系数(CTE)可大于半导体晶片110的热膨胀系数(CTE)。因此，封装基板600和半导体晶片110之间的热膨胀系数(CTE)差异可被第一模制图案310和半导体晶片110之间的热膨胀系数(CTE)差异抵消。由于插入基板100的宽度W和长度L相对小，并且由于第一模制图案310设置在插入基板100的侧壁上，所以模制层300可具有增大的体积，并且半导体晶片110可具有减小的体积。因此，模制层300和半导体晶片110之间的热膨胀系数(CTE)差异可有效地抵消封装基板600和半导体晶片110之间的热膨胀系数(CTE)差异。因此，可防止半导体封装件翘曲。可提高半导体封装件的操作可靠性。
下底填充层410可设置在封装基板600和插入基板100之间的间隙中，从而覆盖耦接焊料500的侧壁。下底填充层410可保护耦接焊料500。下底填充层410还可覆盖第一钝化图案180和第二钝化图案182的外壁以及第一模制图案310的外壁。下底填充层410还可延伸到第二模制图案320的外壁的下部。下底填充层410可与插入基板100间隔开。下底填充层410可包括诸如环氧类聚合物的介电聚合物。然而，下底填充层410可包括与模制层300的材料不同的材料。下底填充层410可具有与模制层300的热膨胀系数(CTE)不同的热膨胀系数(CTE)。下底填充层410的热膨胀系数(CTE)可大于半导体晶片110的热膨胀系数(CTE)。因此，半导体晶片110和封装基板600之间的热膨胀系数(CTE)差异还可被下底填充层410和半导体晶片110之间的热膨胀系数(CTE)差异抵消。
加强件700可位于封装基板600的边缘区域处的顶表面上。加强件700可与模制层300横向地间隔开。例如，加强件700可包括铜、不锈钢(SUS)、碳化硅铝(AlSiC)和钛中的一种或多种。半导体封装件可能在封装基板600的边缘区域处遭受翘曲。加强件700可相对硬以固定封装基板600的边缘区域。因此，可防止封装基板600翘曲。
粘合层710可插设在封装基板600和加强件700之间。粘合层710可将加强件700固定到封装基板600。粘合层710可具有介电性质或导电性质。粘合层710可包括有机材料或金属。
图2C是沿着图2A的线II-II’截取的截面图，其示出根据本公开的一些实施方式的半导体封装件。
参照图2C，半导体封装件可包括第一封装件1A、焊料端子650、封装基板600、下底填充层410、加强件700和粘合层710。第一封装件1A可包括从耦接焊料500、插入基板100、芯片堆叠件200、第二半导体芯片220、模制层300、第一凸块510、第二凸块520、底填充层400、第一钝化图案180和第二钝化图案182中选择的至少一个。第一封装件1A可与图1A和图1B的第一封装件1基本上相同。例如，底填充层400可设置在第二半导体芯片220和插入基板100之间的第二间隙中，从而覆盖第二凸块520的侧壁。然而，底填充层400可以不延伸到第一下半导体芯片210A的外伸区域R2处的底表面上。底填充层400的远端400Z可与第一模制图案310间隔开。底填充层400的远端400Z可与插入基板100垂直地重叠。底填充层400的远端400Z还可延伸到第一下半导体芯片210A的安装区域R1处的底表面上。在本公开的一些实施方式中，底填充层400的远端400Z可以不延伸到第一下半导体芯片210A的底表面上。
图2D是沿着图2A的线II-II’截取的截面图，其示出根据本公开的一些实施方式的半导体封装件。
参照图2D，半导体封装件可包括第一封装件1B、焊料端子650、封装基板600、下底填充层410、加强件700和粘合层710。第一封装件1B可与图1A和图1B的第一封装件1基本上相同。相比之下，第一封装件1B还可包括热辐射器790。
热辐射器790可设置在从第二半导体芯片220的顶表面和芯片堆叠件200的顶表面中选择的至少一个上。在这种情况下，模制层300可暴露出芯片堆叠件200的顶表面和第二半导体芯片220的顶表面。热辐射器790还可覆盖模制层300的顶表面。热辐射器790还可延伸到模制层300的外壁上。热辐射器790可包括散热器、散热块或热界面材料(TIM)层。热辐射器790可具有大于模制层300的热膨胀系数(CTE)的热膨胀系数(CTE)。当半导体封装件操作时，热辐射器790可迅速将从芯片堆叠件200和/或第二半导体芯片220生成的热向外排放。热辐射器790可包括例如铜。热辐射器790可吸收外部物理冲击，从而保护第二半导体芯片220和芯片堆叠件200。
热辐射器790可以是导电的并且可用作电磁场屏蔽层。在这种情况下，热辐射器790可屏蔽芯片堆叠件200和第二半导体芯片220的电磁干扰(EMI)。
图3是沿着图2A的线II-II’截取的截面图，其示出根据本公开的一些实施方式的半导体封装件。
参照图3，半导体封装件可包括第一封装件1C、焊料端子650、封装基板600、下底填充层410、加强件700和粘合层710。第一封装件1C可与图1A和图1B中讨论的第一封装件1基本上相同。
模制层300可包括第一模制图案311和第二模制图案321。第一模制图案311和第二模制图案321的位移可与图1A和图1B的第一模制图案310和第二模制图案320的位移基本上相同。相比之下，第二模制图案321可包括与第一模制图案311的材料相同的材料。例如，第二模制图案321的第二介电聚合物可与第一模制图案311的第一介电聚合物相同。可在第一模制图案311和第二模制图案321之间限定不明晰边界。
例如，第一封装件1C可以不包括底填充层(参见图1A和图1B的400)。模制层300还可设置在插入基板100和第一下半导体芯片210A之间以及插入基板100和第二半导体芯片220之间，从而包封第一凸块510和第二凸块520。模制层300可与介电层120的顶表面直接接触。
图4A是沿着图2A的线II-II’截取的截面图，其示出根据本公开的一些实施方式的半导体封装件。图4B是示出图4A的区段B的放大图。
参照图4A和图4B，半导体封装件可包括第一封装件1D、焊料端子650、封装基板600、下底填充层410、加强件700和粘合层710。第一封装件1D可与图1A和图1B中讨论的第一封装件1基本上相同。例如，模制层300可包括第一模制图案310和第二模制图案320。第二模制图案320可包括与第一模制图案310的材料不同的材料。如图4B所示，第一模制图案310可包括例如第一介电聚合物3101和第一填充物3109。第一填充物3109可分散在第一介电聚合物3101中。第一填充物3109可包括诸如二氧化硅的无机材料。第二模制图案320可包括第二介电聚合物3201和第二填充物3209。第二填充物3209可设置在第二介电聚合物3201中。第二填充物3209可包括诸如二氧化硅的无机材料。第二填充物3209的直径可小于第一填充物3109的直径。
第一封装件1D可以不包括底填充层(参见图1A和图1B的400)。在这种情况下，第二模制图案320还可在插入基板100和第一下半导体芯片210A之间以及插入基板100和第二半导体芯片220之间延伸，从而包封第一凸块510和第二凸块520。
图5A至图5K是示出根据本公开的一些实施方式的制造半导体封装件的方法的截面图。就各种元件的描述已被省略而言，可假设这些元件至少与在本说明书中的别处已经描述的对应的元件相似。为了描述方便，在说明图5F至图5K时，将基于示出特定组件的附图来讨论该特定组件的顶表面和底表面。
参照图5A，可制造初步插入基板100Z。根据本公开的一些实施方式，可制备半导体晶圆110W。半导体晶圆110W可包括多个半导体晶片110。半导体晶片110可彼此连接。半导体晶片110可由限定在半导体晶圆110W的一个表面上的划道限定，但本发明构思未必限于此。
可在半导体晶圆110W中形成通孔170。通孔170可穿透半导体晶片110的顶表面，但可以不穿透半导体晶片110的底表面。通孔170的底表面可设置在半导体晶片110中。
可在半导体晶圆110W的顶表面上形成布线层。布线层的形成可包括形成介电层120和形成布线结构130。布线结构130可耦接到通孔170。因此可制造初步插入基板100Z。每个初步插入基板100Z可包括半导体晶片110、通孔170、介电层120和布线结构130。半导体晶圆110W和介电层120可沿着虚线经历第一锯切工艺以将初步插入基板100Z彼此分离。
参照图5B，分离的初步插入基板100Z可位于载体基板990上。在这种情况下，初步插入基板100Z可彼此横地间隔开。还可在载体基板990和初步插入基板100Z之间设置剥离层980。剥离层980可将初步插入基板100Z附接到载体基板990。
参照图5C，可在载体基板990上形成第一模制层310P，并且第一模制层310P可覆盖初步插入基板100Z的侧壁。可执行晶圆级工艺以形成第一模制层310P。根据本公开的一些实施方式，可在半导体晶片110的侧壁和介电层120的顶表面上形成第一模制层310P。此后，可从介电层120的顶表面去除第一模制层310P，从而暴露出布线结构130的顶表面。例如，第一模制层310P可不保留在介电层120的顶表面上。第一模制层310P的顶表面可在与介电层120的顶表面的水平基本上相同的高度处，但本发明构思未必限于此。另选地，第一模制层310P可部分地保留在介电层120的顶表面上。
可在布线结构130的暴露的顶表面上相应地形成插入焊盘150，并且插入焊盘150可耦接到布线结构130。因此，可制造插入基板100。每个插入基板100可包括半导体晶片110、通孔170、介电层120、布线结构130和插入焊盘150。以下将描述单个插入基板100，但根据本发明构思的半导体封装件的制造未必限于芯片级制造工艺。
参照图5D，可在插入基板100上安装芯片堆叠件200和第二半导体芯片220。如上所讨论的，每个芯片堆叠件200可包括第一下半导体芯片210A、第一上半导体芯片210B、上凸块530和底填充图案420。每个芯片堆叠件200的安装可包括将芯片堆叠件200定位在插入基板100和第一模制层310P上以及形成第一凸块510。在这种情况下，第一下半导体芯片210A可具有与插入基板100垂直地重叠的安装区域R1，并且还可具有与第一模制层310P垂直地重叠的外伸区域R2。可在插入基板100和第一下半导体芯片210A的安装区域R1之间形成第一凸块510。第二半导体芯片220的安装可包括在第二半导体芯片220和插入基板100之间形成第二凸块520。
可在插入基板100和第一下半导体芯片210A之间以及插入基板100和芯片堆叠件200之间的第一间隙中形成底填充层400。底填充层400可包封第一凸块510和第二凸块520。底填充层400可在第一模制层310P的顶表面和第一下半导体芯片210A的外伸区域R2处的底表面之间延伸。底填充层400可具有设置在第一模制层310P上并与第一模制层310P垂直地重叠的远端400Z。
参照图5E，可在第一模制层310P和插入基板100上形成第二模制层320P，并且因此可形成初步模制层300P。可使用与第一模制层310P的材料相同或相似的材料来形成第二模制层320P。可执行晶圆级工艺以形成第二模制层320P。例如，第二模制层320P可覆盖多个第二半导体芯片220的侧壁、多个芯片堆叠件200的侧壁以及多个底填充层400。第二模制层320P还可覆盖第二半导体芯片220的顶表面和芯片堆叠件200的顶表面。在这种情况下，第二模制层320P可经历磨削工艺以去除第二模制层320P的一部分。磨削工艺可继续，直至暴露出第二半导体芯片220的顶表面并且暴露出芯片堆叠件200的顶表面。为了方便，以下将描述单个第二半导体芯片220。
可如虚线所示去除载体基板990和剥离层980，并且相应地可能能够暴露出插入基板100的底表面和第一模制层310P的底表面。可在形成第二模制层320P之前去除载体基板990和剥离层980。
参照图5F，插入基板100、初步模制层300P、底填充层400、第二半导体芯片220和芯片堆叠件200可各自上下颠倒以允许插入基板100面向上。
参照图5G，可对半导体晶片110和第一模制层310P执行减薄工艺。减薄工艺可包括磨削工艺或回蚀工艺。在减薄工艺终止之后，半导体晶片110的顶表面可位于与第一模制层310P的顶表面的水平基本上相同的水平处。减薄工艺可允许通孔170具有突起170Z。通孔170的突起170Z可位于比减薄后的半导体晶片110的顶表面的水平更高的水平处。
参照图5H，可在第一模制层310P和半导体晶片110上形成第一钝化层180P。第一钝化层180P可覆盖第一模制层310P的顶表面、半导体晶片110的顶表面和通孔170的突起170Z。可执行沉积工艺以形成第一钝化层180P。沉积工艺可以是晶圆级沉积工艺。
参照图5I，可对第一钝化层180P执行抛光工艺。如由虚线所示，抛光工艺可去除第一钝化层180P的一部分和通孔170的突起170Z。第一钝化层180P的那部分可以是覆盖通孔170的突起170Z的段。作为抛光工艺的结果，可暴露出通孔170的表面170b。通孔170的表面170b可位于与第一钝化层180P的顶表面的水平基本上相同的水平处。抛光工艺可包括化学机械抛光工艺。
参照图5J，可在第一钝化层180P上形成第二钝化层182P并且第二钝化层182P可覆盖第一钝化层180P。可执行涂覆工艺以形成第二钝化层182P，但本发明构思未必限于此。可在第二钝化层182P中形成开口以暴露出通孔170的表面170b。可在通孔170的对应的表面170b上形成焊料焊盘105以耦接到对应的通孔170。可在对应的焊料焊盘105上形成耦接焊料500。
顺序地参照图5J和图5K，可将划片胶带970附接到芯片堆叠件200的底表面、第二半导体芯片220的底表面和初步模制层300P的底表面。
此后，第二钝化层182P、第一钝化层180P和初步模制层300P可经历第二锯切工艺以形成凹槽390。可使用刀片执行第二锯切工艺。凹槽390可穿透第二钝化层182P、第一钝化层180P和初步模制层300P，并且因此可暴露出划片胶带970。第二钝化层182P、第一钝化层180P和初步模制层300P可被切割以分别形成第二钝化图案182、第一钝化图案180和模制层300。凹槽390可将模制层300彼此分离。每个模制层300可至少部分地被凹槽390围绕。凹槽390可将第一钝化图案180彼此分离。凹槽390可将第二钝化图案182彼此分离。因此，可制造第一封装件1。每个第一封装件1可与在图1A和图1B的示例中讨论的第一封装件1基本上相同。为了简明，下面将讨论单个第一封装件1。
底填充层400可不延伸到第一下半导体芯片210A的外伸区域R2处的底表面上。此方法可用于制造图2C中讨论的第一封装件1A。例如，当第二模制图案320由与第一模制图案310的材料相同的材料形成时，可如图3中讨论制造第一封装件1C。
返回参照图1A和图1B，第一封装件1可与划片胶带970分离。之后，第一封装件1可上下颠倒以允许耦接焊料500面向下。
再参照图2A和图2B，可在封装基板600的中心区域上安装第一封装件1。第一封装件1的安装可包括将耦接焊料500耦接到对应的基板焊盘630。
此后，可在封装基板600和第二钝化图案182之间形成下底填充层410。下底填充层410还可覆盖第一钝化图案180的外壁和第二钝化图案182的外壁以及第一模制图案310的外壁。
可将加强件700定位在封装基板600的边缘区域处的顶表面上。可在封装基板600和加强件700之间形成粘合层710。糊剂可用于形成粘合层710。上面提及的工艺可用于制造半导体封装件。
图2A和图2B、图2C、图2D、图3以及图4A和图4B的示例可彼此组合。例如，结合图2D在示例中讨论的热辐射器790可包括在图2C的第一封装件1A、图3的第一封装件1C和/或图4A和图4B的第一封装件1D中。
根据本公开的实施方式，可减小插入基板的宽度或长度以减小施加到插入基板的应力。可防止模制层从插入基板脱层。另外，插入基板可具有增大的有效面积分数。可容易地制造插入基板。
模制层可设置在第一下半导体芯片的外伸区域处的底表面上，从而覆盖插入基板的侧壁。由于模制层具有增大的体积，所以插入基板和封装基板之间的热膨胀系数差异可被模制层和插入基板之间的热膨胀系数差异抵消。因此，可减少半导体封装件的翘曲。可提高半导体封装件的操作可靠性。
本发明构思的此详细描述不应被解释为限于本文所阐述的实施方式，并且在不脱离本公开的精神和范围的情况下，本发明构思旨在涵盖本发明的各种组合、修改和变化。

Claims (20)

1.一种半导体封装件，包括：
第一半导体芯片，其包括安装区域和外伸区域；
基板，其设置在所述第一半导体芯片的安装区域处的底表面上；以及
模制层，其设置在所述基板上，
其中，所述模制层包括：
第一模制图案，其设置在所述第一半导体芯片的外伸区域处的底表面上并且至少部分地覆盖所述基板的侧壁；以及
第二模制图案，其设置在所述第一模制图案上并且至少部分地覆盖所述第一半导体芯片的侧壁。
2.根据权利要求1所述的半导体封装件，其中，所述第一模制图案的底表面与所述基板的底表面共面。
3.根据权利要求1所述的半导体封装件，还包括设置在所述基板和所述第一半导体芯片之间的底填充层，
其中，所述底填充层还设置在所述第一模制图案和所述第一半导体芯片之间。
4.根据权利要求1所述的半导体封装件，还包括设置在所述基板的底表面上的钝化图案，
其中，所述钝化图案延伸到所述第一模制图案的底表面上。
5.根据权利要求4所述的半导体封装件，还包括堆叠在所述第一半导体芯片上的多个上半导体芯片，
其中，所述第一半导体芯片包括限定在其中的多个通孔，并且
其中，所述多个通孔的底表面位于与所述钝化图案的底表面的水平实质上相同的水平处。
6.根据权利要求1所述的半导体封装件，其中，
所述第一模制图案包括第一介电聚合物和多个第一填充物，
所述第二模制图案包括第二介电聚合物和多个第二填充物，并且
所述多个第二填充物中的每一个的直径小于所述多个第一填充物中的每一个的直径。
7.根据权利要求1所述的半导体封装件，还包括设置在所述基板的顶表面上并与所述第一半导体芯片并排设置的第二半导体芯片，
其中，所述第二半导体芯片与所述基板至少部分地重叠。
8.根据权利要求7所述的半导体封装件，其中，
所述第一半导体芯片包括设置在所述第一半导体芯片的底表面上的多个焊盘，并且
所述第二半导体芯片的多个芯片焊盘的数量等于或大于所述第一半导体芯片的焊盘的数量的两倍。
9.根据权利要求7所述的半导体封装件，还包括：
多个第一凸块，其设置在所述基板和所述第一半导体芯片之间；
多个第二凸块，其设置在所述基板和所述第二半导体芯片之间；以及
底填充层，其设置在所述基板和所述第二半导体芯片之间，
其中，所述底填充层延伸到所述基板和所述第一半导体芯片的安装区域处的底表面上，并且至少部分地覆盖所述多个第一凸块和所述多个第二凸块。
10.根据权利要求1所述的半导体封装件，其中，所述基板包括半导体晶片，
其中，所述第一模制图案的热膨胀系数大于所述半导体晶片的热膨胀系数。
11.一种半导体封装件，包括：
插入基板；
第一半导体芯片，其在所述插入基板上；以及
模制层，其覆盖所述插入基板的侧壁，
其中，所述第一半导体芯片包括外伸区域和安装区域，
其中，所述模制层设置在所述第一半导体芯片的外伸区域处的底表面上，并且
其中，所述模制层的底表面与所述插入基板的底表面共面。
12.根据权利要求11所述的半导体封装件，还包括设置在所述插入基板和所述第一半导体芯片之间的底填充层，
其中，所述底填充层的端部与所述插入基板间隔开。
13.根据权利要求12所述的半导体封装件，还包括：
上半导体芯片，其设置在所述第一半导体芯片上；以及
第二半导体芯片，其设置在所述插入基板上并位于所述第一半导体芯片的一侧，
其中，所述底填充层在所述插入基板和所述第二半导体芯片之间延伸。
14.根据权利要求11所述的半导体封装件，还包括：
封装基板，其设置在所述插入基板的底表面上；以及
多个耦接焊料元件，其设置在所述封装基板和所述插入基板之间，
其中，所述插入基板包括半导体晶片，
其中，所述封装基板的热膨胀系数大于所述半导体晶片的热膨胀系数，并且
其中，所述模制层的热膨胀系数大于所述半导体晶片的热膨胀系数。
15.根据权利要求14所述的半导体封装件，还包括设置在所述封装基板和所述插入基板之间的下底填充层，
其中，所述下底填充层的热膨胀系数大于所述半导体晶片的热膨胀系数。
16.一种半导体封装件，包括：
插入基板；
多个焊料端子，其设置在所述插入基板的底表面上；
芯片堆叠件，其设置在所述插入基板的顶表面上，所述芯片堆叠件包括第一下半导体芯片和设置在所述第一下半导体芯片上的多个第一上半导体芯片；
多个第一凸块，其设置在所述插入基板和所述第一下半导体芯片之间；以及
模制层，其设置在所述插入基板上，
其中，所述第一下半导体芯片包括穿过其设置的多个贯通电极，
其中，所述插入基板包括半导体晶片、多个通孔、多个布线结构和多个插入焊盘，
其中，所述第一下半导体芯片包括：
安装区域，其设置在所述插入基板上；以及
外伸区域，其与所述插入基板间隔开，
其中，所述模制层包括：
第一模制图案，其设置在所述第一下半导体芯片的外伸区域处的底表面上并且覆盖所述插入基板的侧壁；以及
第二模制图案，其设置在所述第一模制图案上并且覆盖所述第一下半导体芯片的侧壁和所述多个第一上半导体芯片的侧壁，并且
其中，所述第一模制图案的热膨胀系数大于所述半导体晶片的热膨胀系数。
17.根据权利要求16所述的半导体封装件，还包括：
第二半导体芯片，其设置在所述插入基板的顶表面上；
多个第二凸块，其设置在所述插入基板和所述第二半导体芯片之间；以及
底填充层，其设置在所述插入基板和所述第一下半导体芯片之间并且还设置在所述插入基板和所述第二半导体芯片之间，
其中，所述芯片堆叠件包括彼此间隔开的第一芯片堆叠件和第二芯片堆叠件，
其中，所述第二半导体芯片设置在所述第一芯片堆叠件和所述第二芯片堆叠件之间，并且
其中，所述底填充层在所述第一模制图案的顶表面和所述第一下半导体芯片的外伸区域处的底表面之间延伸。
18.根据权利要求16所述的半导体封装件，还包括：
第一钝化图案，其覆盖所述插入基板的底表面和所述第一模制图案的底表面；以及
第二钝化图案，其设置在所述第一钝化图案的底表面上，
其中，所述第二钝化图案包括与所述第一钝化图案的材料不同的材料。
19.根据权利要求16所述的半导体封装件，还包括：
封装基板，其设置在所述插入基板的底表面上；
多个耦接焊料元件，其设置在所述封装基板和所述插入基板之间；
下底填充层，其设置在所述封装基板和所述插入基板之间并且覆盖所述多个焊料端子的侧壁；以及
加强件，其设置在所述封装基板的边缘区域上并与所述模制层横向间隔开。
20.根据权利要求16所述的半导体封装件，其中，所述第一模制图案的底表面位于与所述半导体晶片的底表面的水平实质上相同的水平处。
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