CN115132129A - Drive circuit, display module and display device - Google Patents
Drive circuit, display module and display device Download PDFInfo
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- CN115132129A CN115132129A CN202210796092.3A CN202210796092A CN115132129A CN 115132129 A CN115132129 A CN 115132129A CN 202210796092 A CN202210796092 A CN 202210796092A CN 115132129 A CN115132129 A CN 115132129A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
The application relates to a driving circuit, a display module and a display device. The driving circuit includes a signal control unit, a switching unit, a pixel array unit, and a charge discharging unit. The scanning input end of the signal control unit receives the scanning signal, and the signal control unit outputs a control signal according to the scanning signal. And the switch input end of the switch unit is electrically connected with the output signal end. The scanning signal input end of the pixel array unit is electrically connected to the first switch output end and the second switch output end of the switch unit at the same time. The first switch output end or the second switch output end is selectively conducted with the scanning signal input end, so that the scanning signal is selectively transmitted to the pixel array unit. The charge releasing unit releases the parasitic capacitance generated by the pixel array unit. The driving circuit selectively controls the scanning signals to be normally transmitted to the pixel array unit during line scanning, and the problem of afterglow abnormity caused by parasitic capacitance generated continuously during line scanning switching time is avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit, a display module with the driving circuit and a display device with the display module.
Background
In LED display devices such as a sub-millimeter Light Emitting Diode (Mini-LED) display, a Micro Light Emitting Diode (Micro-LED) display, and an Organic Light Emitting Diode (OLED) display using a Passive addressing (PM) driving mode, the requirements of the LED display device for line driving have been significantly increased along with the development of display technologies, particularly the development of small spacing between Light Emitting elements.
In the conventional driving circuit of the LED display device, for example, a common anode driving circuit is used, when a data signal of a control row is low, an anode voltage of a light emitting element is pulled high, and at this time, the light emitting element can generate light with different brightness according to the width of the data signal of a control column. At this time, in the process of switching the line scanning, the residual voltage of the line scanning line generates a parasitic capacitance. However, when other line scans are performed, because the line scan switching interval time is short, the charge on the parasitic capacitor is not released completely, and at this time, the parasitic capacitor and other line scan signals jointly act to make the light-emitting element that should be turned off emit light by mistake, so that afterglow, that is, an abnormal afterglow phenomenon, is generated on the display, and the display effect and the user experience are affected.
Disclosure of Invention
In view of the deficiencies of the prior art, the present application provides a driving circuit, a display module and a display device. The drive circuit is provided with the signal control unit and the switch unit, selectively controls the scanning signal input end to receive or stop receiving the scanning signal, effectively avoids the continuous increase of the parasitic capacitance in the switching time, aggravates the discharge workload of the charge release unit and solves the problem of afterglow abnormality caused by insufficient discharge capacity of the charge release unit.
In a first aspect, embodiments of the present application provide a driving circuit, which includes at least one signal control unit, a switching unit, a pixel array unit, and a charge discharging unit, wherein,
each signal control unit comprises a plurality of scanning input ends and output signal ends, the scanning input ends receive scanning signals, and the signal control units output control signals from the output signal ends according to the scanning signals;
the switch unit comprises a switch input end, a plurality of first switch output ends and a plurality of second switch output ends, and the switch input end is electrically connected with the output signal end and receives the control signal;
the pixel array unit comprises a plurality of scanning signal input ends and a plurality of charge output ends, wherein the plurality of scanning signal input ends are simultaneously and electrically connected to the plurality of first switch output ends and the plurality of second switch output ends, and the first switch output ends or the second switch output ends are selectively conducted with the scanning signal input ends according to the control signals, so that the scanning signals are selectively transmitted to the pixel array unit;
the charge discharging unit comprises a plurality of charge discharging terminals, each charge discharging terminal is electrically connected to each charge output terminal, and the charge discharging unit discharges at least part of charges of parasitic capacitance generated by the pixel array unit.
In an exemplary embodiment, the signal control unit is an or gate circuit, the or gate circuit includes the output signal terminal and a plurality of scan input terminals, the plurality of scan input terminals receive a plurality of scan signals, and the output signal terminal outputs a control signal at a first potential when at least one of the plurality of scan signals is at the first potential; when the scanning signals are all at the second electric potential, the output signal end outputs a control signal at the second electric potential.
In an exemplary embodiment, the switch unit includes a plurality of first transistors, each of the first transistors includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is electrically connected to the switch input terminal for receiving the control signal, the first terminal of the first transistor is for receiving the scan signal, and the second terminal of the first transistor is electrically connected to the first switch output terminal.
In an exemplary embodiment, when the control signal received by the control terminal is at a first potential, the first terminal and the second terminal of each of the first transistors are electrically connected, and a plurality of scan signals are transmitted from a plurality of scan signal input terminals to the pixel array unit;
when the control signal received by the control terminal is at a second potential, the first terminal and the second terminal of each first transistor are electrically disconnected.
In an exemplary embodiment, the switch unit further includes a plurality of second transistors, each of the second transistors includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor is electrically connected to the switch input terminal for receiving the control signal, and two terminals of each of the second transistors are electrically connected to two adjacent second switch output terminals, respectively. .
In an exemplary embodiment, when the control signal received by the control terminal is at a first potential, the first terminals and the second terminals of the plurality of second transistors are electrically disconnected;
when the control signal received by the control terminal is at a second potential, the first terminals and the second terminals of the plurality of second transistors are electrically conducted, the plurality of scanning signal input terminals are electrically conducted, and the plurality of scanning signals cannot be transmitted to the pixel array unit.
In an exemplary embodiment, the first transistor is an nmos transistor and the second transistor is a pmos transistor.
In an exemplary embodiment, the charge discharging unit includes a plurality of capacitors, one end of each of the capacitors is electrically connected to a corresponding charge discharging terminal, and the other end of each of the capacitors is electrically connected to a reference ground of the driving circuit.
In a second aspect, the present application further provides a display module, where the display module includes a display panel and a plurality of driving circuits, the driving circuits are electrically connected to the display panel, and the driving circuits are used for driving the display panel to display images.
In a third aspect, the present application further provides a display device, where the display device includes a power module and the display module, the power module is disposed on a non-display surface of the display module, and the power module is configured to provide a power voltage for the display module to perform image display.
In summary, in the driving circuit, the display module and the display device provided in the present application, the signal control unit and the switch unit are arranged to selectively control the plurality of scanning signal input terminals to receive or stop receiving the scanning signals. Effectively control drive circuit normal transmission scanning signal extremely pixel array unit when carrying out line scanning stops transmitting at line scanning switching time scanning signal extremely pixel array unit has avoided remaining scanning signal electric charge at line scanning switching time to continue to produce parasitic capacitance, has effectively avoided switching time parasitic capacitance to continue to increase, aggravates the work load of releasing of charge release unit, and the problem of afterglow that the charge release unit discharge capacity is not enough to cause is unusual.
In addition, the signal control unit and the switch unit are matched to control the short circuit of the scanning lines in the switching time, and therefore the discharge rate of charges on the capacitor electrically connected to the corresponding scanning lines is improved. Specifically, when a plurality of scanning lines are in short circuit, the charge discharge rate of the capacitor corresponding to the scanning line is increased by a multiple equal to the number of the scanning lines compared with the short circuit. The problem of afterglow abnormity caused by incomplete charge discharge or insufficient timely release of charges on the parasitic capacitor is greatly reduced, so that the driving correctness of the driving circuit is effectively improved, and the display effect of the display module is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a display module of the display device shown in FIG. 1;
FIG. 3 is a circuit diagram of a driving circuit of a display module in the display device shown in FIG. 1;
fig. 4 is a schematic circuit diagram of a specific circuit structure of the driving circuit of the first embodiment shown in fig. 3.
FIG. 5 is a schematic diagram of a specific circuit structure of the driving circuit of the second embodiment shown in FIG. 3;
fig. 6 is a schematic circuit diagram of a specific circuit structure of the driving circuit of the third embodiment shown in fig. 3.
Description of reference numerals:
100-a display device; 10-a display module; 20-a power module; 30-a support frame; 11. 12, 14-drive circuit; 13-a display panel; 17-a backlight module; 131-an array substrate; 132-a liquid crystal layer; 133-color film substrate; 40-a signal control unit; 50-a switching unit; 60-pixel array unit; 70-a charge releasing unit; 42-a scan input; 44-output signal terminal; 51-a switch input; 52-first switch output; 53-a second switch output; 56-a first transistor; 57-a second transistor; 61-scan signal input; 62-data signal input; 63-a charge output; 65-a light emitting unit; 71-capacitance; 73-charge release end; k-the number of scan lines per group that are adjusted; n-total number of scan lines of the drive circuit; f1 — first direction; f2 — second direction; S1-Sn-scan line; D1-Dm-data line; GND-ground reference.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). Directional phrases used in this application, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the application and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the application.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the drawings are used for distinguishing different objects and not for describing a particular order. Furthermore, the terms "comprises," "comprising," "includes," "including," or "including," when used in this application, specify the presence of stated features, operations, elements, and/or the like, but do not limit one or more other features, operations, elements, and/or the like. Furthermore, the terms "comprises" or "comprising" indicate the presence of the respective features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions. It is also to be understood that the term "at least one" as used herein means one and more than one, such as one, two or three, etc., and the term "plurality" means at least two, such as two or three, etc., unless specifically limited otherwise. The terms "step 1", "step 2", and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order.
In the field of display technology, a display device may generally include a display panel and a backlight assembly, wherein the display panel is mounted to a light emitting side of the backlight assembly, and the backlight assembly is used for providing backlight to the display panel to adjust the display panel to display different pictures. In a Thin Film Transistor-Liquid Crystal Display (TFT-LCD), a common electrode, a pixel electrode, a data (data) line, and Liquid Crystal molecules are disposed in the backlight assembly, wherein the voltage of the common electrode is a reference voltage, and the magnitude of a data signal of the data line is changed to release capacitance of the pixel electrode in different degrees, so that electric fields with different magnitudes are formed between the common electrode and the pixel electrode, and the electric fields with different magnitudes control the Liquid Crystal molecules in the backlight assembly to deflect in different degrees, so that the Display panel displays pictures with different gray scales.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device disclosed in an embodiment of the present application. As shown in fig. 1, the display device 100 provided in the embodiment of the present application may at least include a display module 10, a power module 20 and a supporting frame 30, wherein the display module 10 is fixed to the supporting frame 30, and the power module 20 is disposed on a back surface of the display module 10, that is, a non-display surface of the display module 10, that is, a side of the display module 10 opposite to a user. The display module 10 is used for displaying images, the power module 20 is electrically connected with the display module 10 and used for providing power voltage for the display module 10 to display images, and the supporting frame 30 provides supporting and protecting functions for the display module 10 and the power module 20.
It can be understood that the display module 10 further has a display surface opposite to the non-display surface, that is, the front surface of the display module 10, that is, the side of the display module 10 facing the user. The display surface is used to face a user using the display apparatus 100 to display an image.
Referring to fig. 2, fig. 2 is a schematic structural diagram of the display module 10 in the display device 100 shown in fig. 1. In the embodiment of the present application, the display Module 10 at least includes a display panel 13 and a Backlight Module (BM) 17, wherein the display panel 13 is disposed on the light emitting side of the Backlight Module 17, the Backlight Module 17 is configured to provide light for display to the display panel 13, and the display panel 13 emits corresponding light according to image data to be displayed to perform image display.
In the exemplary embodiment of the present application, the display module 10 may further include other elements or components, such as a signal processor module, a signal sensing module, and the like.
AS shown in fig. 2, the display panel 13 at least includes an Array Substrate (AS) 131, a color filter Substrate 133, and a liquid crystal layer 132 interposed between the Array Substrate 131 and the color filter Substrate 133. A corresponding electric field is generated between the array substrate 131 and the color filter substrate 133 according to image data to be displayed, so that liquid crystal molecules in the liquid crystal layer 132 are controlled to deflect by a corresponding angle to emit light rays with corresponding brightness, so as to perform image display. In this embodiment, the display panel 13 may be a Micro-LED display panel, an OLED display panel, a Mini-LED display panel, or the like, which adopts a passive addressing (PM) driving mode.
Referring to fig. 3, fig. 3 is a circuit diagram of the driving circuit 11 of the display module 10 in the display device 100 shown in fig. 1. In the embodiment of the present application, the display module 10 further includes at least a driving circuit 11, the driving circuit 11 may be disposed in a peripheral area of the display panel 13, and the driving circuit 11 is electrically connected to the display panel 13 and configured to supply power to the display panel 13 and provide a driving signal. The driving circuit 11 is electrically connected with the backlight module 17, and the driving circuit 11 and the backlight module 17 cooperate to enable the display panel 13 to display pictures.
In the embodiment of the present application, the driving circuit 11 may include at least one signal control unit 40, a switching unit 50, a pixel array unit 60, and a charge discharging unit 70. Each signal control unit comprises an output signal end and a plurality of scanning input ends, the scanning input ends receive scanning signals, and the signal control units output control signals from the output signal ends according to the scanning signals.
The switch unit comprises a switch input end, a plurality of first switch output ends and a plurality of second switch output ends, wherein the switch input end is electrically connected with the output signal end and receives the control signal.
The pixel array unit comprises a plurality of scanning signal input ends and a plurality of charge output ends, wherein the plurality of scanning signal input ends are simultaneously and electrically connected to the plurality of first switch output ends and the plurality of second switch output ends, and the first switch output ends or the second switch output ends are selectively conducted with the scanning signal input ends according to the control signals, so that the scanning signals are selectively transmitted to the pixel array unit.
The charge discharging unit comprises a plurality of charge discharging terminals, each charge discharging terminal is electrically connected to each charge output terminal, and the charge discharging unit discharges at least part of charges of parasitic capacitance generated by the pixel array unit.
In order to clearly illustrate the port number relationship of each unit, the number of each port and each component, for example, k scan input terminals, n scan signal input terminals, k-1 second transistors, etc., will be set below to further illustrate the technical solution of the present application. Where k is an integer greater than 1 and less than or equal to n, and n is an integer greater than or equal to 2, the number is "plural" or "several", so that the limitation of the number of k or n does not limit the technical solution, but only makes the technical solution clearer.
In the embodiment of the present application, each of the signal control units 40 includes k scan input terminals 42 and an output signal terminal 44. k of the scan inputs 42 receive k scan signals, i.e., each of the scan inputs 42 receives a corresponding scan signal. The signal control unit 40 outputs a control signal at the first potential or the second potential from the output signal terminal 44 according to the k scanning signals. It will be appreciated that the scan input 42 may receive the scan signal with a scan driver circuit or a row driver circuit.
Each of the switching units 50 comprises a switching input 51, k first switching outputs 52 and k second switching outputs 53. The switch input terminal 51 is electrically connected to the output signal terminal 44.
The pixel array unit 60 includes n scan signal input terminals 61 and n charge output terminals 63. The charge output terminal 63 is electrically connected to the charge discharging unit 70. Wherein k of the scan signal input terminals 61 are electrically connected to k of the first switch output terminals 52 and k of the second switch output terminals 53 at the same time. The switch unit 50 selectively connects the scan signal input terminal 61 and the first switch output terminal 52 or the second switch output terminal 53 according to the control signal. Further, the scan signal input terminal 61 is selectively turned on to transmit a corresponding scan signal to the pixel array unit 60 through the scan signal input terminal 61. Wherein the scan signal is generated by other circuit structures of the driving circuit 11 and can be transmitted to the scan signal input terminal 61.
The charge discharging unit 70 includes n charge discharging terminals 73, each of the charge discharging terminals 73 is electrically connected to each of the charge output terminals 63, and the charge discharging unit 70 is configured to discharge charges of a part of the parasitic capacitance generated by the pixel array unit 60. Specifically, each of the charge discharging terminals 73 is used to guide the discharging of the charge of the parasitic capacitance generated by the corresponding scan line.
In the embodiment of the present application, k is an integer greater than 1 and less than or equal to n, and n is an integer greater than or equal to 2. It is understood that the signal control unit 40 and the switch unit 50 may adjust only a portion of the scan signal input terminals 61 of the pixel array unit 60 to selectively receive the scan signal. For example, the scan lines that may interact with each other may be adjusted by the signal control unit 40 and the switching unit 50 according to the actual situation.
In the embodiment of the present application, the signal control unit 40 and the switch unit 50 are added to the driving circuit 11 to stop the transmission of the scan signal to the light emitting unit 65 of the pixel array unit 60 through the scan signal input terminal 61 during the time of switching the scan lines. Therefore, the problem that the parasitic capacitance of the pixel array unit 60 increases during the line switching time, so that the charge releasing unit 70 cannot fully discharge the charges on the parasitic capacitance during the interval time, thereby causing abnormal light emission of the pixel array unit 60 can be effectively avoided. Therefore, the accuracy of driving by the driving circuit 11 is effectively improved, so that the afterglow phenomenon is eliminated, and the display effect of the display module 10 is ensured.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of the driving circuit 11 of the first embodiment shown in fig. 3. In the embodiment of the present application, the pixel array unit 60 includes n Scan lines (Scan lines) S1 to Sn extending along the first direction F1 and m Data lines (Data lines) D1 to Dm extending along the second direction F2, which are arranged in a grid pattern. The first direction F1 and the second direction F2 are perpendicular to each other, and the plurality of scan lines S1 to Sn, the plurality of data lines D1 to Dm, and the scan lines S1 to Sn and the data lines D1 to Dm are insulated from each other. That is, the scan lines S1 to Sn are arranged at intervals along the second direction F2 and are insulated from each other, the data lines D1 to Dm are arranged at intervals along the first direction F1 and are insulated from each other, and the scan lines S1 to Sn and the data lines D1 to Dm are insulated from each other. Wherein each of the scan lines is used for transmitting the scan signal to the light emitting unit 65 through the scan signal input terminal 61. Wherein m is a positive integer.
As shown in fig. 4, in the embodiment of the present application, the pixel array unit 60 includes m data signal input terminals 62, n scan signal input terminals 61, and n × m light emitting units 65, each of the scan signal input terminals 61 is electrically connected to a first pole of m light emitting units 65, each of the data signal input terminals 62 is electrically connected to a second pole of n light emitting units 65, and the scan signal is transmitted to the light emitting units through the scan signal input terminals to control the light emitting units to be turned on and off. That is, each of the scan signal input terminals 61 is electrically connected to the first poles of m light emitting cells 65 in a corresponding row, and each of the data signal input terminals 62 is electrically connected to the second poles of n light emitting cells 65 in a corresponding column. That is, the first pole and the second pole of each of the light emitting cells 65 are electrically connected to the scan signal input terminal 61 and the data signal input terminal 62, respectively.
In the exemplary embodiment of the present application, the first pole of the light emitting unit 65 may be an anode, and the second pole of the light emitting unit 65 may be a cathode.
Referring to fig. 5 and fig. 6 together, fig. 5 is a specific circuit structure diagram of the driving circuit 12 of the second embodiment shown in fig. 3, and fig. 6 is a specific circuit structure diagram of the driving circuit 14 of the third embodiment shown in fig. 3.
In the embodiment of the present application, each of the signal control units 40 may be an or gate circuit, the or gate circuit includes k scan input terminals 42 and the output signal terminals 44, and k scan input terminals 42 receive k scan signals. The signal control unit 40 outputs a control signal having a first potential or a second potential from the output signal terminal 44 according to the potential condition of the received k scanning signals. Wherein k is a positive integer greater than 1 and less than or equal to n.
The scan signal may be at a first potential or a second potential. The scanning signals which are required to be transmitted when the scanning lines perform line scanning are at a first potential, and the scanning signals corresponding to the rest scanning lines which do not perform line scanning are at a second potential. The first potential may be a high potential and the second potential may be a low potential. Specifically, in the signal control unit 40, if the scanning signals are all at the second potential, the output signal terminal 44 outputs a control signal having the second potential to the switch unit 50.
If at least one of the scanning signals is at the first potential, the output signal terminal 44 outputs a control signal having the first potential to the switch unit 50.
Referring to fig. 5, in other embodiments of the present application, the number of the signal control units 40 may be 1, 2, 3 or other numbers, which is not specifically limited in the present application. It is understood that the number of scan lines for selectively transmitting scan signals among the k scan lines controlled by the signal control unit 40 may be determined according to the influence of a specific driving circuit.
For example, if the influence between the scan line S1 and the scan line S2 is easily generated, the signal control unit 40 may be disposed between the scan line S1 and the scan line S2, where the number k of the adjusted scan lines is 2.
If the influence between the scan line Sn and the scan line Sn-1 is easily generated, the signal control unit 40 may be disposed between the scan line Sn and the scan line Sn-1, where the number k of scan lines to be adjusted is 2.
If the influence between the scan line S1 and the scan line S2 and between the scan line Sn and the scan line Sn-1 is easily generated, one signal control unit 40 may be respectively disposed between the scan line S1 and the scan line S2 and between the scan line Sn and the scan line Sn-1, that is, one signal control unit 40 is disposed between the scan line S1 and the scan line S2 as a group, and another signal control unit 40 is disposed between the scan line Sn and the scan line Sn-1 as a group, where the adjusted number k of scan lines in each group is 2. One signal control unit 40 may be disposed between the scan line S1, the scan line S2, the scan line Sn, and the scan line Sn-1, where k is 4.
Further, the transmission of the scanning signals of a plurality of scanning lines which may influence one another is specifically regulated.
In the present embodiment, the switching unit 50 includes a switching input 51, k first switching outputs 52, and k second switching outputs 53. The switch input terminal 51 is electrically connected to the output signal terminal 44, and the switch input terminal 51 receives a control signal at a first potential or a second potential from the output signal terminal 44. The k first switch output terminals 52 are electrically connected to the k scan signal input terminals 61, and the k second switch output terminals 53 are electrically connected to the k scan signal input terminals 61.
Specifically, when the switch input terminal 51 receives a control signal at a first potential, the k first switch output terminals 52 are electrically connected to the k scanning signal input terminals 61, and at this time, the k scanning signal input terminals 61 receive the k scanning signals, and the k scanning signals correspondingly scan the plurality of light emitting units 65 in the corresponding row.
When the switch input terminal 51 receives a control signal at a second potential, the k second switch output terminals 53 are electrically connected to the k scanning signal input terminals 61, at this time, the k scanning signal input terminals 61 are electrically connected, that is, the k scanning lines are short-circuited, and the k scanning signal input terminals 61 stop receiving the k scanning signals, that is, the scanning lines corresponding to the k scanning signal input terminals 61 stop charging.
It will be appreciated that the output signal terminal 44 outputs the control signal at the second potential to the switch input terminal 51, indicating that it is in time to switch the scan line. Through with k electrical property switches on between the scanning signal input end 61, makes the scanning line that corresponds not continue to charge in the time of switching the scanning line, and then parasitic capacitance on this scanning line can not continue to increase, is favorable to promoting the efficiency of discharging parasitic capacitance at scanning line switching time and goes up the electric charge, has effectively avoided influencing between the scanning line to cause luminous unit 65 is luminous unusually and produces afterglow's phenomenon.
It is understood that k scan lines controlled to selectively transmit the scan signals are controlled by one signal control unit 40, and k-1 second transistors 57 are electrically connected between k scan signal input terminals 61. Further, k of the scan signal input terminals 61 are shorted by k-1 second transistors 57 during the switching row scan interval. In the driving circuit, a plurality of the signal control units 40 may be included in combination with the switching unit 50 for controlling a plurality of scan lines to selectively transmit a plurality of scan signals. Each of the signal control units 40 is combined with the switching unit 50, and is configured to control k scan lines to selectively transmit k scan signals.
In the embodiment of the present application, the switching unit 50 includes k first transistors 56 and k-1 second transistors 57. Specifically, each of the first transistors 56 includes a control terminal, a first terminal and a second terminal, the control terminal of the first transistor 56 is electrically connected to the switch input terminal 51 for receiving the control signal at the first potential or the second potential, and the control signal can control the first transistor 56 to be in a conducting state or a blocking state. A first terminal of the first transistor 56 is used for receiving the scan signal. A second terminal of the first transistor 56 is electrically connected to the first switch output terminal 52.
When the control signal is at the first potential, the control terminal of the first transistor 56 receives the control signal at the first potential, and the first transistor 56 is in a conducting state. The first terminal and the second terminal of the first transistor 56 are electrically connected. Further, the scan signal input terminal 61 is connected to the second terminal of the first transistor 56, and the scan signal input terminal 61 receives the scan signal.
When the control signal is at the second potential, the control terminal of the first transistor 56 receives the control signal having the second potential, and the first transistor 56 is in an off state. The first terminal and the second terminal of the first transistor 56 are electrically turned off. Further, the scan signal input terminal 61 is electrically disconnected from the second terminal of the first transistor 56, and the scan signal input terminal 61 cannot receive the scan signal, so that the scan line does not generate any parasitic capacitance.
The first potential is a high potential, and the second potential is a low potential. This is not particularly limited by the present application.
Each of the second transistors 57 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor 57 is electrically connected to the switch input terminal 51, that is, the control terminal of the first transistor 56 and the control terminal of the second transistor 57 are both electrically connected to the switch input terminal 51. The control terminal of the second transistor 57 is configured to receive a control signal at a first potential or a second potential, and the control signal may control the second transistor 57 to be in an on state or an off state.
A first terminal and a second terminal of each of the second transistors 57 are electrically connected to two adjacent second switch output terminals 53, respectively. Specifically, a first terminal of the ith transistor 57 is electrically connected to the ith second switch output terminal 53, and a second terminal of the ith transistor 57 is electrically connected to the (i + 1) th second switch output terminal 53. Wherein i is an integer of 1 to k. For example, a first terminal of the 1 st second transistor 57 is electrically connected to the 1 st second switch output terminal 53, and a second terminal of the 1 st second transistor 57 is electrically connected to the 2 nd second switch output terminal 53; a first terminal of the 2 nd second transistor 57 is electrically connected to the 2 nd second switch output 53, a second terminal of the 2 nd second transistor 57 is electrically connected to the 3 rd second switch output 53, and so on. Wherein i is an integer greater than 1 and less than k.
When the control signal is at the first potential (i.e., at a high potential), the control terminal of the second transistor 57 receives the control signal at the first potential, and the second transistor 57 is in an off state.
When the control signal is at the second potential (i.e., at the low potential), the control terminal of the second transistor 57 receives the control signal at the second potential, and the second transistor 57 is in a conducting state. The first terminal and the second terminal of the ith second transistor 57 are electrically connected, so that the ith second switch output terminal 53 is electrically connected to the (i + 1) th second switch output terminal 53. And then k scanning signal input end 61 electrical property switches on, k scanning line short circuit makes the discharge rate of charge release unit 70 increases at double, has effectively avoided the charge accumulation on the parasitic capacitance to lead to the unusual problem of afterglow.
In the embodiment of the present application, when at least one of the k scan signals has the first potential, the k scan inputs 42 receive the k scan signals. Since the output signal terminal 44 of the signal control unit 40 outputs the control signal at the first potential when at least one of the scanning signals received by the k scanning input terminals 42 is at the first potential. The control signal at the first potential is transmitted to the switch unit 50, the control terminal of the first transistor 56 receives the control signal at the first potential, the first transistor 56 is in a conducting state, the first terminal and the second terminal of the first transistor 56 are electrically conducting, and the scan signal is transmitted from the scan signal input terminal 61 to the pixel array unit 60. At this time, when the second transistor 57 is turned off, each scan line alone outputs a waveform required for its own line, and the short-circuit function of each scan line is disabled.
When the k scan signals are all at the second potential, the k scan inputs 42 receive the k scan signals at the second potential. Since the output signal terminal 44 of the signal control unit 40 outputs the control signal having the second potential when the scanning signals received by the k scanning input terminals 42 are all at the second potential. The control signal with the second potential is transmitted to the switch unit 50, the control signal at the second potential controls the k second switch output terminals 53 to be electrically conducted, that is, the k scanning signal input terminals 61 to be electrically conducted, the scanning signal cannot be transmitted to the corresponding scanning lines, that is, the scanning lines cannot continue to receive the residual scanning signal to generate parasitic capacitance, and each Scan alone outputs the waveform function required by the Scan line itself to be invalid, so that the scanning lines are short-circuited.
In the embodiment of the present application, the first transistor 56 may be an N-Metal-Oxide-Semiconductor (NMOS) transistor, and the second transistor 57 may be a P-Metal-Oxide-Semiconductor (PMOS) transistor.
In the embodiment of the present application, the charge discharging unit 70 may include a plurality of capacitors 71. In the embodiment of the present application, the number of the capacitors 71 is n. Wherein one end of each of the capacitors 71 is electrically connected to the corresponding charge discharging terminal 73, and the other end of each of the capacitors is electrically connected to a ground GND. The capacitor 71 is used for discharging charges on a parasitic capacitor generated by a corresponding scanning line in a row driving scanning process.
In this embodiment of the application, by additionally providing the signal control unit 40 and the switch unit 50, the k scan signal input terminals 61 are controlled to stop receiving k scan signals in the line scan switching time, and the k scan lines are short-circuited at the same time, so that the parasitic capacitance does not continue to increase in the switching time. Further, the efficiency of the capacitor 71 for releasing the charges on the parasitic capacitor is effectively improved. Specifically, when k is 4, the efficiency of the capacitor 71 to discharge the parasitic capacitance is increased by 4 times.
In the embodiment of the present application, when the driving circuit performs line scanning, a scanning signal corresponding to a scanning line to be scanned is at a first potential, and during a period of switching the scanning line, a potential on the scanning line is switched from the first potential to a second potential. At this time, the signals of all the scanning lines are at the second potential, but the first potential charges on the scanning lines are remained during scanning, so that parasitic capacitance is generated. In the embodiment of the present application, during the time of switching the scan lines, by additionally providing the signal control unit 40 and the switch unit 50, the scan lines that may be affected by each other are disconnected by utilizing the characteristic that the scan signals have the second potential during the switching time, so that the problem of continuously increasing the parasitic capacitance due to the fact that the residual charges continuously charge the scan lines during the time of switching the scan lines is avoided, and the accuracy of the driving circuit driving the light emitting unit 65 to emit light is effectively improved. In addition, through setting up switch unit 50, will utilize the characteristic that the switching time scanning signal all has the second potential, will probably influence each other's scanning line short circuit, make charge release unit 70's charge bleed rate doubly increases, has effectively avoided the charge on the parasitic capacitance to bleed and to lead to the problem that the afterglow is unusual slowly.
An exemplary circuit structure of the driving circuit is illustrated below by taking specific circuit structure diagrams of different embodiments of the driving circuit shown in fig. 4, fig. 5 and fig. 6 as examples.
As shown in fig. 4, in one embodiment of the present application, the driving circuit 11 includes 1 signal control unit 40 and 1 switching unit 50, for controlling 4 scan lines to selectively receive the scan signals. The 4 controlled scan lines may be scan line S1, scan line S2, scan line Sn-1, and scan line Sn illustrated in the figure, which is not specifically limited in the present application.
At this time, the signal control unit 40 includes 4 scan inputs 42, and the 4 scan inputs 42 receive 4 scan signals along the scan line S1, the scan line S2, the scan line Sn-1, and the scan line Sn. The switching unit 50 includes four first transistors 56 and three second transistors 57.
When at least one of the 4 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. The switch input terminal 51 is electrically connected to the 4 first switch output terminals 52, the scan signal input terminal 61 is electrically connected to the 4 first switch output terminals 52, and the scan signal is transmitted to the corresponding 4 rows of the pixel array unit 60, so as to further control the light emitting units 65 of the corresponding 4 rows.
When the 4 scan signals are all at the second potential, the output signal terminal 44 outputs a control signal at the second potential to the switching unit 50. In the switch unit 50, the switch input terminal 51 is electrically connected to 4 of the second switch output terminal 53, 4 of the scan signal input terminal 61, that is, 4 of the scan lines are short-circuited, the scan signal stops being transmitted to the corresponding 4 rows of the pixel array unit 60, further, the charge discharging efficiency of the charge discharging unit 70 is correspondingly improved by 4 times, the efficiency of discharging the charges on the parasitic capacitor is effectively improved, and the phenomenon that the parasitic capacitor is abnormal in afterglow due to the fact that the charges cannot be timely and sufficiently discharged is eliminated.
As shown in fig. 5, in one embodiment of the present application, the driving circuit 12 includes 1 signal control unit 40 and 1 switching unit 50 for controlling 2 scan lines to selectively receive the scan signals. The 2 controlled scan lines may be scan line S1 and scan line Sn illustrated in the figure, which is not specifically limited in the present application.
At this time, the signal control unit 40 includes 2 scan input terminals 42, and 2 scan input terminals 42 receive 2 scan signals along the scan line S1 and the scan line Sn. The switching unit 50 includes 2 first transistors 56 and 1 second transistor 57.
When at least one of the 2 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. The switch input terminal 51 is electrically connected to 2 of the first switch output terminals 52, 2 of the first switch output terminals 52 are electrically connected to 2 of the scan signal input terminals 61, and the scan signal is transmitted to the corresponding 2 rows of the pixel array unit 60, so as to further control the plurality of light emitting units 65 corresponding to the 2 rows.
When the 2 scan signals are all at the second potential, the output signal terminal 44 outputs a control signal at the second potential to the switch unit 50. In the switch unit 50, the switch input end 51 is electrically connected to 2 the second switch output end 53, 2 the scanning signal input end 61 is electrically connected, that is, 2 the scanning lines are short-circuited, the scanning signal stops being transmitted to the corresponding 2 rows of the pixel array unit 60, further, the charge discharging efficiency of the charge discharging unit 70 is correspondingly improved by 2 times, the efficiency of discharging the charges on the parasitic capacitor is effectively improved, and the phenomenon that the parasitic capacitor is abnormal in afterglow due to the fact that the charges cannot be timely and sufficiently discharged is eliminated.
As shown in fig. 6, in one embodiment of the present application, the driving circuit 14 includes 2 signal control units 40 and 2 switch units 50, and each signal control unit 40 and each switch unit 50 are combined to control 2 scan lines to selectively receive the scan signals. I.e. 4 scan lines in total. The 4 controlled scan lines may be scan line S1, scan line S2, scan line Sn-1, and scan line Sn-2, which are illustrated in the drawing, and the present application is not particularly limited thereto.
At this time, each of the signal control units 40 includes 2 scan input terminals 42, and one signal control unit 40 receives 2 scan signals along the scan line S1 and the scan line S2. The switching unit 50 used in cooperation with the signal control unit 40 includes 2 first transistors 56 and 1 second transistor 57.
The other signal control unit 40 receives two scan signals along the scan line Sn-1 and the scan line Sn. The switching unit 50 used in cooperation with the signal control unit 40 includes 2 first transistors 56 and 1 second transistor 57.
When at least one of the 2 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. In the switch unit 50, the switch input terminal 51 is electrically connected to 2 of the first switch output terminals 52, 2 of the first switch output terminals 52 are electrically connected to 2 of the scan signal input terminals 61, the scan signal is transmitted to the corresponding 2 rows of the pixel array unit 60, and further, the plurality of light emitting units 65 corresponding to 2 rows can be controlled. When the 2 scan signals are all at the second potential, the output signal terminal 44 outputs a control signal at the second potential to the switch unit 50. In the switch unit 50, the switch input end 51 is electrically connected to 2 of the second switch output end 53, 2 of the scanning signal input end 61 is electrically connected, namely two short-circuited scanning lines, the scanning signal stops being transmitted to two corresponding lines of the pixel array unit 60, further, the charge discharging efficiency of the charge releasing unit 70 is correspondingly improved by 2 times, the efficiency of discharging charges on the parasitic capacitor is effectively improved, and the phenomenon of afterglow abnormality caused by the fact that the charges cannot be timely and sufficiently released in the parasitic capacitor is eliminated.
Based on the same inventive concept, the application further provides a display module 10, wherein the display module 10 comprises the driving circuit and a display panel 13, the driving circuit is electrically connected with the display panel 13, and the driving circuit is used for driving the display panel 13 to display different pictures.
Based on the same inventive concept, the application further provides a display device 100, the display device 100 includes a display module 10 and a power module 20, the power module 20 is disposed on a non-display surface of the display module 10, and the power module 20 is configured to provide a power voltage for image display of the display module 10.
It is understood that the display device 100 provided in the embodiments of the present application may be any product or component having a display function, such as a display screen of a notebook computer, a liquid crystal display, a liquid crystal television, a mobile phone, and a tablet computer.
In one embodiment, the display device 100 further includes other necessary components and components such as a high-pressure board, a key control board, etc., and those skilled in the art can perform corresponding supplementation according to the specific type and actual functions of the display device 100, which will not be described herein again.
It is understood that the display apparatus 100 can also be used in electronic devices such as a Personal Digital Assistant (PDA) and/or a music player, such as a mobile phone, a tablet computer, a wearable electronic device (e.g., a smart watch) with a wireless communication function, and the like. The electronic device may also be other electronic devices such as a Laptop computer (Laptop) with a touch sensitive surface (e.g., a touch panel), etc.
In summary, in the driving circuit, the display module 10 and the display device 100 provided in the present application, the signal control unit 40 and the switch unit 50 are configured to selectively control k scanning signal input terminals 61 to receive or stop receiving the scanning signal, so as to effectively control the driving circuit to normally transmit the scanning signal to the pixel array unit 60 during the line scanning, and stop transmitting the scanning signal to the pixel array unit 60 during the line scanning switching time, thereby avoiding parasitic capacitance generated by the scanning signal charges remaining during the line scanning switching time, effectively avoiding parasitic capacitance increase during the switching time, increasing the discharge workload of the charge release unit 70, and causing afterglow abnormality due to insufficient discharge capability of the charge release unit 70. In addition, the signal control unit 40 and the switch unit 50 cooperate to control the k scan lines to be shorted at the switching time, thereby increasing the discharge rate of the charges on the capacitors 71 electrically connected to the corresponding scan lines. Specifically, if k scan lines are short-circuited, the charge draining rate of the capacitor 71 corresponding to the scan line is increased by k times compared with that of the capacitor without short-circuit. Greatly reduced because the charge on the parasitic capacitance is released not completely or can't get enough in time and release and the unusual problem of afterglow that causes to effectively improved drive circuit driven exactness has guaranteed display module 10's display effect.
All possible combinations of the respective technical features in the above embodiments are described, however, the combination of the technical features should be considered as the scope of the present specification as long as there is no contradiction therebetween.
In the description of the present specification, reference to the description of "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that the above-described examples merely represent several embodiments of the present application, which are described in greater detail and detail, but are not to be construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (10)
1. A driving circuit comprising at least one signal control unit, a switching unit, a pixel array unit, and a charge discharging unit, wherein,
each signal control unit comprises a plurality of scanning input ends and output signal ends, the scanning input ends receive scanning signals, and the signal control units output control signals from the output signal ends according to the scanning signals;
the switch unit comprises a switch input end, a plurality of first switch output ends and a plurality of second switch output ends, and the switch input end is electrically connected with the output signal end and receives the control signal;
the pixel array unit comprises a plurality of scanning signal input ends and a plurality of charge output ends, wherein the plurality of scanning signal input ends are simultaneously and electrically connected to a plurality of first switch output ends and a plurality of second switch output ends, and the first switch output ends or the second switch output ends are selectively conducted with the scanning signal input ends according to the control signals, so that the scanning signals are selectively transmitted to the pixel array unit;
the charge discharging unit comprises a plurality of charge discharging terminals, each charge discharging terminal is electrically connected to each charge output terminal, and the charge discharging unit discharges at least part of charges of parasitic capacitance generated by the pixel array unit.
2. The driving circuit according to claim 1, wherein the signal control unit is an or gate circuit, the or gate circuit including the output signal terminal and a plurality of the scan input terminals, the plurality of the scan input terminals receiving a plurality of the scan signals, the output signal terminal outputting a control signal at a first potential when at least one of the plurality of the scan signals is at the first potential; when the scanning signals are all at the second electric potential, the output signal end outputs a control signal at the second electric potential.
3. The driving circuit as claimed in claim 1, wherein the switching unit comprises a plurality of first transistors, each of the first transistors comprises a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is electrically connected to the switching input terminal for receiving the control signal, the first terminal of the first transistor is for receiving the scan signal, and the second terminal of the first transistor is correspondingly electrically connected to the first switching output terminal.
4. The driving circuit according to claim 3, wherein when the control signal received by the control terminal is at a first potential, the first terminal and the second terminal of each of the first transistors are electrically connected, and a plurality of the scan signals are transmitted from a plurality of the scan signal input terminals to the pixel array unit;
when the control signal received by the control terminal is at a second potential, the first terminal and the second terminal of each first transistor are electrically disconnected.
5. The driving circuit as claimed in claim 4, wherein the switching unit further comprises a plurality of second transistors, each of the second transistors comprises a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor is electrically connected to the switching input terminal for receiving the control signal, and two terminals of each of the second transistors are electrically connected to two adjacent second switching output terminals respectively.
6. The driving circuit according to claim 5, wherein when the control signal received by the control terminal is at a first potential, the first terminals and the second terminals of the plurality of second transistors are electrically disconnected;
when the control signal received by the control terminal is at a second potential, the first terminals and the second terminals of the plurality of second transistors are electrically conducted, the input terminals of the plurality of scanning signals are electrically conducted, and the plurality of scanning signals cannot be transmitted to the pixel array unit.
7. The driver circuit according to claim 6, wherein the first transistor is an N-type metal oxide semiconductor transistor and the second transistor is a P-type metal oxide semiconductor transistor.
8. The drive circuit according to any one of claims 1 to 7, wherein the charge discharging unit includes a plurality of capacitors, one end of each of the capacitors is electrically connected to a corresponding one of the charge discharging terminals, and the other end of each of the capacitors is electrically connected to a reference ground of the drive circuit.
9. A display module, the display module comprises a display panel and a plurality of drive circuits according to any one of claims 1 to 8, the drive circuits are electrically connected with the display panel, and the drive circuits are used for driving the display panel to display pictures.
10. A display device, the display device comprising a power module and the display module of claim 9, wherein the power module is disposed on a non-display surface of the display module, and the power module is used for providing a power voltage for the display module to display images.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210796092.3A CN115132129B (en) | 2022-07-07 | 2022-07-07 | Driving circuit, display module and display device |
| PCT/CN2022/137574 WO2024007529A1 (en) | 2022-07-07 | 2022-12-08 | Driving circuit, display module, and display apparatus |
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| CN202210796092.3A CN115132129B (en) | 2022-07-07 | 2022-07-07 | Driving circuit, display module and display device |
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| CN115953983A (en) * | 2023-03-09 | 2023-04-11 | 惠科股份有限公司 | Display panel, driving method of display panel, and display device |
| CN116246566A (en) * | 2023-01-30 | 2023-06-09 | 惠科股份有限公司 | Display panel and electronic equipment |
| CN116416928A (en) * | 2023-06-08 | 2023-07-11 | 惠科股份有限公司 | Display device and electronic apparatus |
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| CN116416928A (en) * | 2023-06-08 | 2023-07-11 | 惠科股份有限公司 | Display device and electronic apparatus |
| CN116416928B (en) * | 2023-06-08 | 2023-09-19 | 惠科股份有限公司 | Display device and electronic apparatus |
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| CN115132129B (en) | 2023-08-08 |
| WO2024007529A1 (en) | 2024-01-11 |
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