CN115035929A

CN115035929A - Circuit, method and electronic equipment for efficiently realizing clock domain crossing of pseudo DDR signal

Info

Publication number: CN115035929A
Application number: CN202210731207.0A
Authority: CN
Inventors: 杨建国; 程锦辉
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2022-09-09

Abstract

The invention discloses a circuit, a method and an electronic device for efficiently realizing clock domain crossing of a pseudo DDR signal, and relates to the technical field of circuit design, wherein the circuit comprises: the system comprises a chip end high-frequency clock domain module, a plurality of clock domain crossing modules arranged on the chip end high-frequency clock domain module and a host end low-frequency clock domain module connected with the clock domain crossing modules; each clock spanning module comprises a low-frequency-to-high-frequency transmission sub-module and a high-frequency-to-low-frequency transmission sub-module, one end of the low-frequency-to-high-frequency transmission sub-module is connected with the chip-end high-frequency clock domain module, the other end of the low-frequency-to-high-frequency transmission sub-module is connected with the host-end low-frequency clock domain module, one end of the high-frequency-to-low-frequency transmission sub-module is connected with the chip-end high-frequency clock domain module, and the other end of the high-frequency-to-low-frequency transmission sub-module is connected with the host-end low-frequency clock domain module; the synchronous clock-crossing domain transmission method can simultaneously process scenes with high timing sequence requirements such as synchronous clock-crossing domain transmission between single-cycle signals and multi-cycle signals, avoid multi-domain transmission of a metastable state, and improve the stability and reliability of the circuit.

Description

Circuit, method and electronic equipment for efficiently realizing clock domain crossing of pseudo DDR signal

Technical Field

The invention relates to the technical field of circuit design, in particular to a circuit, a method and electronic equipment for efficiently realizing clock domain crossing of a pseudo DDR signal.

Background

Simple digital integrated circuits are synchronous logic circuits driven by a single clock. The flip-flop in the circuit is turned over under the control of a unified clock, the time sequence constraint is simpler, and the design of a clock system is easier. However, a single clock constraint has long been no longer suitable for the rapidly increasing scale of integrated circuits at the present stage. There are typically multiple clock domains in a large scale digital circuit design process where the functionality is complex. How to solve the problem of signal propagation across Clock Domains (CDC), implementing output driving and input sampling of signals, and reducing or avoiding generation of metastable states has become a key problem in determining success or failure of digital integrated circuit design.

The most common way to solve the clock domain crossing at present is to use a synchronizer to sample an asynchronous input signal, so that the generated output signal meets the requirements of a synchronous system on setup time (setup time) and hold time (hold time), thereby inhibiting the adverse effect of a metastable state on a circuit. Two methods of synchronization are commonly used: a two-stage flip-flop method and a latch method.

The essence of the two-stage flip-flop method is to reduce the probability of occurrence of metastable state, and through the cascade of two-stage flip-flops, when a signal from a previous clock domain reaches the first flip-flop of a next clock domain, it is likely that the setup/hold time is not satisfied, resulting in the stage output being metastable for a long time. If the state of the second stage lasts less than one cycle, the metastable state can be eliminated by adding a stage flip-flop, so that the output end of the second stage flip-flop meets the requirement of a synchronous signal, but the 1-stage delay of an input signal can be increased by only adding a 1-stage D flip-flop. The method is generally used for circuit synchronization with low time sequence requirements, is suitable for small-quantity signal synchronization from a slow clock to a fast clock, and cannot realize bidirectional synchronization with high time sequence requirements and a large quantity of signals between fast and slow clock domains.

The locking method mainly solves the problem that when a signal transits from a fast clock to a slow clock in the synchronization process of a two-stage starting device, if the signal changes too fast, the slow clock may not sample the fast clock in time. The locking method synchronizer is used as a supplement to a two-stage trigger method, and still cannot meet the high time sequence requirement of synchronous cross-domain propagation of a large number of control signals and data signals between fast and slow clock domains, so that multi-domain propagation of a metastable state occurs, and the stability and reliability of a system are reduced.

Disclosure of Invention

The invention aims to provide a circuit, a method and electronic equipment for efficiently realizing cross-clock domain of a pseudo DDR signal, and solve the problems that the existing clock domain crossing mode cannot meet the high time sequence requirement of synchronous cross-domain propagation of a large number of control signals and data signals between a fast clock domain and a slow clock domain, so that multi-domain propagation of a metastable state occurs, and the stability and the reliability of a system are reduced

In a first aspect, the present invention provides a circuit for efficiently implementing clock domain crossing of a pseudo DDR signal, the circuit comprising:

the system comprises a chip-end high-frequency clock domain module, a plurality of clock domain crossing modules arranged on the chip-end high-frequency clock domain module and a host-end low-frequency clock domain module connected with the clock domain crossing modules;

each clock domain crossing module comprises a low-frequency-to-high-frequency transmission sub-module and a high-frequency-to-low-frequency transmission sub-module, one end of the low-frequency-to-high-frequency transmission sub-module is connected with the chip-end high-frequency clock domain module, the other end of the low-frequency-to-high-frequency transmission sub-module is connected with the host-end low-frequency clock domain module, one end of the high-frequency-to-low-frequency transmission sub-module is connected with the chip-end high-frequency clock domain module, and the other end of the high-frequency-to-low-frequency transmission sub-module is connected with the host-end low-frequency clock domain module;

the low-frequency to high-frequency transmission sub-module is used for adjusting a write control signal and a write data signal from a low-frequency clock domain to a high-frequency clock domain respectively under the condition of receiving the write control signal and the write data signal corresponding to a write operation instruction sent by the host-end low-frequency clock domain module, performing synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sending the write control signal and the write data signal subjected to synchronous alignment processing to the chip-end high-frequency clock domain module;

and the high-frequency-to-low-frequency transmission sub-module is used for finishing reading of corresponding data based on the read data signal under the condition of receiving the read data signal corresponding to the read operation instruction sent by the host-end low-frequency clock domain module.

With the adoption of the technical scheme, in the circuit for efficiently realizing clock domain crossing of the pseudo DDR signal provided by the embodiment of the present invention, the low-frequency to high-frequency transmission sub-module is configured to, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module; the high-frequency-to-low-frequency transmission sub-module is used for completing reading of corresponding data based on the read data signals when the read data signals corresponding to the read operation instructions sent by the host-end low-frequency clock domain module are received, and can simultaneously process high-timing-sequence-requirement scenes such as synchronous cross-clock-domain propagation between single-cycle and multi-cycle signals.

In a possible implementation manner, the low-frequency-to-high-frequency transmission sub-module includes an asynchronous first-in first-out control signal transmission unit and a data signal transmission unit, one end of the asynchronous first-in first-out control signal transmission unit is connected with the chip-side high-frequency clock domain module, the other end of the asynchronous first-in first-out control signal transmission unit is connected with the host-side low-frequency clock domain module, one end of the data signal transmission unit is connected with the chip-side high-frequency clock domain module, and the other end of the data signal transmission unit is connected with the host-side low-frequency clock domain module;

the low-frequency-to-high-frequency transmission sub-module is configured to, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module, and includes:

the asynchronous first-in first-out control signal transmission unit is used for adjusting the write control signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write control signal corresponding to the write operation instruction sent by the host end low-frequency clock domain module;

the data signal transmission unit is used for adjusting the write data signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write data signal corresponding to the write operation instruction sent by the host end low-frequency clock domain module;

the asynchronous first-in first-out control signal transmission unit and the data signal transmission unit are further configured to perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module.

In a possible implementation manner, the circuit further includes a plurality of memory modules, the memory modules are disposed on the chip-side high-frequency clock domain module, and the plurality of memory modules are respectively connected to each of the clock domain crossing modules in a one-to-one correspondence manner.

In a possible implementation manner, the asynchronous fifo control signal transmission unit is configured to adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, and includes:

the asynchronous first-in first-out control signal transmission unit is used for writing the write control signal into the asynchronous first-in first-out control signal transmission unit under the condition that the write control signal corresponding to the write operation instruction sent by the host-end low-frequency clock domain module is received and under the condition that the asynchronous first-in first-out control signal transmission unit is detected to be in a preset normal state according to a preset first transmission depth value;

the preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and is not in a non-read and non-write state.

In a possible implementation manner, the data signal transmission unit is configured to adjust a write data signal from a low-frequency clock domain to a high-frequency clock domain when receiving the write data signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, and includes:

and the data signal transmission unit is used for determining a corresponding data transmission signal to be transmitted each time according to a preset second transmission depth value under the condition of receiving the data writing signal sent by the host end low-frequency clock domain module, storing the data writing transmission signal in the corresponding memory module until the transmission frequency reaches the second transmission depth value, and sequentially reading all the data writing transmission signals from the data transmission unit according to a storage and writing sequence.

In a second aspect, the present invention further provides a method for efficiently implementing clock domain crossing of a pseudo DDR signal, which is applied to any one of the circuits for efficiently implementing clock domain crossing of a pseudo DDR signal in the first aspect, and the method includes:

under the condition that a low-frequency to high-frequency transmission sub-module receives a write control signal and a write data signal corresponding to a write operation instruction sent by a host end low-frequency clock domain module, the low-frequency to high-frequency transmission sub-module respectively adjusts the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, performs synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sends the write control signal and the write data signal subjected to synchronous alignment processing to a chip end high-frequency clock domain module;

and the high-frequency to low-frequency transmission sub-module finishes reading corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction sent by the host end low-frequency clock domain module.

In a possible implementation manner, the low-frequency-to-high-frequency transmission sub-module includes an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit, and when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, the low-frequency-to-high-frequency transmission sub-module adjusts the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, performs synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sends the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module, including:

the asynchronous first-in first-out control signal transmission unit adjusts the write control signal from a low-frequency clock domain to a high-frequency clock domain under the condition that the asynchronous first-in first-out control signal transmission unit receives the write control signal corresponding to the write operation command sent by the host end low-frequency clock domain module;

the data signal transmission unit adjusts the write data signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write data signal corresponding to the write operation instruction sent by the host end low-frequency clock domain module;

the asynchronous first-in first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal which are subjected to synchronous alignment processing to the chip end high-frequency clock domain module.

In a possible implementation manner, the adjusting, by the asynchronous fifo control signal transmission unit, the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module includes:

the asynchronous first-in first-out control signal transmission unit writes the write control signal into the asynchronous first-in first-out control signal transmission unit under the condition that the asynchronous first-in first-out control signal transmission unit detects that the asynchronous first-in first-out control signal transmission unit is in a preset normal state according to a preset first transmission depth value under the condition that the write control signal corresponding to the write operation instruction sent by the host-end low-frequency clock domain module is received;

In a possible implementation manner, when receiving a write data signal corresponding to the write operation command sent by the host-side low-frequency clock domain module, the data signal transmission unit adjusts the write data signal from a low-frequency clock domain to a high-frequency clock domain, including:

and the data signal transmission unit determines that the corresponding write data transmission signal is transmitted each time according to a preset second transmission depth value under the condition that the write data signal transmitted by the host-end low-frequency clock domain module is received, stores the write data transmission signal in the corresponding memory module until the transmission times reach the second transmission depth value, and sequentially reads all the write data transmission signals from the data transmission unit according to the sequence of storing and writing.

The beneficial effect of the method for efficiently implementing the clock domain crossing of the pseudo DDR signal provided by the second aspect is the same as that of the circuit for efficiently implementing the clock domain crossing of the pseudo DDR signal described in the first aspect or any one of the possible implementation manners of the first aspect, and details are not described here.

In a third aspect, the present invention also provides an electronic device, including: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to perform a method for efficiently implementing a pseudo-DDR signal across clock domains as described in any one of the possible implementations of the second aspect.

The beneficial effect of the electronic device provided in the third aspect is the same as that of the method for efficiently implementing crossing clock domains by pseudo DDR signals described in the second aspect or any possible implementation manner of the second aspect, and details are not repeated here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:

fig. 1 shows a schematic structural diagram of a circuit for efficiently implementing a clock domain crossing of a pseudo DDR signal according to an embodiment of the present application;

FIG. 2 is a timing diagram illustrating operations of write operation signals according to an embodiment of the present application;

FIG. 3 is a timing diagram illustrating operation of a read operation signal according to an embodiment of the present disclosure;

fig. 4 shows a schematic diagram of waveforms before and after a clock domain crossing from a host-side low-frequency clock domain module to a chip-side high-frequency clock domain module according to an embodiment of the present application;

fig. 5 illustrates a schematic waveform diagram before and after a clock domain is spanned from a chip-side high-frequency clock domain module to a host-side low-frequency clock domain module according to an embodiment of the present application;

fig. 6 is a schematic flowchart illustrating a method for efficiently implementing clock domain crossing of a pseudo DDR signal according to an embodiment of the present application;

fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a common type of memory used as RAM for most modern processors. In order to match with the actual application requirement, the pseudo DDR signal singles the double edge transmission characteristic of the standard DDR, and simplifies unnecessary DDR regulations according to the application scene, such as fixing the Burst length, eliminating the non-common DDR signal, and the like. However, considering the pseudo DDR, there is still a bi-directional cross-domain propagation signal, and there is a problem of synchronous cross-domain propagation between a specific Read/Write (Read/Write) command and the data transferred therewith. Therefore, the method can efficiently solve the key clock domain crossing propagation problem, avoid the propagation of the metastable state among different clock domains on the basis of realizing the basic functions of the system, and reduce the level disorder of the system so as to achieve the purpose of improving the stability and the reliability of the system, and has wide application prospect in the era of super-large-scale integrated circuits with increasingly complex functions in the future.

Fig. 1 shows a schematic structural diagram of a circuit for efficiently implementing a clock domain crossing of a pseudo DDR signal according to an embodiment of the present application, and as shown in fig. 1, the circuit for efficiently implementing a clock domain crossing of a pseudo DDR signal includes:

a chip-side high-frequency clock domain module 101, a plurality of clock domain crossing modules 102 arranged on the chip-side high-frequency clock domain module 101, and a host-side low-frequency clock domain module 103 connected with the clock domain crossing modules 102;

each clock domain crossing module 102 includes a low-frequency-to-high-frequency transmission sub-module 1021 and a high-frequency-to-low-frequency transmission sub-module 1022, one end of the low-frequency-to-high-frequency transmission sub-module 1021 is connected with the chip-side high-frequency clock domain module 101, the other end of the low-frequency-to-high-frequency transmission sub-module is connected with the host-side low-frequency clock domain module 103, one end of the high-frequency-to-low-frequency transmission sub-module 1022 is connected with the chip-side high-frequency clock domain module 101, and the other end of the high-frequency-to-low-frequency transmission sub-module is connected with the host-side low-frequency clock domain module 103.

The low-frequency-to-high-frequency transmission sub-module is used for adjusting the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain respectively under the condition of receiving the write control signal and the write data signal corresponding to a write operation instruction sent by the host-end low-frequency clock domain module, performing synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sending the write control signal and the write data signal subjected to synchronous alignment processing to the chip-end high-frequency clock domain module;

and the high-frequency to low-frequency transmission submodule is used for finishing reading of corresponding data based on the read data signal under the condition of receiving the read data signal corresponding to the read operation command sent by the host end low-frequency clock domain module.

In the present application, the high frequency to low frequency transmission sub-module 1022 includes a first-in-first-out QUEUE (QUEUE) 1022A.

In the circuit for efficiently implementing clock domain crossing of a pseudo DDR signal provided in the embodiment of the present invention, the low-frequency to high-frequency transmission sub-module is configured to, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module; the high-frequency-to-low-frequency transmission sub-module is used for completing reading of corresponding data based on the read data signals when the read data signals corresponding to the read operation instructions sent by the host-end low-frequency clock domain module are received, and can simultaneously process high-timing-sequence-requirement scenes such as synchronous cross-clock-domain propagation between single-cycle and multi-cycle signals.

Optionally, referring to fig. 1, the circuit further includes a plurality of memory modules 104, the memory modules 104 are disposed on the chip-side high-frequency clock domain module 101, and the plurality of memory modules 104 are respectively connected to each of the clock domain crossing modules 102 in a one-to-one correspondence manner.

Optionally, referring to fig. 1, the low-frequency-to-high-frequency transmission sub-module 1021 includes an asynchronous first-in first-out control signal transmission unit 1021A and a data signal transmission unit 1021B, one end of the asynchronous first-in first-out control signal transmission unit 1021A is connected to the chip-side high-frequency clock domain module 101, the other end of the asynchronous first-in first-out control signal transmission unit 1021A is connected to the host-side low-frequency clock domain module 103, one end of the data signal transmission unit 1021B is connected to the chip-side high-frequency clock domain module 101, and the other end of the data signal transmission unit 1021B is connected to the host-side low-frequency clock domain module 103.

Wherein the HOST side low frequency clock domain module may be HOST, wherein HOST is a 100 MHz low frequency clock, and the chip side high frequency clock domain module may be DEVICE, wherein DEVICE is a 400 MHz high frequency clock.

When the HOST-side low-frequency clock domain module executes WRITE (WRITE) operation, the HOST side can send a control (WRITE) signal, a synchronous DATA (DATA) signal, a non-READ non-WRITE (NOP) signal and the like to the DEVICE side, and when READ (READ) operation is executed, the DEVICE side only sends a DATA signal to the HOST side.

Optionally, fig. 2 shows an operation timing diagram of a WRITE operation signal provided in an embodiment of the present application, as shown in fig. 2, a CTRL signal lasts for one clock cycle, and then follows a NOP operation for several cycles, when a WRITE operation is performed, the HOST issues a WRITE signal, and 8 cycles of DATA are synchronously sent to the DEVICE while sending the WRITE instruction, no instruction other than the NOP instruction is issued until DATA sending is finished, and the signal odt ═ 1 indicates that DATA is written to the DEVICE by the HOST.

Alternatively, fig. 3 shows an operation timing diagram of a read operation signal provided by an embodiment of the present application, as shown in fig. 3, there are only DATA signal transmissions of 8 consecutive cycles from DEVICE to HOST, there is no CTRL signal transmission in this direction, and the read valid signal rdvalid ═ 1 indicates that DATA is read by DEVICE to HOST.

It should be noted that, the cross-time domain basic requirement may include: the signal period remains unchanged before and after CDC, the WRITE command and transmitted DATA signal remain aligned before and after CDC, and the DATA for the WRITE and READ processes are controlled by the odt and rdvalid signals, respectively.

The signal across the clock domain from HOST to DEVICE may include: ddr4_ cke, ddr4_ cs _ n, ddr4_ act _ n, ddr4_ adr [16:0], ddr4_ bg [2:0], ddr4_ c [2:0], ddr4_ ba [1:0], ddr4_ odt, ddr4_ dq [7:0], ddr4_ dm _ n, and ddr4_ dqs.

The signals across clock domains from DEVICE to HOST may include: ddr4_ dq [7:0], ddr4_ dm _ n, ddr4_ dqs, and rd _ valid.

Optionally, the asynchronous FIFO control signal transmission unit in the present application is also an asynchronous FIFO (First in First out queue). The asynchronous FIFO is a first-in first-out circuit and can store and buffer data of two different clock domains for resynchronization, the asynchronous FIFO is two completely independent clock domains, namely a writing clock domain and a reading clock domain, a clock signal of the writing clock domain is wclk, and an asynchronous reset signal is reset _ n. The winc signal is an enable signal that controls whether wdata is written into the FIFO.

When the FIFO is full, the wfull signal will be pulled high active until the data in the FIFO is read from the read clock domain so that the FIFO is not empty, at which point wfull will not be pulled low again. The signal definition of the read clock domain is similar to that of the write clock domain. If the repty signal is pulled high, it indicates that the data in the FIFO is completely empty, and until the write clock field writes the data into the FIFO again, the repty signal is pulled low again. The awfull and area signals in the asynchronous FIFO are used to characterize that at this time the poems in the FIFO will be filled or emptied by only one size difference, and the awfull and area signals are also high active outputs.

When HOST issues a write operation (ddr4adr is 10000), referring to fig. 2, HOST sends a write control signal of one cycle to DEVICE, and at this time, 8 cycles of write data signals are sent synchronously with it, and the write control signal and the write data signals can be processed from the low frequency domain to the high frequency domain across the clock domain, and then they are synchronously aligned.

Optionally, the asynchronous fifo control signal transmission unit is configured to, when receiving the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, write the write control signal into the asynchronous fifo control signal transmission unit according to a preset first transmission depth value when detecting that the asynchronous fifo control signal transmission unit is in a preset normal state;

In particular, the CTRL (control) signal has a certain persistence, rather than a burst transmission like the DATA signal, and thus, by setting the appropriate FIFO depth, setting the winc signal to 1 when it is detected that the FIFO is not full and not in the NOP state, allows wdata to be written to the FIFO from the write clock domain. The rinc signal is set to 1 as long as the FIFO is detected to be not empty, and the rinc signal can only keep one cycle valid, so that the real-time processing of the CTRL signal across clock domains can be realized. That is, as long as a non-NOP instruction of a cycle is written in the FIFO, the instruction in the FIFO is read out, and the read instruction also keeps one cycle active, because the clock frequency changes before and after clock domain crossing, in order to ensure that rin is active for only one cycle, on the basis of setting rin to 1 when detecting that the FIFO is not empty, a level pulse conversion (rising edge detection) circuit can be added to control rin to be active for only one cycle.

Optionally, the data signal transmission unit is configured to, when the write data signal sent by the host-side low-frequency clock domain module is received, determine, according to a preset second depth value, to transmit a corresponding write data transmission signal each time, store the write data transmission signal in the corresponding memory module until the number of transmission times reaches the second depth value, and sequentially read all the write data transmission signals from the data transmission unit according to a sequence of storage and writing.

In the present application, the data transmission unit may be QUEUE.

Specifically, when odt is 1, DATA is transmitted from HOST to DEVICE, and the DATA signal is characterized by burstiness, DATA transmission is only carried out when HOST sends a specific WRITE command, and the transmission length of each burst is fixed to 8. Using FIFO as QUEUE, firstly setting the depth of FIFO as burst length, which can be a definite value of 8, that is, the second transmission depth value can be 8, storing 8 units of DATA in FIFO every burst transmission stably, after 8 units of DATA are all entered into QUEUE, the QUEUE is marked as full (full is 1), and then reading DATA from QUEUE according to the sequence written from the write clock domain.

After CDC transmission of the CTRL signal and the DATA signal is finished respectively, the WRITE command of specific 1 cycle and the DATA signal of specific 8 cycles are coupled to achieve cooperative transmission of the CTRL signal and the DATA signal, and the DATA signal has certain delay characteristics due to certain delay caused by temporary storage of the DATA signal in the QUEUE, so that the DATA signal cannot be transmitted in the same period as each WRITE command in advance, and based on the delay, the WRITE command can be transmitted in the same period as the DATA signal. Since reading of the DATA signal is conditioned on rinc being 1, the CTRL and DATA signals can be synchronized under the condition that rinc being 1 is read as the CTRL signal, and the clock domain crossing processing from HOST to DEVICE is completed.

In this application, the high frequency to low frequency transmission sub-module may include a QUEUE, and when a read operation occurs, the cross-clock domain processing is performed from a DEVICE high frequency domain to a HOST low frequency domain, the DEVICE end has a certain burstiness for DATA transmission to the HOST end, and when the DEVICE transmits 8 cycles of DATA to the HOST continuously in bursts, the FIFO is used as a QUEUE function, all DATA is all temporarily stored in the QUEUE, and then the DATA in the QUEUE is sequentially read from the DEVICE end. Because the clock frequency of the DEVICE is higher than that of the HOST, the writing speed of the QUEUE is the first speed of reading, so that the next DATA writing needs to be performed after the DATA in the last QUEUE is completely read, the interval between the 8 units of DATA of two burst reading operations cannot be too small, the DATA loss caused by the fact that the DATA written next time is arrived and the clock domain crossing processing from the DEVICE to the HOST can be avoided.

The circuit for efficiently realizing the cross-clock domain of the pseudo DDR signal has good configurability, can simultaneously process scenes with high timing sequence requirements such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals, has wide application scenes, can be applied to propagation of a large number of signals from a low frequency domain to a high frequency domain or an opposite reverse bidirectional cross-clock domain, avoids multi-domain propagation of a metastable state, and improves the stability and reliability of a system.

Fig. 4 shows a schematic diagram of waveforms before and after a clock domain crossing from a HOST-side low-frequency clock domain module to a chip-side high-frequency clock domain module, according to an embodiment of the present invention, in a mode that a HOST crosses a clock domain to a DEVICE, after CDC transmission of a CTRL signal and a DATA signal is completed, a CTRL signal and a DATA signal are transmitted cooperatively, where a DATA signal is temporarily stored in a QUEUE, which may cause a certain delay, and therefore has a certain delay characteristic, so that the DATA signal may not be transmitted earlier in the same period as each WRITE command, and based on this, the WRITE command may be delayed in the same period as the DATA before transmission. Since reading of the DATA signal is conditioned on rinc being 1, the CTRL and DATA signals can be synchronized under the condition that rinc being 1 is read as the CTRL signal, and the clock domain crossing processing from HOST to DEVICE is completed.

Fig. 5 shows waveforms before and after crossing a clock domain from a chip-side high-frequency clock domain module to a HOST-side low-frequency clock domain module according to an embodiment of the present application, in a DEVICE-to-HOST cross-clock domain mode, when a read operation occurs, the DEVICE-side cross-clock domain processing is performed from a DEVICE high-frequency domain to a HOST low-frequency domain, DATA transmission from the DEVICE side to the HOST side has certain burstiness, when the DEVICE transmits DATA of 8 cycles to the HOST continuously, the FIFO is used as a QUEUE function, all DATA are all temporarily stored in the QUEUE, and then the DATA in the QUEUE are sequentially read from the DEVICE side. Because the clock frequency of the DEVICE is higher than that of the HOST, the writing speed of the QUEUE is the first time with the reading speed, so that the next DATA writing is required after all DATA in the last QUEUE is read, the interval between the 8 units of DATA of two burst reading operations cannot be too small, namely, before the next written DATA comes, the currently written DATA is ensured to be read.

In the circuit for efficiently implementing clock domain crossing of a pseudo DDR signal provided in the embodiment of the present invention, the low-frequency to high-frequency transmission sub-module is configured to, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module; the high-frequency-to-low-frequency transmission sub-module is used for completing reading of corresponding data based on the read data signals when the read data signals corresponding to the read operation instructions sent by the host end low-frequency clock domain module are received, and can simultaneously process high-timing sequence requirements such as synchronous cross-clock domain transmission between single-cycle and multi-cycle signals.

Fig. 6 shows a schematic flowchart of a method for efficiently implementing clock domain crossing of a pseudo DDR signal, which is provided by an embodiment of the present application, and is applied to the circuit for efficiently implementing clock domain crossing of a pseudo DDR signal shown in fig. 1, as shown in fig. 6, the method for efficiently implementing clock domain crossing of a pseudo DDR signal includes:

step 201: under the condition that a low-frequency to high-frequency transmission sub-module receives a write control signal and a write data signal corresponding to a write operation instruction sent by a low-frequency clock domain module of a host end, the low-frequency to high-frequency transmission sub-module respectively adjusts the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, performs synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sends the write control signal and the write data signal subjected to synchronous alignment processing to a high-frequency clock domain module of a chip end.

Optionally, a specific implementation manner of step 201 may include the following sub-steps:

substep S1: the asynchronous first-in first-out control signal transmission unit adjusts the write control signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write control signal corresponding to the write operation instruction sent by the host-end low-frequency clock domain module;

optionally, the asynchronous fifo control signal transmission unit writes the write control signal into the asynchronous fifo control signal transmission unit when detecting that the asynchronous fifo control signal transmission unit is in a preset normal state according to a preset first transmission depth value, under the condition that the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module is received;

Sub-step S2: the data signal transmission unit adjusts the write data signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write data signal corresponding to the write operation instruction sent by the host end low-frequency clock domain module;

Substep S3: the asynchronous first-in first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal which are subjected to synchronous alignment processing to the chip end high-frequency clock domain module.

Step 202: and the high-frequency to low-frequency transmission sub-module finishes reading corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction sent by the host end low-frequency clock domain module.

In the method for efficiently realizing clock domain crossing of the pseudo DDR signal provided by the embodiment of the present invention, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by a host end low-frequency clock domain module, a low-frequency to high-frequency transmission sub-module adjusts the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain respectively, performs synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sends the write control signal and the write data signal after the synchronous alignment processing to the chip end high-frequency clock domain module; under the condition that the high-frequency-to-low-frequency transmission sub-module receives a read data signal corresponding to a read operation instruction sent by the host-end low-frequency clock domain module, reading of corresponding data is completed based on the read data signal, and high-timing-sequence-requirement scenes such as synchronous cross-clock-domain propagation between single-cycle and multi-cycle signals can be processed simultaneously.

The method for efficiently realizing the clock domain crossing of the pseudo DDR signal is applied to a circuit for efficiently realizing the clock domain crossing of the pseudo DDR signal as shown in FIG. 1, and is not repeated herein for avoiding repetition.

The electronic device in the embodiment of the present invention may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiment of the present invention is not particularly limited.

The electronic device in the embodiment of the present invention may be an apparatus having an operating system. The operating system may be an Android (Android) operating system, an IOS operating system, or other possible operating systems, and embodiments of the present invention are not limited in particular.

Fig. 7 shows a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 7, the electronic device 300 includes a processor 310.

As shown in fig. 7, the processor 310 may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention.

As shown in fig. 7, the electronic device 300 may further include a communication line 340. Communication link 340 may include a path to transfer information between the aforementioned components.

Optionally, as shown in fig. 7, the electronic device may further include a communication interface 320. The communication interface 320 may be one or more. The communication interface 320 may use any transceiver or the like for communicating with other devices or communication networks.

Optionally, as shown in fig. 7, the electronic device may further include a memory 330. The memory 330 is used to store computer-executable instructions for performing aspects of the present invention and is controlled for execution by the processor. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

As shown in fig. 7, the memory 330 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 330 may be separate and coupled to the processor 310 via a communication line 340. The memory 330 may also be integrated with the processor 310.

Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In particular implementations, as one embodiment, processor 310 may include one or more CPUs, such as CPU0 and CPU1 in fig. 7, as shown in fig. 7.

In a specific implementation, as an embodiment, as shown in fig. 7, the terminal device may include a plurality of processors, such as the first processor 3101 and the second processor 3102 in fig. 7. Each of these processors may be a single-core processor or a multi-core processor.

Fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 8, the chip 400 includes one or more than two (including two) processors 310.

Optionally, as shown in fig. 8, the chip further includes a communication interface 320 and a memory 330, and the memory 330 may include a read-only memory and a random access memory and provide operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 8, memory 330 stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present invention, as shown in fig. 8, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.

As shown in fig. 8, the processor 310 controls the processing operation of any one of the terminal devices, and the processor 310 may also be referred to as a Central Processing Unit (CPU).

As shown in fig. 8, memory 330 may include both read-only memory and random access memory and provides instructions and data to the processor. A portion of the memory 330 may also include NVRAM. For example, in applications where the memory, communication interface, and memory are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 450 in fig. 8.

As shown in fig. 8, the method disclosed in the above embodiments of the present invention may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, the instructions implement the functions performed by the terminal device in the above embodiments.

In one aspect, a chip is provided, where the chip is applied in a terminal device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the circuit that efficiently implements the clock domain crossing of the pseudo DDR signal in the above embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, hard disk, magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present invention has been described in connection with the specific features and embodiments thereof, it is apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A circuit for efficiently implementing a clock domain crossing of a pseudo DDR signal, the circuit comprising:

2. The circuit for efficiently implementing clock domain crossing of pseudo DDR signals according to claim 1, wherein the low frequency to high frequency transmission sub-module comprises an asynchronous first in first out control signal transmission unit and a data signal transmission unit, one end of the asynchronous first in first out control signal transmission unit is connected with the chip end high frequency clock domain module, the other end of the asynchronous first in first out control signal transmission unit is connected with the host end low frequency clock domain module, one end of the data signal transmission unit is connected with the chip end high frequency clock domain module, and the other end of the data signal transmission unit is connected with the host end low frequency clock domain module;

the low-frequency to high-frequency transmission sub-module is configured to, when receiving a write control signal and a write data signal corresponding to a write operation instruction sent by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and write data signal, and send the write control signal and the write data signal after synchronous alignment processing to the chip-side high-frequency clock domain module, and includes:

the asynchronous first-in first-out control signal transmission unit and the data signal transmission unit are further configured to perform synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and send the write control signal and the write data signal that are subjected to the synchronous alignment processing to the chip-side high-frequency clock domain module.

3. The circuit for efficiently implementing the clock domain crossing of the pseudo DDR signal as claimed in claim 2, wherein the circuit further comprises a plurality of memory modules, the memory modules are disposed on the chip-side high frequency clock domain module, and the plurality of memory modules are respectively connected with each clock domain crossing module in a one-to-one correspondence.

4. The circuit for efficiently implementing clock domain crossing of pseudo DDR signals as claimed in claim 3, wherein said asynchronous FIFO control signal transmission unit is configured to, upon receiving a write control signal corresponding to said write operation command sent by said host side low frequency clock domain module, adjust said write control signal from a low frequency clock domain to a high frequency clock domain, comprising:

5. The circuit for efficiently implementing clock domain crossing of pseudo DDR signals as claimed in claim 4, wherein the data signal transmission unit is configured to, in case of receiving a write data signal corresponding to the write operation instruction issued by the host side low frequency clock domain module, adjust the write data signal from a low frequency clock domain to a high frequency clock domain, and comprises:

6. A method for efficiently realizing clock domain crossing of a pseudo DDR signal, which is applied to the circuit for efficiently realizing clock domain crossing of a pseudo DDR signal, as claimed in any one of claims 1 to 5, the method comprising:

under the condition that a low-frequency to high-frequency transmission sub-module receives a write control signal and a write data signal corresponding to a write operation instruction sent by a host end low-frequency clock domain module, adjusting the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain respectively, performing synchronous alignment processing on the adjusted write control signal and the adjusted write data signal, and sending the write control signal and the write data signal subjected to synchronous alignment processing to a chip end high-frequency clock domain module;

and the high-frequency to low-frequency transmission sub-module finishes reading corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation command sent by the host end low-frequency clock domain module.

7. The method according to claim 6, wherein the low-frequency to high-frequency transmission sub-module comprises an asynchronous first-in first-out control signal transmission unit and a data signal transmission unit, and when receiving a write control signal and a write data signal corresponding to a write operation command sent by the host-side low-frequency clock domain module, the low-frequency to high-frequency transmission sub-module adjusts the write control signal and the write data signal from a low-frequency clock domain to a high-frequency clock domain, performs synchronous alignment on the adjusted write control signal and the adjusted write data signal, and sends the write control signal and the write data signal after the synchronous alignment to the chip-side high-frequency clock domain module, including:

the asynchronous first-in first-out control signal transmission unit adjusts the write control signal from a low-frequency clock domain to a high-frequency clock domain under the condition of receiving the write control signal corresponding to the write operation instruction sent by the host-end low-frequency clock domain module;

8. The method according to claim 7, wherein the adjusting the write control signal from the low frequency clock domain to the high frequency clock domain by the asynchronous fifo control signal transmission unit when receiving the write control signal corresponding to the write operation command sent by the host-side low frequency clock domain module includes:

9. The method for efficiently implementing clock domain crossing of pseudo DDR signals as claimed in claim 8, wherein the data signal transmission unit adjusts the write data signal from a low frequency clock domain to a high frequency clock domain upon receiving a write data signal corresponding to the write operation command issued by the host side low frequency clock domain module, comprising:

10. An electronic device, comprising: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause performance of the method for efficiently implementing the clock domain crossing of a pseudo DDR signal of any of claims 6-9.