CN115016586A - Low dropout regulator and control system thereof - Google Patents
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Abstract
The application discloses low dropout regulator and control system, low dropout regulator include error amplification branch road, first current branch road and resistance branch road. The error amplification branch circuit is connected with the first current branch circuit, the first reference voltage and the resistance branch circuit, and the first current branch circuit is connected with the first power supply. The error amplification branch circuit obtains a sampling voltage based on the voltage of the first connection point, and amplifies a difference value between the sampling voltage and a first reference voltage to output a first voltage signal. The first current branch outputs a first current in response to a first voltage signal. The resistance branch circuit responds to a first current to generate a first voltage on the resistance branch circuit, the first voltage acts on the first connecting point to introduce a zero point for compensating a first pole, and the frequency of the first pole is determined by an equivalent output resistor at the first end of the error amplification branch circuit and an equivalent capacitor at the first end of the first current branch circuit. By the method, the stability of the circuit in the low dropout linear regulator can be improved.
Description
Technical Field
The present disclosure relates to electronic circuits, and particularly to a low dropout regulator and a control system.
Background
In power supply, a Low Dropout Regulator (LDO) is widely used in different output voltage domains due to the advantages of less peripheral component requirements, Low output noise, small output ripple, simple circuit structure, and the like.
In a circuit of a low dropout linear regulator, at least two poles are often included. One at the output of the error amplifier with a relatively fixed pole frequency and the other at the output of the low dropout regulator with a frequency that varies with load variations. This pole with frequency varying with load, combined with another pole with relatively fixed frequency, can cause the stability of the circuit in the low dropout linear regulator to change. Therefore, in order to ensure the stability of the loop in the circuit of the low dropout regulator under different load conditions, the stability compensation of the circuit of the low dropout regulator is required. At present, the compensation method is usually realized by adopting a load current sampling technology.
However, due to the change of temperature, process parameters, peripheral components and mismatch in the production process, the pole frequency of the loop may change greatly, and it is difficult to ensure that the dynamic zero and the output pole are completely matched in the full load range, which also results in that the implementation of the loop compensation by the load current sampling technique is difficult and there is a risk of instability.
Disclosure of Invention
The application aims to provide a low dropout regulator and a control system, which can improve the stability of a circuit in the low dropout regulator.
To achieve the above object, in a first aspect, the present application provides a low dropout linear regulator, comprising:
the error amplifying branch circuit, the first current branch circuit and the resistance branch circuit;
the first end of the error amplification branch circuit is connected with the first end of the first current branch circuit, the second end of the first current branch circuit is connected with a first power supply, the second end of the error amplification branch circuit is connected with a first reference voltage, the third end of the error amplification branch circuit is respectively connected with the third end of the first current branch circuit and the first end of the resistance branch circuit, the second end of the resistance branch circuit is an output end, and a connection point among the third end of the error amplification branch circuit, the third end of the first current branch circuit and the first end of the resistance branch circuit is a first connection point, and the output end is used for being connected with a load;
the error amplification branch is configured to obtain a sampling voltage based on the voltage of the first connection point and amplify a difference value between the sampling voltage and the first reference voltage to output a first voltage signal;
the first current branch is configured to output a first current at a third terminal of the first current branch in response to the first voltage signal;
the resistance branch is configured to generate a first voltage on the resistance branch in response to the first current, wherein the first voltage is applied to the first connection point to introduce a zero for compensating a first pole, and a frequency of the first pole is determined by an equivalent output resistance of the first end of the error amplification branch and an equivalent capacitance of the first end of the first current branch.
In an optional mode, the error amplification branch comprises an operational amplifier and a voltage division unit;
the output end of the operational amplifier is connected with the first end of the first current branch, the input power end of the operational amplifier is connected with a second power supply, the first input end of the operational amplifier is connected with the first end of the voltage division unit, the second input end of the operational amplifier is connected with the first reference voltage, the grounding end of the operational amplifier and the second end of the voltage division unit are both grounded, and the third end of the voltage division unit is connected with the first connection point;
the voltage division unit is used for dividing the voltage of the first connecting point and outputting the sampling voltage to a first input end of the operational amplifier;
the output end of the operational amplifier is a first end of the error amplification branch, the second input end of the operational amplifier is a second end of the error amplification branch, and the third end of the voltage division unit is a third end of the error amplification branch.
In an optional manner, the voltage dividing unit includes a first resistor and a second resistor;
the first end of the first resistor is connected with the first connecting point, the second end of the first resistor is respectively connected with the first input end of the operational amplifier and the first end of the second resistor, and the second end of the second resistor is grounded;
the first end of the first resistor is the third end of the error amplification branch circuit.
In an alternative mode, the error amplifying branch further includes a driving unit;
the first end of the driving unit is connected with the first power supply, the second end of the driving unit is connected with the first end of the first current branch, the third end of the driving unit is connected with the output end of the operational amplifier, and the fourth end of the driving unit is grounded;
the driving unit is configured to output the first voltage signal in response to a second voltage signal output by the operational amplifier, wherein the driving capability of the first voltage signal is stronger than that of the second voltage signal;
and the second end of the driving unit is the first end of the error amplification branch.
In an alternative mode, the driving unit includes a current source and a third transistor;
the negative electrode of the current source is connected with the first power supply, the positive electrode of the current source is respectively connected with the second end of the third transistor and the first end of the first current branch, the first end of the third transistor is connected with the output end of the operational amplifier, and the third end of the third transistor is grounded.
In an alternative, the first current branch comprises a first transistor;
the first end of the first transistor is connected with the first end of the error amplification branch circuit, the second end of the first transistor is connected with the first power supply, and the third end of the first transistor is connected with the first connecting point.
In an alternative mode, the resistance branch comprises a third resistance;
the first end of the third resistor is connected to the first connection point, and the second end of the third resistor is the output end.
In an optional manner, the resistance value r1 of the resistor branch, the equivalent output resistor r2 at the first end of the error amplifying branch, and the equivalent capacitor c2 at the first end of the first current branch satisfy the following relationship:
r1＝r2*c2/cL；
wherein cL is an output capacitance in the load.
In an optional mode, the low dropout linear regulator further comprises a second current branch;
the first end of the second current branch is connected with the first end of the first current branch, the second end of the second current branch is connected with the first power supply, and the third end of the second current branch is connected with the output end;
the second current branch is configured to output a second current at a third terminal of the second current branch in response to the first voltage signal to generate a second voltage at the output terminal based on the first current and the second current, wherein a sum of the first voltage and the second voltage is applied to the first connection point to introduce a zero for compensating the first pole.
In an alternative mode, the second current branch includes a second transistor;
the first end of the second transistor is connected with the first end of the first current branch, the second end of the second transistor is connected with the first power supply, and the third end of the second transistor is connected with the output end.
In an optional mode, the transconductance of the second current branch is N times that of the first current branch, and N > 1;
the resistance value r3 of the resistance branch, the equivalent output resistance r2 of the first end of the error amplification branch and the equivalent capacitance c2 of the first end of the first current branch satisfy the following relations:
r3＝r2*c2*(N+1)/cL；
wherein cL is an output capacitance in the load.
In an optional mode, the low dropout linear regulator further comprises a current mirror branch;
the first end of the current mirror branch circuit is connected with the first end of the first current branch circuit, the second end of the current mirror branch circuit is connected with the first power supply, the third end of the current mirror branch circuit is connected with the first connecting point, and the fourth end of the current mirror branch circuit is grounded;
the current mirror branch is configured to generate a first direct current flowing out of the first connection point, and the first direct current is equal to the direct current flowing through the first current branch in magnitude, so that the direct current flowing through the resistance branch is zero.
In an optional mode, the current mirror branch comprises a fourth transistor, a fifth transistor and a sixth transistor;
the fourth transistor is respectively connected with the first current branch and the fifth transistor, and the fourth transistor is used for generating a second direct current flowing through the fifth transistor;
the sixth transistor is connected to the fifth transistor and the first connection point, respectively, and the sixth transistor is configured to generate the first direct current based on the second direct current.
In an optional manner, a first terminal of the fourth transistor is connected to the first terminal of the first current branch, a second terminal of the fourth transistor is connected to the first power supply, a third terminal of the fourth transistor and a third terminal of the fifth transistor are connected, a second terminal of the sixth transistor and a second terminal of the fifth transistor are both grounded, and a third terminal of the sixth transistor is connected to the first connection point;
the first end of the fourth transistor is the first end of the current mirror branch, the second end of the fourth transistor is the second end of the current mirror branch, the third end of the sixth transistor is the third end of the current mirror branch, and the second end of the sixth transistor is the fourth end of the current mirror branch.
In an optional mode, the low dropout linear regulator further comprises a filtering branch;
the first end of the filtering branch circuit is connected with the first end of the fifth transistor, the second end of the filtering branch circuit is connected with the first end of the sixth transistor, and the third end of the filtering branch circuit is grounded;
the filtering branch is configured to low-pass filter the alternating current signal in the current mirror branch to keep the current in the current mirror branch as a direct current.
In an optional mode, the filtering branch comprises a fourth resistor and a first capacitor;
a first end of the fourth transistor is connected with a first end of the first current branch, a second end of the fourth transistor is connected with the first power supply, a third end of the fourth transistor is respectively connected with a third end of the fifth transistor, a first end of the fourth resistor and a first end of the fifth transistor, a second end of the fourth resistor is respectively connected with a first end of the sixth transistor and a first end of the first capacitor, a second end of the sixth transistor, a second end of the fifth transistor and a second end of the first capacitor are all grounded, and a third end of the sixth transistor is connected with the first connection point;
the first end of the fourth transistor is the first end of the current mirror branch, the second end of the fourth transistor is the second end of the current mirror branch, the third end of the sixth transistor is the third end of the current mirror branch, and the second end of the sixth transistor is the fourth end of the current mirror branch.
In a second aspect, the present application provides a control system comprising:
a load and a low dropout linear regulator as described above;
the low dropout linear regulator is connected with the load and is used for providing voltage and current for the load
The beneficial effect of this application is: the application provides a low dropout regulator includes error amplification branch road, first current branch road and resistance branch road. The first end of the error amplification branch circuit is connected with the first end of the first current branch circuit, the second end of the first current branch circuit is connected with the first power supply, the second end of the error amplification branch circuit is connected with the first reference voltage, the third end of the error amplification branch circuit is respectively connected with the third end of the first current branch circuit and the first end of the resistance branch circuit, the second end of the resistance branch circuit is an output end, a connection point between the third end of the error amplification branch circuit, the third end of the first current branch circuit and the first end of the resistance branch circuit is a first connection point, and the output end is used for being connected with a load. The error amplification branch is configured to obtain a sampling voltage based on the voltage of the first connection point and amplify a difference between the sampling voltage and a first reference voltage to output a first voltage signal. The first current branch is configured to output a first current at a third terminal of the first current branch in response to a first voltage signal. The resistance branch is configured to generate a first voltage on the resistance branch in response to a first current, wherein the first voltage acts on the first connection point to introduce a zero for compensating the first pole, so that, in the above manner, a zero can be introduced to compensate the first pole existing in the low dropout linear regulator, and since the frequency of the first pole is determined by the equivalent output resistor at the first end of the error amplification branch and the equivalent capacitor at the first end of the first current branch, the first pole does not change along with load change, and relatively stable compensation can be realized, thereby improving the stability of the circuit in the low dropout linear regulator.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic circuit diagram of a prior art LDO;
fig. 2 is a schematic structural diagram of a low dropout regulator according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a low dropout linear regulator according to another embodiment of the present application;
fig. 5 is a schematic circuit diagram of a low dropout linear regulator according to another embodiment of the present application;
fig. 6 is a schematic circuit diagram of a low dropout linear regulator according to still another embodiment of the present application;
fig. 7 is a schematic circuit diagram of a low dropout linear regulator according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a circuit diagram of a Low Dropout Regulator (LDO) in the prior art. As shown in fig. 1, the circuit structure of the low dropout linear regulator substantially includes two poles.
Wherein, the first pole: the output resistance of the high impedance at the output of the error amplifier Ua and the parasitic gate capacitance of the power transistor PM1 will generate a first pole whose frequency is calculated as:
wherein C p1 Is the capacitance value of the gate parasitic capacitance, r, of the power transistor PM1 o1 Is the resistance value of the output resistor of the error amplifier Ua, f P1 The frequency of the first pole.
The second pole: at the output VOU of the low dropout regulatorThe output equivalent resistor RaL and the external filter capacitor CaL of T will generate a second pole whose frequency is calculated as:
wherein, C L Is the capacitance value, R, of the external filter capacitor CaL L Is the resistance value, f, of the equivalent output resistance RaL of the load p2 The frequency of the second pole.
It will be appreciated that in a circuit with a feedback loop, the capacitance at the circuit node can slow the analog signal frequency response. The pole reflects the change in output impedance, where below the pole frequency the output impedance is determined by the output impedance of the node, and above the pole frequency the output impedance is determined by the capacitance of the node.
Then, it can be seen from the above formula (i) and the formula (ii) that when the current of the load connected to the output terminal VOUT of the low dropout linear regulator is small (the resistance R of the equivalent output resistor RaL) L Larger), the dominant pole is at the output of the low dropout regulator, and the capacitance C of the external capacitor CaL is used to control the output voltage of the low dropout regulator L And resistance value R of equivalent output resistor RaL L And (6) determining. However, the larger the power transistor PM1, the larger the gate parasitic capacitance C thereof p1 The larger is f p1 The lower and the smaller the quiescent current, r o1 The larger, the same factor f p1 The more it becomes, f p1 And f p2 The closer together. Therefore, in order to stabilize the loop, the structure needs to introduce a compensation circuit for stability compensation. r is o1 ，C p1 The larger the compensation circuit is, the stronger the compensation circuit needs to be made, so that the loop bandwidth is narrowed and the dynamic response is slowed down. In practical applications, the compensation circuit can usually use Miller compensation to let f p1 And f p2 And separating to stabilize.
In addition, the dynamic response of the low dropout linear regulator is also dependent on the gate slew rate of the power transistor PM 1. The smaller the driving current of the power tube is, the larger the power tube is, the more difficult the grid voltage is to change so as to adjust the output current of the loop. The gate slew rate of the power transistor PM1 means that when the load current changes, the gate voltage of the power transistor PM1 also needs to change to adjust the output current of the low dropout regulator.
In summary, loop stability and dynamic response are limiting factors in directly depressing static power consumption. Furthermore, in the prior art, in order to maintain the loop stability and improve the dynamic response of the low dropout linear regulator with low static power consumption, a compensation circuit which can be dynamically adjusted along with the load change is generally required to be arranged. The specific implementation process is as follows: the control circuit senses the current of the power tube PM1, and then controls the compensation circuit to obtain a dynamic zero compensation output pole (i.e. the second pole), and the dynamic zero can track the change of the output pole, so as to achieve the stable operation of the low dropout linear regulator in the full load range. In addition, the driving capability of the output of the error amplifier can be controlled to change along with the load change through the induction current so as to increase the transient response of the low dropout linear regulator.
However, the above solution has the following disadvantages: the pole frequency of the loop can change significantly due to variations in temperature, process parameters, and peripheral components and mismatches during production. Therefore, it is difficult to ensure that the dynamic zero and the output pole are perfectly matched over the full load range. Thereby making the implementation of such a technique difficult for loop compensation.
Based on this, the present application provides a low dropout regulator, which is capable of introducing a zero point by adding a corresponding circuit structure, and compensating the first pole in the above formula (i) through the zero point. At this time, the compensated zero point and the compensated first pole do not change with the load current, and the compensation effect is better and more stable.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a low dropout regulator according to an embodiment of the present disclosure. As shown in fig. 2, the low dropout regulator 100 includes a first current branch 10, an error amplifying branch 20 and a resistor branch 30.
The first end of the error amplification branch 20 is connected to the first end of the first current branch 10, the second end of the first current branch 10 is connected to the first power source VC1, the second end of the error amplification branch 20 is connected to the first reference voltage Vref1, the third end of the error amplification branch 20 is connected to the third end of the first current branch 10 and the first end of the resistance branch 30, the second end of the resistance branch 30 is the output terminal VOUT, and the connection point between the third end of the error amplification branch 20, the third end of the first current branch 10 and the first end of the resistance branch 30 is the first connection point P1, and the output terminal VOUT is used for being connected to the load 200. The first reference voltage Vref1 can be set according to practical applications, and is not particularly limited in this embodiment of the present application.
Specifically, the error amplifying branch 20 is configured to obtain a sampled voltage based on the voltage of the first connection point P1, and amplify a difference between the sampled voltage and the first reference voltage Vref1 to output a first voltage signal. The first current branch 10 is configured to output a first current at a third terminal of the first current branch 10 in response to the first voltage signal. The resistance branch 30 is configured to generate a first voltage on the resistance branch 30 in response to the first current, wherein the first voltage is applied to the first connection point P1 to introduce a zero for compensating a first pole, and a frequency of the first pole is determined by an equivalent output resistance of the first end of the error amplifying branch 20 and an equivalent capacitance of the first end of the first current branch 10.
In this embodiment, by providing the resistor branch 30 between the first connection point P1 and the output terminal VOUT, a zero can be introduced, which is used to compensate for the first pole. Specifically, the frequency of the zero is near the frequency of the first pole, that is, the difference between the frequency of the zero and the frequency of the first pole is within a preset difference range, for example, the frequency of the zero is equal to the frequency of the first pole, so that the zero can compensate the first pole. It can be understood that the smaller the difference between the frequency of the zero and the frequency of the first pole, the better the compensation. The preset difference range may be set according to an actual application situation, and this is not specifically limited in the embodiments of the present application.
Meanwhile, it can be known from the above embodiments that in the related art, the output pole is compensated, that is, the pole corresponding to the formula (ii) in the above embodiments, when the output pole is related to the load current, it is likely to change due to the change of the load current, and the compensation process is difficult to implement and there is a risk of instability.
In the embodiment of the present application, the compensated first pole is determined only by the equivalent output resistance of the first end of the error amplifying branch 20 and the equivalent capacitance of the first end of the first current branch 10, and may correspond to the pole of the above formula (i), and the first pole does not change with the change of the load current, which is helpful for realizing stable compensation. In other words, the compensation applied to the first pole is effective regardless of the change of the load current, so that the improvement of the stability of the circuit in the low dropout linear regulator can be maintained.
In one embodiment, as shown in fig. 3, the error amplifying branch 20 includes an operational amplifier U1 and a voltage dividing unit 21.
An output end of the operational amplifier U1 is connected to a first end of the first current branch 10, an input power terminal of the operational amplifier U1 is connected to a second power source VC2, a first input end of the operational amplifier U1 is connected to a first end of the voltage dividing unit 21, a second input end of the operational amplifier U1 is connected to a first reference voltage Vref1, a ground terminal of the operational amplifier U1 and a second end of the voltage dividing unit 21 are both grounded GND, and a third end of the voltage dividing unit 21 is connected to a first connection point P1. The first power source VC1 and the second power source VC2 may be the same or different, and the embodiment of the present invention does not specifically limit the same.
In this embodiment, the voltage dividing unit 21 is configured to divide the voltage at the first connection point P1 and output the sampled voltage to the first input terminal of the operational amplifier U1. The output end of the operational amplifier U1 is the first end of the error amplification branch 20, the second input end of the operational amplifier U1 is the second end of the error amplification branch 20, and the third end of the voltage divider unit 21 is the third end of the error amplification branch 20. The first input terminal of the operational amplifier U1 may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal.
Fig. 3 also illustrates an example of a structure of the voltage dividing unit 21, and as shown in fig. 3, the voltage dividing unit 21 includes a first resistor R1 and a second resistor R2.
A first end of the first resistor R1 is connected to the first connection point P1, a second end of the first resistor R1 is connected to the first input end of the operational amplifier U1 and the first end of the second resistor R2, and a second end of the second resistor R2 is grounded. The first end of the first resistor R1 is the third end of the error amplifying branch 20.
Also illustrated in fig. 3 is one configuration of the first current branch 10, and as shown in fig. 3, the first current branch 10 includes a first transistor Q1.
A first terminal of the first transistor Q1 is connected to the first terminal of the error amplifying branch 20, a second terminal of the first transistor Q1 is connected to the first power source VC1, and a third terminal of the first transistor Q1 is connected to the first connection point P1.
It is understood that in this embodiment, the first transistor Q1 is taken as a PMOS transistor for example. The gate of the PMOS transistor is the first terminal of the first transistor Q1, the source of the PMOS transistor is the second terminal of the first transistor Q1, and the drain of the PMOS transistor is the third terminal of the first transistor Q1.
Also illustrated in fig. 3 is one configuration of the resistive branch 30, which includes a third resistor R3, as shown in fig. 3.
The first end of the third resistor R3 is connected to the first connection point P1, and the second end of the third resistor R3 is the output terminal VOUT.
Fig. 3 also illustrates an example of a structure of the load 200, as shown in fig. 3, the load 200 is connected between the output terminal VOUT and the ground, and the load 200 includes an output capacitor CL and an output resistor RL connected in parallel, where the output capacitor CL functions to filter the voltage of the output terminal VOUT, and the output resistor RL is an equivalent resistor of the load connected to the output terminal VOUT, and the resistance value of the output resistor RL varies with the load current.
The principle of the structure shown in fig. 3 will be explained below.
As shown in fig. 3, a fixed zero point can be added to compensate for the stability of the circuit of the low dropout regulator by connecting a third resistor R3 in series between the first connection point P1 and the output terminal VOUT.
Specifically, the operational amplifier U1 is controlled to output a first voltage signal to the first terminal of the first transistor Q1, and when the first transistor Q1 operates in the amplifying region, a current between the source and the drain of the first transistor Q1 is equivalent to a variable current source controlled by the first voltage signal, i.e., a current between the source and the drain of the first transistor Q1 varies with the variation of the first voltage signal. Since the resistance values of the first resistor R1 and the second resistor R2 can be set to be much larger than the resistance value of the third resistor R3, the first current can mainly flow through the branch where the third resistor R3 is located, the first current flows through the third resistor R3 to generate the first voltage, and the first current flows through the load 200 to generate the first load voltage. The voltage of the first connection point P1 is the sum of the first voltage and the first load voltage, and the voltage of the first connection point P1 is divided by the first resistor R1 and the second resistor R2 and then input to the non-inverting input terminal of the operational amplifier U1. Thus, the transfer function from the output of the op-amp U1 to its non-inverting input can be obtained as:
wherein, V + The voltage input to the non-inverting input terminal of the operational amplifier U1, Δ v is the first voltage signal output by the operational amplifier U1, gm1 is the transconductance of the first transistor Q1, cL is the capacitance value of the output capacitor cL in the load 200, R11 is the resistance value of the first resistor R1, R12 is the resistance value of the second resistor R2, and R1 is the resistance value of the third resistor R3 in the circuit shown in fig. 3.
As can be seen from the equation (1), the introduction of the third resistor R3 adds a zero point to the circuit, and by making the equation (1) zero, the frequency of the zero point can be obtained as
And the frequency of the first pole is
Where r2 is an equivalent output resistor (i.e. the output resistor of the operational amplifier U1 in fig. 3) at the first end of the error amplifying branch 20, and c2 is an equivalent capacitor at the first end of the first current branch 10. The zero point f can then be made by selection of circuit parameters z1 Is located exactly around the frequency of the first pole to realize a pair circuitStability compensation of (3).
For example, in some embodiments, to obtain the best compensation effect, the frequency of the zero is also set equal to the frequency of the first pole, i.e., f z1 ＝f p The following can be obtained: cL × r1 ═ c2 × r 2.
The compensation mode has the advantages that the circuit is simple and easy to realize, the pole frequency compensated by the introduced zero point is not changed along with the load current, and the compensation effect is good. Correspondingly, the resistance value of the third resistor required for completing the compensation mode
In one embodiment, as shown in fig. 4, the low dropout regulator 100 further comprises a second current branch 40.
The first end of the second current branch 40 is connected to the first end of the first current branch 10, the second end of the second current branch 40 is connected to the first power source VC1, and the third end of the second current branch 40 is connected to the output terminal VOUT.
Specifically, the second current branch 40 is configured to output a second current at a third terminal of the second current branch 40 in response to the first voltage signal, so as to generate a second voltage at the output terminal VOUT based on the first current and the second current, wherein a sum of the first voltage and the second voltage acts on the first connection point to introduce a zero for compensating the first pole. The second voltage is a total voltage generated by applying the sum of the first current and the second current to the load 200.
Also illustrated in fig. 4 is one configuration of second current branch 40, and as shown in fig. 4, second current branch 40 includes a second transistor Q2.
A first terminal of the second transistor Q2 is connected to the first terminal of the first current branch 10 (i.e., the first terminal of the first transistor Q1), a second terminal of the second transistor Q2 is connected to the first power source VC1, and a third terminal of the second transistor Q2 is connected to the output terminal VOUT.
It is understood that in this embodiment, the second transistor Q2 is a PMOS transistor for example. The gate of the PMOS transistor is the first terminal of the second transistor Q2, the source of the PMOS transistor is the second terminal of the second transistor Q2, and the drain of the PMOS transistor is the third terminal of the second transistor Q2.
In this embodiment, the second transistor Q2 also operates in the amplification region, and the source and the drain of the second transistor Q2 act as a variable current source controlled by the first voltage signal, i.e., a first current controlled by the first voltage signal can be generated in the first transistor Q1, and a second current controlled by the first voltage signal can be generated in the second transistor Q2. The first current flows through the third resistor to generate a first voltage, and then the first current flows into the load 200, and the first current and the second current generate a second voltage at the output terminal VOUT together. Then, the voltage of the first connection point P1 is the sum of the first voltage and the second voltage. At this time, the first voltage can be obtained as:
V R3 ＝gm1×Δv×r3 (2)
where R3 represents the resistance value of the third resistor R3 in the circuit shown in fig. 4.
The voltage across the load can be obtained, i.e. the second voltage is:
wherein gm1 is the transconductance of the first transistor Q1, and gm2 is the transconductance of the second transistor Q2.
The transfer function from the output of the op-amp U1 to its non-inverting input is:
the transfer function from the output of the operational amplifier U1 to its non-inverting input can be obtained by combining equations (2), (3) and (4):
for convenience of calculation, in an embodiment, the transconductance gm2 of the second current branch 40 may be set to be N times the transconductance gm1 of the first current branch 10, that is, the transconductance of the second transistor Q1 is N times that of the first transistor Q1, where N > 1. Equation (5) can be simplified as:
as can be seen from equation (6), by adding the second transistor Q2, the frequency of the zero point introduced can be made to be:
the first pole is still
Here, c2 is still the equivalent capacitance at the first end of the first current branch, however, in the circuit shown in fig. 4, since the first end of the first current branch is connected to the first end of the second current branch, c2 includes the sum of the parasitic capacitances of the first end of the first transistor Q1 and the first end of the second transistor Q2. When the total area of the first transistor Q1 and the second transistor Q2 in the circuit shown in fig. four is equal to the area of the first transistor Q1 in the circuit shown in fig. three, the corresponding capacitance c2 in the two circuits is also equal. Likewise, the zero point f can be made by selection of circuit parameters z2 Is located just around the frequency fp of the first pole to achieve stability compensation for the circuit.
In some embodiments, the zero is also set to have a frequency equal to the frequency of the first pole, i.e., f, for best compensation z2 ＝f p The following can be obtained: cL × r3 ═ c2 × r2 × (N + 1). That is, the new resistance value of the third resistor R3 required for completing the compensation of the same frequency is
The resistance value of the third resistor R3 shown in fig. 4 is increased by (N +1) times as compared with the resistance value of the third resistor R3 shown in fig. 3.
Meanwhile, it is understood that if the resistance value of the third resistor R3 shown in fig. 4 is set to the third resistor R3 shown in fig. 3N +1 times the resistance value of resistor R3, zero point f z1 And zero point f z2 The same frequency, the same compensation function can be realized. In this case, that is, under the condition of keeping the zero-point introduction frequency unchanged, compared with the result shown in fig. 3, although the resistance value of the third resistor R3 is increased by N +1 times, the current flowing through the third resistor R3 is decreased by N +1 times, since the resistance area is proportional to the square of the current, in practical applications, when a chip is implemented, the chip area occupied by the third resistor R3 shown in fig. 4 is instead one of N +1 times of the chip area occupied by the third resistor R3 shown in fig. 3, and the area of the third resistor R3 is significantly decreased, that is, the area occupied by the third resistor R3 in the low dropout linear regulator can be decreased, which is beneficial to reducing the cost of the low dropout linear regulator chip.
In an embodiment, a driving unit may be further disposed in the error amplifying branch 20 to increase the driving capability of the error amplifying branch 20, thereby increasing the response speed of the whole system.
As shown in fig. 5, the error amplifying branch 20 further comprises a driving unit 22.
A first terminal of the driving unit 22 is connected to the first power source VC1, a second terminal of the driving unit 22 is connected to the first terminal of the first current branch 10 (i.e., the first terminal of the first transistor Q1), a third terminal of the driving unit 22 is connected to the output terminal of the operational amplifier U1, and a fourth terminal of the driving unit 22 is grounded GND.
Specifically, the driving unit 22 is configured to output a first voltage signal in response to a second voltage signal output by the operational amplifier U1, wherein the driving capability of the first voltage signal is stronger than the second voltage signal. Wherein the second end of the driving unit 22 is the first end of the error amplifying branch 20.
In this embodiment, by providing the driving unit 22, the currents input to the first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 can be increased on the basis of outputting the corresponding first voltage signal according to the second voltage signal, so that the first transistor Q1 and the second transistor Q2 can be driven faster to perform corresponding operations.
Fig. 5 also illustrates a structure of the driving unit 22, and as shown in fig. 5, the driving unit 22 includes a current source I1 and a third transistor Q3.
The negative electrode of the current source I1 is connected to the first power source VC1, the positive electrode of the current source I1 is connected to the second end of the third transistor Q3 and the first end of the first current branch 10, the first end of the third transistor Q3 is connected to the output terminal of the operational amplifier U1, and the third end of the third transistor Q3 is grounded to GND.
It is understood that in this embodiment, the third transistor Q3 is a PMOS transistor for example. The gate of the PMOS transistor is the first terminal of the third transistor Q3, the source of the PMOS transistor is the second terminal of the third transistor Q3, and the drain of the PMOS transistor is the third terminal of the third transistor Q3.
In this embodiment, the third transistor Q3 also operates in the amplification region, the source and the drain of the third transistor Q3 is equivalent to a variable current source controlled by the second voltage signal, and the magnitude relationship between the current flowing through the third transistor Q3 and the current provided by the current source I1 determines the voltage at the drain of the third transistor Q3, i.e., the first voltage signal is controlled by the second voltage signal. The current source I1 can provide a stable current to increase the driving capability, thereby increasing the response speed of the first transistor Q1 and the second transistor Q2.
It should be noted that the driving unit 22 shown in fig. 5 can be applied to the structure shown in fig. 3, and can also achieve the effect of increasing the driving capability, and of course, can also be applied to other embodiments of the present application. In other words, any combination of the technical features in the different embodiments of the present application is possible.
In one embodiment, as shown in fig. 6, the low dropout linear regulator 100 further comprises a current mirror branch 50.
The first end of the current mirror branch 50 is connected to the first end of the first current branch 10 (i.e., the first end of the first transistor Q1), the second end of the current mirror branch 50 is connected to the first power source VC1, the third end of the current mirror branch 50 is connected to the first connection point P1, and the fourth end of the current mirror branch 50 is grounded GND.
Specifically, the current mirror branch 50 is configured to generate a first dc current flowing out of the first connection point P1, and the first dc current is equal to the dc current flowing through the first current branch 10, so that the dc current flowing through the resistance branch 30 is zero.
In one embodiment, with reference to fig. 6, the current mirror branch 50 includes a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6.
The fourth transistor Q4 is connected to the first current branch 10 and the fifth transistor Q5, respectively, and the sixth transistor Q6 is connected to the fifth transistor Q5 and the first connection point P1, respectively.
Specifically, a first terminal of the fourth transistor Q4 is connected to the first terminal of the first current branch 10, a second terminal of the fourth transistor Q4 is connected to the first power source VC1, a third terminal of the fourth transistor Q4 is connected to a third terminal of the fifth transistor Q5, a first terminal of the fifth transistor Q5, and a first terminal of the sixth transistor Q6, a second terminal of the sixth transistor Q6 and a second terminal of the fifth transistor Q5 are both grounded, and a third terminal of the sixth transistor Q6 is connected to the first connection point P1.
The first terminal of the fourth transistor Q4 is the first terminal of the current mirror branch 50, the second terminal of the fourth transistor Q4 is the second terminal of the current mirror branch 50, the third terminal of the sixth transistor Q6 is the third terminal of the current mirror branch 50, and the second terminal of the sixth transistor Q6 is the fourth terminal of the current mirror branch 50.
In this embodiment, the first terminal of the fourth transistor Q4 is connected to the first terminal of the first transistor Q1, and the second terminal of the fourth transistor Q4 and the second terminal of the first transistor Q1 are both connected to the first power source VC1, so that the current flowing through the fourth transistor Q4 (i.e., the second dc current) is equal to the dc current flowing through the first transistor Q1 by configuring the fourth transistor Q4 and the first transistor Q1 to be equal in size. In other words, the direct current flowing through the first transistor Q1 is divided by 1: 1 is mirrored to the fourth transistor Q4, i.e. the second dc current is equal to the dc current flowing through the first current branch 10.
Since the second dc current flows through the fifth transistor Q5, and the first terminal of the sixth transistor Q6 is connected to the first terminal of the fifth transistor Q5, and the second terminal of the sixth transistor Q6 is connected to the second terminal of the fifth transistor Q5, the current flowing through the sixth transistor Q6 (i.e., the second dc current) is equal to the dc current flowing through the fifth transistor Q5 by arranging the fifth transistor Q5 and the sixth transistor Q6 to have the same size. In other words, the dc current flowing through the fifth transistor Q5 is further controlled by 1: 1 is mirrored to the sixth transistor Q1, i.e., the sixth transistor Q6 generates the first dc current based on the second dc current, and the first dc current and the second dc current are equal and equal to the dc current flowing through the first transistor Q1.
Alternatively, the first direct current may be equal to the direct current flowing through the first transistor Q1 by a method of keeping the size ratio M1 of the second transistor Q2 to the fourth transistor Q4 and the size ratio M2 of the sixth transistor Q6 to the fifth transistor Q5 equal (i.e., M1-M2-M). In this case the ratio of the second direct current to the first direct current is M.
Meanwhile, the first dc current flows from the first connection point P1, and the first dc current is equal to the dc current flowing through the first transistor Q1, so that the current flowing through the first transistor Q1 flows into the branch of the sixth transistor Q6 as the first dc current once flowing into the first connection point P1. In this case, no dc current is present across the third resistor R3, i.e., no dc voltage drop is present. Further, the output terminal VOUT and the first connection point P1 are equivalent to a dc short circuit. It can be understood that in the embodiments shown in fig. 3-5, the third resistor R3 is introduced to cause the output voltage not to be equal to the voltage at the first connection point P1, which may cause an error in the voltage output by the low dropout regulator when the output current varies, and by providing a dc short circuit between the output terminal VOUT and the first connection point P1, the problem of the error in the output voltage caused by the third resistor R3 is solved skillfully, which is beneficial to keep the low dropout regulator 100 outputting a stable voltage.
In one embodiment, as shown in fig. 7, the low dropout regulator 100 further comprises a filtering branch 60.
The first end of the filtering branch 60 is connected to the first end of the fifth transistor Q5, the second end of the filtering branch 60 is connected to the first end of the sixth transistor Q6, and the third end of the filtering branch 60 is grounded GND.
Specifically, the filtering branch 60 is configured to perform low-pass filtering on the ac signal in the current mirror branch 50 to keep the current in the current mirror branch 50 as a dc current, so as to prevent the influence on the added zero due to the addition of the current mirror branch 50, which is beneficial to maintaining the stability of compensating the first pole.
Fig. 7 also illustrates an example of a structure of the filter branch 60, and as shown in fig. 7, the filter branch 60 includes a fourth resistor R4 and a first capacitor C1.
A first end of the fourth transistor Q4 is connected to the first end of the first current branch 10, a second end of the fourth transistor Q4 is connected to the first power source VC1, a third end of the fourth transistor Q4 is connected to a third end of the fifth transistor Q5, a first end of the fourth resistor R4, and a first end of the fifth transistor Q5, a second end of the fourth resistor R4 is connected to a first end of the sixth transistor Q6 and a first end of the first capacitor C1, a second end of the sixth transistor Q6, a second end of the fifth transistor Q5, and a second end of the first capacitor C1 are all grounded, and a third end of the sixth transistor Q6 is connected to the first connection point P1.
The first terminal of the fourth transistor Q4 is the first terminal of the current mirror branch 50, the second terminal of the fourth transistor Q4 is the second terminal of the current mirror branch 50, the third terminal of the sixth transistor Q6 is the third terminal of the current mirror branch 50, and the second terminal of the sixth transistor Q6 is the fourth terminal of the current mirror branch 50.
In this embodiment, the filter branch 60 formed by the fourth resistor R4 and the first capacitor C1 is used to perform low-pass filtering on the ac signals applied to the first terminal of the fifth transistor Q5 and the first terminal of the sixth transistor Q6, so that the whole current mirror branch 60 does not participate in the ac response of the circuit in the low dropout linear regulator. The fourth resistor R4 and the first capacitor C1 are appropriately selected such that only the dc component of the current flowing through the first transistor Q1 is shunted to the sixth transistor Q6, while the ac component of the current flowing through the first transistor Q1 still flows through the third resistor R3 to the output terminal VOUT and the load 200. In this way, the transfer function (such as equation (1) or equation (5)) of the original compensation circuit remains unchanged. The addition of the filtering branch 60 enables the current mirror branch 60 to completely maintain the compensation characteristic of the zero point brought by the third resistor R3 to the stability of the system while eliminating the output voltage error of the circuit in the original low dropout linear regulator.
It should be noted that, in this embodiment, although the connection relationship among the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 is different from the structure described in fig. 6, the functions and the specific implementation processes of the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are all the same as those of the structure shown in fig. 6, and specifically, the detailed description of fig. 6 may be referred to, and are not repeated herein.
The embodiment of the present application further provides a control system, which includes a load and the low dropout regulator as in any of the above embodiments, where the low dropout regulator is connected to the load, and the low dropout regulator is configured to provide voltage and current for the load.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; within the context of the present application, where technical features in the above embodiments or in different embodiments can also be combined, the steps can be implemented in any order and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (17)
1. A low dropout linear regulator, comprising:
the error amplifying branch circuit, the first current branch circuit and the resistance branch circuit;
the first end of the error amplification branch circuit is connected with the first end of the first current branch circuit, the second end of the first current branch circuit is connected with a first power supply, the second end of the error amplification branch circuit is connected with a first reference voltage, the third end of the error amplification branch circuit is respectively connected with the third end of the first current branch circuit and the first end of the resistance branch circuit, the second end of the resistance branch circuit is an output end, and a connection point among the third end of the error amplification branch circuit, the third end of the first current branch circuit and the first end of the resistance branch circuit is a first connection point, and the output end is used for being connected with a load;
the error amplification branch is configured to obtain a sampling voltage based on the voltage of the first connection point and amplify a difference between the sampling voltage and the first reference voltage to output a first voltage signal;
the first current branch is configured to output a first current at a third end of the first current branch in response to the first voltage signal;
the resistance branch is configured to generate a first voltage on the resistance branch in response to the first current, wherein the first voltage is applied to the first connection point to introduce a zero for compensating a first pole, and a frequency of the first pole is determined by an equivalent output resistance of the first end of the error amplification branch and an equivalent capacitance of the first end of the first current branch.
2. The low dropout regulator according to claim 1, wherein the error amplifying branch comprises an operational amplifier and a voltage dividing unit;
the output end of the operational amplifier is connected with the first end of the first current branch, the input power end of the operational amplifier is connected with a second power supply, the first input end of the operational amplifier is connected with the first end of the voltage division unit, the second input end of the operational amplifier is connected with the first reference voltage, the grounding end of the operational amplifier and the second end of the voltage division unit are both grounded, and the third end of the voltage division unit is connected with the first connection point;
the voltage division unit is used for dividing the voltage of the first connecting point and outputting the sampling voltage to a first input end of the operational amplifier;
the output end of the operational amplifier is a first end of the error amplification branch, the second input end of the operational amplifier is a second end of the error amplification branch, and the third end of the voltage division unit is a third end of the error amplification branch.
3. The low dropout regulator according to claim 2, wherein the voltage dividing unit comprises a first resistor and a second resistor;
the first end of the first resistor is connected with the first connecting point, the second end of the first resistor is respectively connected with the first input end of the operational amplifier and the first end of the second resistor, and the second end of the second resistor is grounded;
the first end of the first resistor is the third end of the error amplification branch circuit.
4. The low dropout regulator of claim 2 wherein the error amplification branch further comprises a drive unit;
the first end of the driving unit is connected with the first power supply, the second end of the driving unit is connected with the first end of the first current branch, the third end of the driving unit is connected with the output end of the operational amplifier, and the fourth end of the driving unit is grounded;
the driving unit is configured to output the first voltage signal in response to a second voltage signal output by the operational amplifier, wherein the driving capability of the first voltage signal is stronger than that of the second voltage signal;
and the second end of the driving unit is the first end of the error amplification branch.
5. The low dropout regulator according to claim 4, wherein the driving unit comprises a current source and a third transistor;
the negative electrode of the current source is connected with the first power supply, the positive electrode of the current source is respectively connected with the second end of the third transistor and the first end of the first current branch, the first end of the third transistor is connected with the output end of the operational amplifier, and the third end of the third transistor is grounded.
6. The low dropout linear regulator of claim 1 wherein the first current branch comprises a first transistor;
the first end of the first transistor is connected with the first end of the error amplification branch circuit, the second end of the first transistor is connected with the first power supply, and the third end of the first transistor is connected with the first connecting point.
7. The low dropout regulator of claim 1 wherein the resistive branch comprises a third resistor;
the first end of the third resistor is connected to the first connection point, and the second end of the third resistor is the output end.
8. The low dropout regulator according to any one of claims 1-7, wherein the resistance r1 of the resistance branch, the equivalent output resistance r2 of the first end of the error amplifying branch, and the equivalent capacitance c2 of the first end of the first current branch satisfy the following relationship:
r1＝r2*c2/cL；
wherein cL is an output capacitance in the load.
9. The LDO of claim 1, further comprising a second current branch;
the first end of the second current branch is connected with the first end of the first current branch, the second end of the second current branch is connected with the first power supply, and the third end of the second current branch is connected with the output end;
the second current branch is configured to output a second current at a third terminal of the second current branch in response to the first voltage signal to generate a second voltage at the output terminal based on the first current and the second current, wherein a sum of the first voltage and the second voltage is applied to the first connection point to introduce a zero for compensating the first pole.
10. The low dropout linear regulator of claim 9 wherein the second current branch comprises a second transistor;
the first end of the second transistor is connected with the first end of the first current branch, the second end of the second transistor is connected with the first power supply, and the third end of the second transistor is connected with the output end.
11. The low dropout regulator according to claim 9 or 10, wherein the transconductance of the second current branch is N times that of the first current branch, N > 1;
the resistance value r3 of the resistance branch, the equivalent output resistance r2 of the first end of the error amplification branch and the equivalent capacitance c2 of the first end of the first current branch satisfy the following relations:
r3＝(N+1)*r2*c2/cL；
wherein cL is an output capacitance in the load.
12. The LDO of claim 1, further comprising a current mirror branch;
the first end of the current mirror branch circuit is connected with the first end of the first current branch circuit, the second end of the current mirror branch circuit is connected with the first power supply, the third end of the current mirror branch circuit is connected with the first connecting point, and the fourth end of the current mirror branch circuit is grounded;
the current mirror branch is configured to generate a first direct current flowing out of the first connection point, and the first direct current is equal to the direct current flowing through the first current branch in magnitude, so that the direct current flowing through the resistance branch is zero.
13. The low dropout regulator of claim 12 wherein the current mirror branch comprises a fourth transistor, a fifth transistor, and a sixth transistor;
the fourth transistor is respectively connected with the first current branch and the fifth transistor, and the fourth transistor is used for generating a second direct current flowing through the fifth transistor;
the sixth transistor is connected to the fifth transistor and the first connection point, respectively, and the sixth transistor is configured to generate the first direct current based on the second direct current.
14. The low dropout regulator of claim 13 wherein a first terminal of the fourth transistor is connected to the first terminal of the first current branch, a second terminal of the fourth transistor is connected to the first power supply, a third terminal of the fourth transistor is connected to the third terminal of the fifth transistor and the first terminal of the fifth transistor, a second terminal of the sixth transistor and the second terminal of the fifth transistor are both grounded, and a third terminal of the sixth transistor is connected to the first connection point;
the first end of the fourth transistor is the first end of the current mirror branch, the second end of the fourth transistor is the second end of the current mirror branch, the third end of the sixth transistor is the third end of the current mirror branch, and the second end of the sixth transistor is the fourth end of the current mirror branch.
15. The LDO of claim 13, further comprising a filtering branch;
the first end of the filtering branch circuit is connected with the first end of the fifth transistor, the second end of the filtering branch circuit is connected with the first end of the sixth transistor, and the third end of the filtering branch circuit is grounded;
the filtering branch is configured to low-pass filter the alternating current signal in the current mirror branch to keep the current in the current mirror branch as a direct current.
16. The low dropout regulator according to claim 15, wherein the filter branch comprises a fourth resistor and a first capacitor;
a first end of the fourth transistor is connected with a first end of the first current branch, a second end of the fourth transistor is connected with the first power supply, a third end of the fourth transistor is respectively connected with a third end of the fifth transistor, a first end of the fourth resistor and a first end of the fifth transistor, a second end of the fourth resistor is respectively connected with a first end of the sixth transistor and a first end of the first capacitor, a second end of the sixth transistor, a second end of the fifth transistor and a second end of the first capacitor are all grounded, and a third end of the sixth transistor is connected with the first connection point;
the first end of the fourth transistor is the first end of the current mirror branch, the second end of the fourth transistor is the second end of the current mirror branch, the third end of the sixth transistor is the third end of the current mirror branch, and the second end of the sixth transistor is the fourth end of the current mirror branch.
17. A control system, comprising:
a load and a low dropout linear regulator according to any one of claims 1 to 16;
the low dropout linear regulator is connected with the load and is used for providing voltage and current for the load.
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| CN116979806A (en) * | 2023-09-22 | 2023-10-31 | 希荻微电子集团股份有限公司 | Switch control circuit and method and power conversion system |
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