CN114999380A

CN114999380A - Driving circuit, driving method and display panel

Info

Publication number: CN114999380A
Application number: CN202210803467.4A
Authority: CN
Inventors: 张淑媛
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-07-07
Filing date: 2022-07-07
Publication date: 2022-09-02

Abstract

The driving circuit comprises a driving transistor, a first light emitting control module, a second light emitting control module, a light emitting device and a writing module, and can avoid the problem that the voltage of a first electrode of the driving transistor is changed due to continuous writing of a data signal in a low-frequency state, so that the voltage difference between the first electrode and a grid electrode of the driving transistor is changed, the threshold voltage of the driving transistor is drifted, and the display panel flickers.

Description

Driving circuit, driving method and display panel

Technical Field

The application relates to the field of display, in particular to a driving circuit, a driving method and a display panel.

Background

From the current market application, the low-temperature polysilicon product is more and more widely used on a high-end flagship, and as a fist performance index of the low-temperature polysilicon product, low power consumption and low-frequency flicker become more and more important consideration points for limiting the product taste, and therefore, the requirements on the power consumption and the flicker of the low-temperature polysilicon product are more and more strict.

In the existing pixel driving circuit, a data signal cannot be normally written in a low-frequency state, a gate node of a low-frequency (10 Hz or 1 Hz) driving transistor has very long non-writing time, and in a frame skipping period, the data signal can be continuously written in a source electrode of the driving transistor, so that the three-terminal voltage of the driving transistor changes, and the threshold voltage of the driving transistor drifts under the influence of the hysteresis characteristic of the transistor, and finally the data signal writing frame and the frame skipping luminance brightness are inconsistent, and the brightness difference can cause the brightness to regularly change, thereby causing the problem that a display panel flickers.

Disclosure of Invention

The application provides a driving circuit, a driving method and a display panel, which can solve the problem that the threshold voltage drift of a driving transistor is caused by continuous writing of a data signal in the existing driving circuit, and then the display panel flickers.

In a first aspect, the present application provides a driving circuit comprising: the light-emitting diode comprises a driving transistor, a first light-emitting control module, a second light-emitting control module, a light-emitting device and a writing module, wherein a grid electrode of the driving transistor is electrically connected with a first node, a first electrode of the driving transistor is electrically connected with a second node, and a second electrode of the driving transistor is electrically connected with a third node; the first light-emitting control module is connected to a first light-emitting control signal and is electrically connected to the second node and a first power end, and the first light-emitting control module is used for controlling the connection or disconnection between the first power end and the second node under the control of the first light-emitting control signal; the second light-emitting control module is connected to a second light-emitting control signal and is electrically connected to the third node and the fourth node, and the second light-emitting control module is used for controlling the connection or disconnection between the third node and the fourth node under the control of the second light-emitting control signal; a first end of the light emitting device is electrically connected with the fourth node, and a second end of the light emitting device is electrically connected with a second power supply end; the write-in module is connected to a data signal, a first scanning signal and a second scanning signal and is electrically connected to the first node, the second node and the third node, and the write-in module is used for outputting the data signal to the first node under the control of the first scanning signal and the second scanning signal; the write module is further configured to disconnect a line between the data signal and the second node under control of the second scan signal.

Optionally, in an embodiment of the present application, the writing module includes a first transistor, a second transistor, a third transistor, and a first capacitor, a gate of the first transistor is connected to the first scan signal, a first electrode of the first transistor is connected to the data signal, and a second electrode of the first transistor is electrically connected to a fifth node; a gate of the second transistor is connected to the second scan signal, a first electrode of the second transistor is electrically connected to the fifth node, and a second electrode of the second transistor is electrically connected to the second node; a gate of the third transistor is connected to the second scan signal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the first node; one end of the first capacitor is connected to the first scanning signal, and the other end of the first capacitor is electrically connected with the first node.

Optionally, in an embodiment of the present application, the write module further includes a second capacitor, one end of the second capacitor is electrically connected to the first power source end, and the other end of the second capacitor is electrically connected to the first node.

Optionally, in an embodiment of the present application, the write module further includes a third capacitor, one end of the third capacitor is electrically connected to the first power source end, and the other end of the third capacitor is electrically connected to the fifth node.

Optionally, in an embodiment of the present application, the driving circuit further includes a reset module, the reset module is connected to the first reset signal, the second reset signal, the third scan signal and the fourth scan signal, and is electrically connected to the first node and the fourth node, the reset module is configured to output the first reset signal to the first node under the control of the third scan signal, and the reset module is further configured to output the second reset signal to the fourth node under the control of the fourth scan signal.

Optionally, in an embodiment of the present application, the reset module includes a fourth transistor and a fifth transistor; a gate of the fourth transistor is connected to the third scanning signal, a first electrode of the fourth transistor is connected to the first reset signal, and a second electrode of the fourth transistor is electrically connected to the first node; the gate of the fifth transistor is connected to the fourth scan signal, the first electrode of the fifth transistor is connected to the second reset signal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

Optionally, in an embodiment of the present application, the first lighting control module includes a sixth transistor, a gate of the sixth transistor is connected to the first lighting control signal, a first electrode of the sixth transistor is electrically connected to the first power source terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

Optionally, in an embodiment of the present application, the second light-emitting control module includes a seventh transistor, a gate of the seventh transistor is connected to the second light-emitting control signal, a first electrode of the seventh transistor is electrically connected to the third node, and a second electrode of the seventh transistor is electrically connected to the fourth node.

In a second aspect, the present application also provides a driving method for driving the driving circuit described above, the driving method comprising: a data writing phase, in which the first light-emitting control module controls disconnection between the first power source terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing module outputs the data signal to the first node under the control of the first scan signal and the second scan signal;

and in the control phase, the first light-emitting control module controls disconnection between the first power supply end and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the write-in module disconnects a line between the data signal and the second node under the control of the first scanning signal and the second scanning signal.

In a third aspect, the present application further provides a display panel, where the display panel includes a plurality of pixels arranged in an array, and each of the pixels includes the above-mentioned driving circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 2 is a first circuit schematic diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 3a is a second circuit schematic diagram of a driving circuit according to an embodiment of the present disclosure;

FIG. 3b is a third schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 3c is a fourth circuit diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 4a is a fifth circuit schematic diagram of a driving circuit according to an embodiment of the present application;

fig. 4b is a sixth circuit schematic diagram of a driving circuit provided in the embodiment of the present application;

fig. 5a is a seventh circuit schematic diagram of a driving circuit provided in an embodiment of the present application;

fig. 5b is a circuit diagram illustrating an eighth circuit of the driving circuit according to the embodiment of the present disclosure;

fig. 6 is a ninth circuit schematic diagram of a driving circuit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of the driving circuit shown in FIG. 6;

fig. 8 is a schematic diagram illustrating voltage simulation of each node of a low-frequency frame according to an embodiment of the present disclosure;

fig. 9 is a schematic flowchart of a driving method according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the first electrode and the second electrode of the transistor used herein are symmetrical, the first electrode and the second electrode thereof can be interchanged. In the embodiments of the present application, to distinguish two electrodes of a transistor except for a gate, one of the two electrodes is referred to as a first electrode, and the other electrode is referred to as a second electrode.

In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 1, the driving circuit provided by the embodiment of the present application includes a light emitting device D, a driving transistor T0, a writing module 101, a first light emitting control module 102, and a second light emitting control module 103.

It should be noted that the Light Emitting device D may be a Micro Light Emitting Diode (Micro-LED), a Mini Light Emitting Diode (Mini-LED), or an Organic Light Emitting Diode (OLED). In some embodiments, the light emitting device DD may comprise a Micro-LED, a Mini-LED or an OLED. In other embodiments, the light emitting device DD may include a plurality of Micro-LEDs, a plurality of Mini-LEDs, or a plurality of OLEDs, the plurality of Micro-LEDs may be arranged in series or in parallel, the plurality of Mini-LEDs, and the plurality of OLEDs may be arranged in series or in parallel.

The light emitting device D is connected in series to a light emitting loop formed by the first power terminal VDD and the second power terminal VSS. Specifically, the first power supply terminal VDD and the second power supply terminal VSS are both dc voltage sources. A gate electrode of the driving transistor T0 is electrically connected to the first node Q, a first electrode of the driving transistor T0 is electrically connected to the second node a, and a second electrode of the driving transistor T0 is electrically connected to the third node B; the write module 101 receives the DATA signal DATA, the first SCAN signal SCAN1 and the second SCAN signal SCAN2, and is electrically connected to the first node Q, the second node A and the third node B. The first lighting control module 102 is connected to the first lighting control signal EM1, and is electrically connected to the first power terminal VDD and the second node a; the second light-emitting control module 103 is connected to the second light-emitting control signal EM2, and is electrically connected to the third node B and the fourth node C. A first terminal of the light emitting device D is electrically connected to the fourth node C, and a second terminal of the light emitting device D is electrically connected to the second power source terminal VSS.

Specifically, the driving transistor T0 is used to control the current flowing through the driving circuit. The write module 101 outputs the DATA signal DATA to the first node Q under the control of the first SCAN signal SCAN1 and the second SCAN signal SCAN2, and controls the output of the DATA signal DATA under the control of the second SCAN signal SCAN 2. The first lighting control module 102 is configured to control the connection or disconnection between the first power source terminal VDD and the second node a under the control of the first lighting control signal EM 1. The second light emission control module 103 is configured to control the third node B and the fourth node C to be turned on or off under the control of the second light emission control signal EM 2.

Note that, the first node Q, the second node a, the third node B, and the fourth node C are all nodes electrically connected to corresponding devices, and are merely represented in an electrical connection relationship, and the first node Q, the second node a, the third node B, and the fourth node C are not represented as terminals.

In some embodiments, please refer to fig. 2, wherein fig. 2 is a first circuit diagram of a driving circuit provided in the present application. Referring to fig. 1 and 2, the write module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1, wherein a gate of the first transistor T1 is connected to the first SCAN signal SCAN1, a first electrode of the first transistor T1 is connected to the DATA signal DATA, and a second electrode of the first transistor T1 is electrically connected to the fifth node E; a gate of the second transistor T2 is connected to the second SCAN signal SCAN2, a first electrode of the second transistor T2 is electrically connected to the fifth node E, and a second electrode of the second transistor T2 is electrically connected to the second node a; a gate electrode of the third transistor T3 is connected to the second SCAN signal SCAN2, a first electrode of the third transistor T3 is electrically connected to the third node B, and a second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first SCAN signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. The driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors. The first capacitor C1 is used for storing the corresponding potential of the data signal.

In some embodiments, please refer to fig. 3a, and fig. 3a is a second circuit diagram of a driving circuit according to an embodiment of the present disclosure. Referring to fig. 1 and 3a, the write module includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2, wherein a gate of the first transistor T1 is connected to the first SCAN signal SCAN1, a first electrode of the first transistor T1 is connected to the DATA signal DATA, and a second electrode of the first transistor T1 is electrically connected to the fifth node E; a gate of the second transistor T2 is connected to the second SCAN signal SCAN2, a first electrode of the second transistor T2 is electrically connected to the fifth node E, and a second electrode of the second transistor T2 is electrically connected to the second node a; a gate electrode of the third transistor T3 is connected to the second SCAN signal SCAN2, a first electrode of the third transistor T3 is electrically connected to the third node B, and a second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first SCAN signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. The driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors; one end of the second capacitor C2 is electrically connected to the first power terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q. Such a design is different from the prior art in which the capacitor is electrically connected to the variable signal, and one end of the second capacitor C2 is electrically connected to the first power source terminal, and the other end is electrically connected to the first node Q, so that the second capacitor C2 can be used for storing the corresponding potential of the DATA signal DATA, and can also achieve the voltage stabilizing effect on the first node Q.

In some embodiments, please refer to fig. 3b, and fig. 3b is a third circuit diagram of the driving circuit according to the embodiment of the present disclosure. Referring to fig. 1 and 3b, the write module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a third capacitor C3, wherein a gate of the first transistor T1 is connected to the first SCAN signal SCAN1, a first electrode of the first transistor T1 is connected to the DATA signal DATA, and a second electrode of the first transistor T1 is electrically connected to the fifth node E; a gate electrode of the second transistor T2 is connected to the second SCAN signal SCAN2, a first electrode of the second transistor T2 is electrically connected to the fifth node E, and a second electrode of the second transistor T2 is electrically connected to the second node a; a gate electrode of the third transistor T3 is connected to the second SCAN signal SCAN2, a first electrode of the third transistor T3 is electrically connected to the third node B, and a second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first SCAN signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. The driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors; one terminal of the third capacitor C3 is electrically connected to the first power terminal VDD, and the other terminal of the third capacitor C3 is electrically connected to the fifth node E. Such a design is different from the prior art in which the capacitor is electrically connected to the variable signal, and one end of the third capacitor C3 is electrically connected to the first power source terminal, and the other end is electrically connected to the fifth node E, so that the third capacitor C3 can be used for storing the corresponding potential of the DATA signal DATA, and can also achieve a voltage stabilizing effect on the fifth node E.

In some embodiments, please refer to fig. 3c, wherein fig. 3c is a fourth circuit diagram of the driving circuit provided in the present application. Referring to fig. 1 and 3C, the write module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and a third capacitor C3, wherein a gate of the first transistor T1 is connected to the first SCAN signal SCAN1, a first electrode of the first transistor T1 is connected to the DATA signal DATA, and a second electrode of the first transistor T1 is electrically connected to a fifth node E; a gate of the second transistor T2 is connected to the second SCAN signal SCAN2, a first electrode of the second transistor T2 is electrically connected to the fifth node E, and a second electrode of the second transistor T2 is electrically connected to the second node a; a gate electrode of the third transistor T3 is connected to the second SCAN signal SCAN2, a first electrode of the third transistor T3 is electrically connected to the third node B, and a second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to a first SCAN signal SCAN, and the other end of the first capacitor C1 is electrically connected to a first node Q; one end of the second capacitor C2 is electrically connected to the first power terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q; one terminal of the third capacitor C3 is electrically connected to the first power terminal VDD, and the other terminal of the third capacitor C3 is electrically connected to the fifth node E. The driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

In some embodiments, please refer to fig. 4a, and fig. 4a is a fifth circuit diagram of a driving circuit according to an embodiment of the present disclosure. Referring to fig. 1 and 4a, the driving circuit further includes a reset module 104, and the reset module 104 is connected to the first reset signal VINI1, the second reset signal VINI2, the third SCAN signal SCAN3 and the fourth SCAN signal SCAN4, and is electrically connected to the first node Q and the fourth node C. The reset module 104 is configured to output a first reset signal VINI1 to the first node Q under the control of the third SCAN signal SCAN3, and the reset module 104 is further configured to output a second reset signal VINI2 to the fourth node C under the control of the fourth SCAN signal SCAN 4.

In some embodiments, please refer to fig. 4b, where fig. 4b is a sixth circuit diagram of a driving circuit provided in the present application. As shown in fig. 1 and 4b, the reset module 104 includes a fourth transistor T4 and a fifth transistor T5; a gate electrode of the fourth transistor T4 is connected to the third SCAN signal SCAN3, a first electrode of the fourth transistor T4 is connected to the first reset signal VINI1, and a second electrode of the fourth transistor T4 is electrically connected to the first node Q; a gate of the fifth transistor T5 is connected to the fourth SCAN signal SCAN4, a first electrode of the fifth transistor T5 is connected to the second reset signal VINI2, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node C. Preferably, the fourth transistor T4 is an N-type transistor, and the fifth transistor T5 is a P-type transistor.

In some embodiments, please refer to fig. 5a, and fig. 5a is a seventh circuit diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 1 and 5a, the first light emitting control module 102 includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the first light emitting control signal EM1, a first electrode of the sixth transistor T6 is electrically connected to the first power terminal VDD, and a second electrode of the sixth transistor T6 is electrically connected to the second node a. It should be noted that the specific circuit structure of the first light-emitting control module in the driving circuit provided in the embodiment of the present application is merely an example, and it can be understood that the first light-emitting control module may also be formed by connecting a plurality of transistors in series.

In some embodiments, please refer to fig. 5b, and fig. 5b is an eighth circuit diagram of the driving circuit according to the embodiment of the present disclosure. As shown in fig. 1 and 5B, the second light emission control module 103 includes a seventh transistor T7, a gate of the seventh transistor T7 is connected to the second light emission control signal EM2, a first electrode of the seventh transistor T7 is electrically connected to the third node B, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node C. It should be noted that the specific circuit structure of the second light-emitting control module in the driving circuit provided in the embodiment of the present application is only an example, and it can be understood that the second light-emitting control module may also be formed by connecting a plurality of transistors in series.

Further, the present embodiment will describe a complete circuit of the driving circuit. Referring to fig. 6, fig. 6 is a ninth circuit diagram of a driving circuit according to an embodiment of the disclosure. As shown in fig. 6, the driving circuit provided in the embodiment of the present application includes a light emitting device D, a driving transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

The driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be one or more of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor. Preferably, the driving transistor T0, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are P-type transistors, and the second transistor T2, the third transistor T3 and the fourth transistor T4 are N-type transistors.

In some embodiments, the transistors in the driving circuit provided in the embodiments of the present application may be set to be the same type of transistor, so as to avoid influence on the driving circuit caused by differences between different types of transistors.

A gate of the first transistor T1 is connected to the first SCAN signal SCAN1, a first electrode of the first transistor T1 is connected to the DATA signal DATA, and a second electrode of the first transistor T1 is electrically connected to the fifth node E; a gate of the second transistor T2 is connected to the second SCAN signal SCAN2, a first electrode of the second transistor T2 is electrically connected to the fifth node E, and a second electrode of the second transistor T2 is electrically connected to the second node a; a gate electrode of the third transistor T3 is connected to the second SCAN signal SCAN2, a first electrode of the third transistor T3 is electrically connected to the third node B, and a second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to a first SCAN signal SCAN, and the other end of the first capacitor C1 is electrically connected to a first node Q; one end of the second capacitor C2 is electrically connected to the first power terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q; a gate of the fourth transistor T4 is connected to the third SCAN signal SCAN3, a first electrode of the fourth transistor T4 is connected to the first reset signal VINI1, and a second electrode of the fourth transistor T4 is electrically connected to the first node Q; a gate of the fifth transistor T5 is connected to the fourth SCAN signal SCAN4, a first electrode of the fifth transistor T5 is connected to the second reset signal VINI2, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node C; a gate of the sixth transistor T6 is connected to the first emission control signal EM1, a first electrode of the sixth transistor T6 is electrically connected to the first power terminal VDD, and a second electrode of the sixth transistor T6 is electrically connected to the second node a; a gate of the seventh transistor T7 is connected to the second emission control signal EM2, a first electrode of the seventh transistor T7 is electrically connected to the third node B, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node C; a first terminal of the light emitting device D is electrically connected to the fourth node C, and a second terminal of the light emitting device D is electrically connected to the second power source terminal VSS.

Referring to fig. 7, fig. 7 is a timing diagram of the driving circuit shown in fig. 1. Referring to fig. 1, 6 and 7, the driving timing of the driving circuit according to the embodiment of the present disclosure includes a data writing phase t2, a control phase t3 and a light emitting phase t 4.

In the DATA write phase t2, the first light-emitting control module 102 controls the disconnection between the first power source terminal VDD and the second node a under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2, and the write module 101 outputs the DATA signal DATA to the first node Q under the control of the first SCAN signal SCAN1 and the second SCAN signal SCAN 2.

In the control phase t3, the first light-emitting control module 102 controls the disconnection between the first power source terminal VDD and the second node a under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2, and the write module 101 disconnects the line between the DATA signal DATA and the second node a under the control of the first SCAN signal SCAN1 and the second SCAN signal SCAN 2.

In the light emitting period t4, the light emitting device D emits light.

Optionally, in some embodiments, the driving circuit further includes a reset module 104, the driving timing of the driving circuit further includes a reset phase t1, and in the reset phase t1, the reset module 104 writes the potential of the first reset signal VINI1 into the first node Q under the control of the first reset signal VINI 1.

In the data write phase t2, the reset module 104 writes the potential of the second reset signal VINI2 to the fourth node C under the control of the second reset signal VINI 2. The arrangement is favorable for avoiding the mutual influence between the two reset signals.

The application provides a driving circuit, including light emitting device D, driving transistor T0, write in module 101, first light emitting control module 102 and second light emitting control module 103, adopt this driving circuit can avoid under the low frequency state DATA signal DATA continuous write in to lead to the voltage of the first electrode of driving transistor T0 to change, and then make the voltage difference between the first electrode of driving transistor T0 and the grid change, lead to the threshold voltage of driving transistor T0 to drift, and then cause the problem that the display panel appears the scintillation.

Referring to fig. 8 in combination with fig. 1, fig. 6, and fig. 7, fig. 8 is a schematic diagram illustrating voltage simulation of each node of a low frequency frame according to an embodiment of the present disclosure. As shown in fig. 8, in the low frequency state, the voltage of the first electrode and the voltage of the gate of the driving transistor T0 tend to be stable, and a voltage difference (V) flows between the first electrode and the gate of the driving transistor T0 _gs ) There is no significant change, i.e. the voltages at the first node Q and the second node a are stable.

The second transistor T2 controlled by a second SCAN signal SCAN2 is arranged, the situation that the voltage of the first electrode of the driving transistor T0 changes due to continuous writing of the DATA signal DATA in a low-frequency state is shielded, the voltage difference between the first electrode of the driving transistor T0 and the grid electrode changes, the threshold voltage of the driving transistor T0 drifts, the problem that flicker occurs to a display panel is caused, the stability of the first electrode, the second electrode and the grid electrode voltage of the driving transistor T0 is guaranteed in the low-frequency state, and the stability of the driving transistor T0 is improved.

Referring to fig. 9, fig. 9 is a schematic flowchart of a driving method according to an embodiment of the present disclosure. As shown in fig. 9, the driving method provided in the embodiment of the present application is used in the above driving circuit. The driving method includes the steps of:

s10, in the DATA writing phase, the first light-emitting control module 102 controls the first power supply terminal VDD to be disconnected from the second node a under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the third node B to be disconnected from the fourth node C under the control of the second light-emitting control signal EM2, and the write module 101 outputs the DATA signal DATA to the first node Q under the control of the first SCAN signal SCAN1 and the second SCAN signal SCAN 2.

S20, the first light-emitting control module 102 controls the first power supply terminal VDD to be disconnected from the second node a under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the third node B to be disconnected from the fourth node C under the control of the second light-emitting control signal EM2, and the write module 101 disconnects the DATA signal DATA from the second node a under the control of the first SCAN signal SCAN1 and the second SCAN signal SCAN 2.

S30, in the light emitting stage, the light emitting device D emits light.

Optionally, in some embodiments, the driving method further includes a reset phase, and the reset module 104 writes the potential of the first reset signal VINI1 into the first node Q under the control of the first reset signal VINI 1.

In some embodiments, the reset module 104 writes the potential of the second reset signal VINI2 to the fourth node C under the control of the second reset signal VINI2 during the reset phase.

Alternatively, in some embodiments, the reset module 104 writes the potential of the second reset signal VINI2 to the fourth node C under the control of the second reset signal VINI2 during the data writing phase. The arrangement is favorable for avoiding the mutual influence between the two reset signals.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides a display panel 100, which includes a plurality of pixels 20 arranged in an array, and each pixel 11 includes the above driving circuit 10, which may refer to the description of the driving circuit 10 above and will not be described herein again.

The application provides a driving circuit in a display panel, including light emitting device D, driving transistor T0, write module 101, first light emitting control module 102 and second light emitting control module 103, adopt this driving circuit can avoid under the low frequency state DATA signal DATA continuously write in and lead to the voltage of the first electrode of driving transistor T0 to change, and then make the voltage difference between the first electrode and the grid of driving transistor T0 change, lead to the threshold voltage of driving transistor T0 to drift, and then cause the problem that the display panel appears the scintillation.

The foregoing is a preferred embodiment of the present application and it should be noted that modifications and embellishments could be made by those skilled in the art without departing from the principle described in the present application and should also be considered as within the scope of the present invention.

Claims

1. A driver circuit, comprising:

the grid electrode of the driving transistor is electrically connected with a first node, the first electrode of the driving transistor is electrically connected with a second node, and the second electrode of the driving transistor is electrically connected with a third node;

the first light-emitting control module is connected to a first light-emitting control signal and is electrically connected to the second node and a first power end, and the first light-emitting control module is used for controlling the connection or disconnection between the first power end and the second node under the control of the first light-emitting control signal;

the second light-emitting control module is connected to a second light-emitting control signal and is electrically connected to the third node and a fourth node, and the second light-emitting control module is used for controlling the connection or disconnection between the third node and the fourth node under the control of the second light-emitting control signal;

a light emitting device, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to a second power supply terminal;

a write module, which is connected to a data signal, a first scanning signal and a second scanning signal, and is electrically connected to the first node, the second node and the third node, and is configured to output the data signal to the first node under the control of the first scanning signal and the second scanning signal; the write module is further configured to disconnect a line between the data signal and the second node under control of the second scan signal.

2. The driving circuit according to claim 1, wherein the writing module comprises a first transistor, a second transistor, a third transistor, and a first capacitor;

a grid electrode of the first transistor is connected with the first scanning signal, a first electrode of the first transistor is connected with the data signal, and a second electrode of the first transistor is electrically connected with a fifth node;

a gate of the second transistor is connected to the second scan signal, a first electrode of the second transistor is electrically connected to the fifth node, and a second electrode of the second transistor is electrically connected to the second node;

a gate of the third transistor is connected to the second scan signal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the first node;

one end of the first capacitor is connected to the first scanning signal, and the other end of the first capacitor is electrically connected with the first node.

3. The driving circuit according to claim 2, wherein the writing module further comprises a second capacitor, one end of the second capacitor is electrically connected to the first power source terminal, and the other end of the second capacitor is electrically connected to the first node.

4. The driving circuit according to claim 2, wherein the writing module further comprises a third capacitor, one end of the third capacitor is electrically connected to the first power supply terminal, and the other end of the third capacitor is electrically connected to the fifth node.

5. The driving circuit according to claim 1, further comprising a reset module, wherein the reset module is connected to a first reset signal, a second reset signal, a third scan signal and a fourth scan signal and is electrically connected to the first node and the fourth node, the reset module is configured to output the first reset signal to the first node under the control of the third scan signal, and the reset module is further configured to output the second reset signal to the fourth node under the control of the fourth scan signal.

6. The driving circuit according to claim 5, wherein the reset module comprises a fourth transistor and a fifth transistor;

a gate of the fourth transistor is connected to the third scanning signal, a first electrode of the fourth transistor is connected to the first reset signal, and a second electrode of the fourth transistor is electrically connected to the first node;

the gate of the fifth transistor is connected to the fourth scan signal, the first electrode of the fifth transistor is connected to the second reset signal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

7. The driving circuit according to claim 1, wherein the first light-emitting control module comprises a sixth transistor, a gate of the sixth transistor is connected to the first light-emitting control signal, a first electrode of the sixth transistor is electrically connected to the first power source terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

8. The driving circuit according to claim 1, wherein the second light emitting control module comprises a seventh transistor, a gate of the seventh transistor is connected to the second light emitting control signal, a first electrode of the seventh transistor is electrically connected to the third node, and a second electrode of the seventh transistor is electrically connected to the fourth node.

9. A driving method for driving the driving circuit according to any one of claims 1 to 8, characterized in that the driving method comprises:

a data writing-in phase, in which the first light-emitting control module controls disconnection between the first power terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing-in module outputs the data signal to the first node under the control of the first scan signal and the second scan signal;

10. A display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising the driving circuit of any one of claims 1-8.