CN114970428A - Verification system and method for Flexray bus controller in SoC - Google Patents
Verification system and method for Flexray bus controller in SoC Download PDFInfo
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Abstract
The invention discloses a verification system and a method for a Flexray bus controller in SoC (System on chip), belongs to the technical field of integrated circuit verification, and provides a verification method for the Flexray bus controller in SoC (System on chip). The test efficiency of the Flexray node in the system on chip can be effectively improved by the verification method.
Description
Technical Field
The invention belongs to the technical field of integrated circuit verification, and particularly relates to a verification system and method for a Flexray bus controller in an SoC.
Background
Flexray is a new generation of high-performance bus, has the characteristics of more flexible data communication, higher data rate, more comprehensive topology selection, better fault-tolerant operation and the like compared with a CAN (controller area network) bus, and is widely applied to the field of vehicle-mounted control at present. The security of the vehicle network control system is important, and the network topology has a significant impact in the vehicle network. The Flexray bus provides flexible configuration and can support various topologies, such as bus, star and mixed topologies, the Flexray utilizes two independent physical lines for communication, the data rate of each line is 10mbps, the two communication lines are mainly used for realizing redundancy, therefore, the message transmission has fault-tolerant capability, and the two lines can also be used for transmitting different messages, so that the data throughput can be doubled. The Flexray bus thus provides the required speed and reliability for the next generation of in-vehicle control systems.
The Flexray bus controller test in the traditional SoC needs software to participate in frame coding, frame analysis and result comparison, often the work occupies a large amount of system resources and simulation time, and the related test environment and use cases can not be reused due to different SoC structures, thereby further influencing the verification progress.
Disclosure of Invention
In order to overcome the disadvantages of the prior art, an object of the present invention is to provide a verification system and method for a Flexray bus controller in an SoC, which improve the verification efficiency of the system and provide effective guidance for the verification of similar products.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
the invention discloses a verification system for a Flexray bus controller in an SoC, which comprises: the system comprises a system bus end coding model, a multi-buffer type software data sending and receiving unit, an application end data transmission marking and collecting unit, a driving structure and a scoring board; the multi-buffer software data sending and receiving unit for data receiving and sending carries out data interaction with the marking and collecting unit of the application end transmission data, the marking and collecting unit of the application end transmission data informs a system bus end coding model to begin analyzing and coding data of a system bus end, the coded data are written into the score counting board, the driving structure is connected with the Flexray controller, the driving structure drives a Flexray bus node to transmit and monitors the transmission of the Flexray bus controller node on the Flexray bus, the data are written into the score counting board, and index type data checking is realized by the score counting board.
Preferably, the system bus end coding model is used for monitoring data interaction between a host and a Flexray bus controller on a bus in an SoC, extracting data sent or received by the Flexray bus controller according to a register and a memory address, analyzing the data of the system bus end, coding the data according to a Flexray bus data frame format, directly acquiring a data type consistent with a transmission format on the Flexray bus, and sending the data type to the Scoreboard score board.
Preferably, the multi-Buffer software data sending and receiving unit is configured to plan data to be sent or received through the Flexray bus controller in the MEM in advance by simulating multiple sets of Message Buffer operations at the software application end, write the data to be sent into the planned sending Message Buffer address space through the software end in advance, reserve a free receiving Message Buffer address space in advance for the data to be received, and update the MEM address corresponding to the Message Buffer sent or received by the Flexray bus controller through the host end after the Flexray bus controller starts sending or receiving the data to complete data sending and receiving.
Preferably, the data is programmed in MEM such that the internally related MEM is divided into a plurality of separate Message Buffer memory spaces.
Preferably, the marking and collecting unit of the application-side transmission data is used for marking certain application-specific data streams by selecting accesses of some reserved address spaces inside the Flexray bus controller.
Preferably, the drive structure is connected to the Flexray controller through a Flexray bus a channel and a Flexray bus B channel.
Preferably, the driving structure comprises an a _ node _1 node, an a _ node _2 node, an a _ node _3 node, a P _ node _4 node, a Flexray bus a channel and a B channel; the A _ node _1 node is connected with the A channel and the B channel and is a double-channel transmission node, the A _ node _2 node is connected with the A channel and is a single-channel transmission node, the A _ node _3 node is connected with the B channel and is a single-channel transmission node, and the P _ node _4 node is connected with the A channel and the B channel to monitor the Flexray controller node to be tested.
Preferably, the score board is configured to retrieve a system bus data FIFO or a Flexray bus data FIFO, and determine whether the data comparison is correct.
The invention also discloses a Flexray bus controller data transmission verification based on a verification system for the Flexray bus controller in the SoC, which comprises the following steps:
s1: the host initializes and configures a Flexray controller as a sending mode;
s2: a multi-buffer software data transmitting and receiving unit configures MEM (memory information storage) in the SoC, and a storage space for transmitting data is planned in the MEM;
s3: the application end data transmission mark and acquisition unit writes the data of the application end into the MEM through the bus and writes the data into the mark at the same time;
s4: the method comprises the steps that a marking and acquisition unit of application end transmission data monitors a marking notification system bus end coding model;
s5: the system bus end coding model collects and codes the sent application end data from the system bus into Flexray bus format data, and writes the Flexray bus format data into system bus data FIFO in the score board;
s6: monitoring that a Flexray bus controller to be tested sends a data frame to a Flexray bus by a P _ node _4 node in a driving structure, writing the data into a Flexray bus data FIFO in a score counting board, and triggering the score counting board to start checking current data;
s7: and (3) sending data by the score board index system bus, testing pass if the same data exists, and testing Fail if the corresponding data does not exist.
The invention also discloses a Flexray bus controller data receiving verification based on a verification system for the Flexray bus controller in the SoC, which comprises the following steps:
s8: the host initializes and configures a Flexray controller as a receiving mode;
s9: a multi-buffer software data transmitting and receiving unit configures MEM (memory information storage) in the SoC, and a storage space for receiving data is planned in the MEM;
s10: an A _ node _1 node, an A _ node _2 node and an A _ node _3 node in a driving structure send data through a Flexray bus, and a P _ node _4 node writes monitored data received by a Flexray bus controller to be tested into a Flexray bus data FIFO in a score board;
s11: after the Flexray bus controller receives the data, calling a marking and acquisition unit of application end transmission data to read the received data from the corresponding MEM through the bus and write the received data into the marking;
s12: after the application end transmits the mark of the data and the acquisition unit monitors the mark, the application end informs a system bus end coding model to acquire the received data from a system bus and codes the data into Flexray bus format data;
s13: coding a system bus end coding model into Flexray bus format data, writing the Flexray bus format data into a system bus data FIFO in a score counting board, and triggering the score counting board to start checking current data;
s14: and the score board index Flexray bus receives data, pass is tested if the same data exist, and Fail is tested if the corresponding data do not exist.
Compared with the prior art, the invention has the following beneficial effects:
the invention discloses a verification system for a Flexray bus controller in an SoC, which comprises: the system comprises a system bus end coding model, a multi-buffer type software data sending and receiving unit, an application end data transmission marking and collecting unit, a driving structure and a scoring board; the system bus end coding model is used for analyzing and coding data of a system bus end, the coded data is written into a score board, a multi-buffer type software data sending and receiving unit is used for receiving and sending the data, an application end transmits a data mark and an acquisition unit marks the data and informs the system bus end coding model after the mark is obtained, a driving structure sends bus data to a Flexray bus controller or monitors the data of the Flexray bus controller and writes the data into the score board, the score board checks the data and outputs a result, the construction of an application end Flexray protocol data frame during the sending period through the cooperation of the five parts, the analysis of a received frame and the data comparison of a receiving and sending frame do not need to participate in a CPU, if the CPU in an SoC is used, a large amount of system simulation time is occupied, and the load of a server is increased, so that the test efficiency of the Flexray bus controller can be obviously improved, and accelerating the test process.
Further, the principles of the Flexray bus controller data transmission verification and reception verification disclosed by the present application are as follows: initializing a Flexray bus controller to be tested through a host, planning and configuring MEM memory space in the SoC, decomposing the memory space into a plurality of independent Message buffer address spaces for receiving or sending to store data of an application terminal, converting the sending or receiving data of the application terminal into data frames conforming to a Flexray bus format through a bus coding model and sending the data frames into a scoring board through marking and collecting the transmission data of the application terminal when a system bus terminal in the SoC carries out data transmission control on the Flexray controller, sending or monitoring the sending and receiving data of the Flexray bus controller node to be tested to the Flexray bus controller node through a node model in a Flexray bus driving structure, sending the data sent or received by the Flexray bus controller node to be tested at the Flexray bus terminal into the scoring board, and finally carrying out index type data check in the scoring board. The method and the principle can be suitable for testing the Flexray bus controllers in SoCs with different bus architectures, and have good application prospects.
Drawings
FIG. 1 is a schematic view of a driving structure of the present invention;
FIG. 2 is a schematic diagram of a verification method according to the present invention;
FIG. 3 is a flow chart of data reception verification according to the present invention;
fig. 4 is a flow chart of data transmission verification according to the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
a verification method for a Flexray bus controller in SoC (System on chip) uses UVM and SystemVerilog languages to realize a relevant verification system, and the verification system comprises a coding model 1 of system bus end data; a multi-Buffer (Message Buffer) software data transmitting and receiving unit 2; a marking and collecting unit 3 for transmitting data by an application terminal; drive structure 4 and scoreboard 5 for different transmission types; the multi-buffer software data transmitting and receiving unit 2 for data receiving and transmitting performs data interaction with the application end data transmission marking and collecting unit 3, the application end data transmission marking and collecting unit 3 informs the system bus end coding model 1 to begin analyzing and coding data of the system bus end, the coded data is written into the score plate 5, the driving structure 4 is connected with the Flexray controller, the driving structure 4 monitors the Flexray bus controller and writes the data into the score plate 5, and the score plate 5 realizes index type data inspection.
Multi-buffer software data transmitting and receiving unit 2: the method comprises the steps that internal relevant MEMs are divided into a plurality of independent Message Buffer storage spaces, data to be sent are written into the planned sending Message Buffer address space in advance through a software end, a free receiving Message Buffer address space is reserved in advance for the data to be received, and after the Flexray bus controller starts sending or receiving the data, the host end only needs to update the address of the Message Buffer sent or received by the Flexray bus controller to complete the sending and receiving of the relevant data.
The application end data transmission marking and acquisition unit 3: since the MEM data address space in the SoC may be accessed by other hosts or peripherals, in addition to controlling data, additional tag accesses are added at the application side of the Flexray bus controller, and some special application side data streams are tagged by selecting some reserved address spaces inside the Flexray bus controller, for example, the address space accessed after accessing tag address a is up to access tag address B, the data accessed between AB tags is the data that the application side needs to send through the Flexray bus controller, the address space accessed after accessing tag address C is up to access tag address D, and the data accessed between CD tags is the data that the application side receives through the Flexray bus controller.
The driving structure 4: in the method, a driving structure shown in the following figure 1 is designed, and single-A channel transmission, single-B channel transmission, AB dual-channel redundant transmission and AB dual-channel non-redundant transmission comprising a static section and a dynamic section are realized.
Wherein:
the node of A _ node _1 type can send static frame and dynamic frame in the A channel and the B channel in the Flexray bus, and the data sent by the A channel and the B channel can be sent separately, but the data is the same data;
nodes of the a _ node _2 type can send static frames and dynamic frames on the a channel in the Flexray bus.
Nodes of the a _ node _3 type can send static frames and dynamic frames on the B channel in the Flexray bus.
The node of the P _ node _4 type does not send any data, and the node is only responsible for monitoring the Flexray bus to collect the sending and receiving conditions of the Flexray controller node to be tested.
How various types of nodes can be used together specifically to achieve the above described transmission types is the scope of protection of the patent of the invention.
Scoring plate 5: due to the fact that the Flexray bus is a time slot multiplexing transmission mode, data which needs to be sent by an application end is not sent in a current Cycle or is repeatedly sent in a plurality of cycles in the data monitoring process, and high requirements are placed on accuracy of data checking. Aiming at the transmitted data, when the Flexray bus end monitors that the transmission of one frame of data is finished, the Scoreboard searches the data FIFO of the bus end of the system, and if the data are the same, the data comparison is correct; for received data, when the system bus receives a frame of data, the Scoreboard searches the data FIFO of the Flexray bus, and if there is the same received data, the data comparison is correct.
FIG. 2 is a schematic diagram of a Flexray bus controller verification method for SoC according to the present invention
The technical solution of the present invention will be more clearly and completely described with reference to fig. 2. As shown in fig. 2, the Felxray bus controller testing method includes a system bus end coding model 1, a multi-buffer software data sending and receiving unit 2, an application end data transmission marking and collecting unit 3, a driving structure 4 and a scoring board 5; the multi-buffer software data transmitting and receiving unit 2 for data receiving and transmitting performs data interaction with the application end data transmission marking and collecting unit 3, the application end data transmission marking and collecting unit 3 informs the system bus end coding model 1 to begin analyzing and coding data of the system bus end, the coded data is written into the score plate 5, the driving structure 4 is connected with the Flexray controller, the driving structure 4 monitors the Flexray bus controller and writes the data into the score plate 5, and the score plate 5 realizes index type data inspection.
Referring to fig. 3, Flexray bus controller data transmission verification: after a Flexray controller is initialized and configured by a host to be in a sending mode, firstly, a tx _ mb _ cfg201 function in a multi-buffer software data sending and receiving unit 2 is called to configure MEM inside the SoC, and a storage space for sending data is planned inside the MEM, as shown in fig. 2, Buf1 to Bufn distributed in the MEM; secondly, calling a mark of data transmission of the application end and a MEM _ write301 function in the acquisition unit 3 to write the data of the application end into the MEM through a bus and write the data into the mark at the same time; at this time, the Flag of the application end transmission data and the Flag _ finder in the acquisition unit 3 monitor that the Flag informs the system bus end coding model 1 to call a write _ bus101 function, and the sent application end data is acquired from the system bus, coded into data in a Flexray bus format and written into a system bus data FIFO in the score counting board 5; when the P _ node _4 node model monitors that the Flexray bus controller to be tested sends a data frame to the Flexray bus, calling a write _ scb _ tx401 function to write the data into a Flexray bus data FIFO in the score counting board 5 and triggering the score counting board 5 to start checking the current data; and finally, calling a find _ frame501 function in the scoring board 5, indexing the system bus to send data, testing pass if the same data exists, and testing Fail if the corresponding data does not exist.
Referring to fig. 4, Flexray bus controller data reception verification: in this scenario, after the host initializes and configures the Flexray controller to be in the receiving mode, the MEM inside the SoC is configured first through the rx _ mb _ cfg202 function in the multi-buffer software data transmitting and receiving unit 2, and the storage space of the received data is planned inside the MEM, as shown in fig. 2, where Buf1 to Bufn are allocated in the MEM; secondly, sending data through a Flexray bus by using nodes A _ node _1 to A _ node _3, simultaneously writing the monitored data received by a Flexray bus controller to be detected into a Flexray bus data FIFO in a score plate 5 through a write _ scb _ rx402 function by using a P _ node _4 node model, calling a mark of application end transmission data and a MEM _ read302 function in an acquisition unit 3 after the Flexray bus controller finishes receiving the data, reading the received data from a corresponding MEM through a bus, and writing the mark; at this time, the Flag of the application end transmitting data and the Flag _ finder in the acquisition unit 3 monitor that the Flag informs the system bus end coding model 1 to call a write _ bus101 function, the received data is acquired from the system bus and coded into data in a Flexray bus format, and the data is written into a system bus data FIFO in the score counting board 5 and triggers the score counting board 5 to check the current data; and finally, calling a find _ frame501 function in the scoring board 5, receiving data by the index Flexray bus, testing pass if the same data exist, and testing Fail if the corresponding data do not exist.
For the scene of simultaneous test of data receiving and transmitting, the above processes are only needed to be carried out simultaneously.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. An authentication system for a Flexray bus controller in a SoC, comprising: the system comprises a system bus end coding model (1), a multi-buffer type software data sending and receiving unit (2), an application end data transmission marking and collecting unit (3), a driving structure (4) and a scoring board (5); the multi-buffer software data transmitting and receiving unit (2) for data receiving and transmitting carries out data interaction with the application end data transmission marking and collecting unit (3), the application end data transmission marking and collecting unit (3) informs the system bus end coding model (1) to begin analyzing and coding data of the system bus end, the coded data are written into the score board (5), the driving structure (4) is connected with the Flexray controller, the driving structure (4) drives the Flexray bus node to transmit and monitors the transmission of the Flexray bus controller node on the Flexray bus, the data are written into the score board (5), and index type data checking is realized by the score board (5).
2. The system for verifying the Flexray bus controller in the SoC according to claim 1, wherein the system bus end coding model (1) is used for monitoring data interaction between a host and the Flexray bus controller on a bus in the SoC, extracting data sent or received by the Flexray bus controller according to a register and a memory address, analyzing the data at the system bus end, coding according to a data frame format of the Flexray bus, directly acquiring a data type consistent with a transmission format on the Flexray bus, and sending the data type to the Scoreboard score board.
3. The verification system for the Flexray bus controller in the SoC according to claim 1, wherein the multi-Buffer software data sending and receiving unit (2) is configured to simulate a plurality of sets of Message Buffer operations at the software application end, program data to be sent or received through the Flexray bus controller in MEM in advance, write the data to be sent into the programmed sending Message Buffer address space through the software end in advance, reserve a free receiving Message Buffer address space in advance for the data to be received, and update the MEM address corresponding to the sending or receiving Message Buffer of the Flexray bus controller through the host end after the Flexray bus controller starts sending or receiving the data to complete data transceiving.
4. The system of claim 3, wherein the data is programmed in the MEM to divide the internal MEM into a plurality of independent Message Buffer memory spaces.
5. An authentication system for a Flexray bus controller in a SoC according to claim 1, characterized in that the marking and collecting unit (3) for application side transport data is used to mark certain application specific data streams by selecting accesses of some reserved address spaces inside the Flexray bus controller.
6. An authentication system for a Flexray bus controller in a SoC according to claim 1, characterized in that the driver fabric (4) is connected to the Flexray controller through a Flexray bus A-channel and a Flexray bus B-channel.
7. A verification system for a Flexray bus controller in a SoC according to claim 6 characterized in that the driving architecture (4) comprises A _ node _1 node, A _ node _2 node, A _ node _3 node, P _ node _4 node, Flexray bus A channel and B channel; the A _ node _1 node is connected with the A channel and the B channel and is a double-channel transmission node, the A _ node _2 node is connected with the A channel and is a single-channel transmission node, the A _ node _3 node is connected with the B channel and is a single-channel transmission node, and the P _ node _4 node is connected with the A channel and the B channel to monitor the Flexray controller node to be tested.
8. The system for verifying the Flexray bus controller in the SoC according to claim 1, wherein the score board (5) is used for retrieving the data FIFO at the system bus end or the data FIFO at the Flexray bus end and judging whether the data comparison is correct or incorrect.
9. The Flexray bus controller data transmission verification method for the verification system of the Flexray bus controller in the SoC according to any one of claims 1 to 8, comprising the following steps:
s1: the host initializes and configures a Flexray controller as a sending mode;
s2: a multi-buffer software data transmitting and receiving unit (2) configures MEM in the SoC, and a storage space for transmitting data is planned in the MEM;
s3: the application end data transmission mark and acquisition unit (3) writes the data of the application end into the MEM through the bus and writes the data into the mark at the same time;
s4: the marking and acquisition unit (3) of the application end transmission data monitors the marking to inform the system bus end coding model (1);
s5: the system bus end coding model (1) collects and codes the sent application end data from the system bus into data in a Flexray bus format, and writes the data into system bus data FIFO in the scoring board (5);
s6: after monitoring that a Flexray bus controller to be tested sends a data frame to a Flexray bus, a P _ node _4 node in the driving structure (4) writes data into a Flexray bus data FIFO in the scoring board (5) and triggers the scoring board (5) to start checking current data;
s7: the scoring board (5) indexes the system bus to send data, pass is tested if the same data exist, and Fail is tested if the corresponding data do not exist.
10. The Flexray bus controller data reception verification method for the verification system of the Flexray bus controller in the SoC according to any one of claims 1 to 8, comprising:
s8: the host initializes and configures a Flexray controller as a receiving mode;
s9: a multi-buffer software data transmitting and receiving unit (2) configures MEM in the SoC, and a storage space for receiving data is planned in the MEM;
s10: an A _ node _1 node, an A _ node _2 node and an A _ node _3 node in a driving structure (4) send data through a Flexray bus, and a P _ node _4 node writes monitored data received by a Flexray bus controller to be tested into a Flexray bus data FIFO in a score board (5);
s11: after the Flexray bus controller receives the data, calling a marking and acquisition unit (3) of application end transmission data to read the received data from the corresponding MEM through the bus and write the received data into the marking;
s12: after the application end transmits the mark of the data and the acquisition unit (3) monitors the mark, the system bus end coding model (1) is informed to acquire the received data from the system bus and encode the data into Flexray bus format data;
s13: the system bus end coding model (1) is coded into Flexray bus format data and written into a system bus data FIFO in a score counting board (5) and triggers the score counting board (5) to start checking current data;
s14: the scoring board (5) indexes the Flexray bus to receive data, pass is tested if the same data exist, and Fail is tested if the corresponding data do not exist.
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| CN115685785A (en) * | 2022-12-29 | 2023-02-03 | 摩尔线程智能科技(北京)有限责任公司 | Universal bus model and simulation test method |
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| CN115685785A (en) * | 2022-12-29 | 2023-02-03 | 摩尔线程智能科技(北京)有限责任公司 | Universal bus model and simulation test method |
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