CN114975566A - Array substrate and display panel - Google Patents
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- CN114975566A CN114975566A CN202210707178.4A CN202210707178A CN114975566A CN 114975566 A CN114975566 A CN 114975566A CN 202210707178 A CN202210707178 A CN 202210707178A CN 114975566 A CN114975566 A CN 114975566A
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- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
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- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate and a display panel, wherein the array substrate comprises a substrate; the array layer is arranged on one side of the substrate and comprises at least one signal wiring layer, and the signal wiring layer comprises a first signal wire; and the shielding layer is arranged between the substrate and the array layer, at least part of the region of the shielding layer is multiplexed into a first signal wire, and the first signal wire of the shielding layer is connected with the first signal wire of the signal routing layer in parallel. The first signal wire of the shielding layer is connected with the first signal wire of the signal routing layer in parallel, according to the series-parallel resistance rule, after the first signal wires on different layers are connected in parallel, the total impedance of the first signal wires can be reduced, the voltage drop of the first signal wires is further reduced, the uniformity of voltage signals transmitted by the first signal wires is improved, and the problem of display uniformity of the array substrate when the array substrate is applied to a display panel is further improved.
Description
Technical Field
The invention belongs to the technical field of electronic products, and particularly relates to an array substrate and a display panel.
Background
Light Emitting elements such as Organic Light Emitting Diodes (OLEDs), mini Light Emitting diodes (mini LEDs) and micro Light Emitting diodes (micro LEDs) are widely used in the field of lighting and display technologies.
In order to drive the light emitting elements to emit light better for illumination or display, an array substrate for controlling the light emitting elements needs to be provided. In the existing array substrate, due to design limitations of the existing signal routing structure, voltage drops of the signal routing relative to the far end and the near end of the control chip are different, so that a display panel driven by the array substrate has the problem of display uniformity.
Therefore, a new array substrate and a new display panel are needed.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a display panel, which can reduce the voltage drop of a first signal line, improve the uniformity of a voltage signal transmitted by the first signal line and further improve the problem of display uniformity when the array substrate is applied to the display panel.
An embodiment of the present invention provides an array substrate, including: a substrate; the array layer is arranged on one side of the substrate and comprises at least one signal wiring layer, and the signal wiring layer comprises a first signal wire; the shielding layer is arranged between the substrate and the array layer, at least partial region of the shielding layer is multiplexed into the first signal line, and the first signal line of the shielding layer is connected with the first signal line of the signal routing layer in parallel.
According to one aspect of the invention, the array structure further comprises a buffer layer, wherein the buffer layer is arranged between the substrate and the array layer, and the shielding layer and the buffer layer are arranged on the same layer; or, the shielding layer is arranged between the substrate and the buffer layer.
According to one aspect of the invention, the substrate comprises a first substrate, a first water oxygen barrier layer, a second substrate and a second water oxygen barrier layer which are arranged in a stacked manner, and the shielding layer is arranged between the second water oxygen barrier layer and the buffer layer.
According to one aspect of the present invention, the array layer includes an active layer, a gate layer, a first source drain layer, and a second source drain layer stacked in a thickness direction of the array substrate; the signal wiring layer and at least one of the gate layer, the first source drain layer and the second source drain layer are arranged on the same layer.
According to one aspect of the invention, an insulating layer is arranged between two adjacent layers of the active layer, the gate layer, the first source drain layer and the second source drain layer; the same layer of the first source drain layer and the second source drain layer is provided with the signal wiring layer, and the first signal wire of the signal wiring layer and the first signal wire of the shielding layer are connected in parallel through a through hole penetrating through the insulating layer.
According to one aspect of the invention, the array layer comprises a driving transistor, and an orthographic projection of the shielding layer on the substrate covers an orthographic projection of the driving transistor on the substrate; preferably, the driving transistor includes a first driving transistor and a second driving transistor, one of the first driving transistor and the second driving transistor is a low temperature polysilicon transistor, and the other is an indium gallium zinc oxide transistor.
According to an aspect of the present invention, the first signal line is a high-level voltage signal line or a low-level voltage signal line.
According to one aspect of the invention, the shielding layer comprises at least one metal layer; preferably, the shielding layer comprises a copper metal layer; or, the shielding layer comprises a titanium-aluminum-titanium composite metal layer.
Another aspect of an embodiment of the present invention provides a display panel, including: an array substrate, the array substrate of any of the above embodiments of the array substrate.
According to another aspect of the present invention, the display panel further includes a control chip and a light emitting layer disposed on one side of the array substrate, the light emitting layer includes a light emitting unit, and the array layer includes a driving transistor electrically connected to the light emitting unit; one end of the first signal line is electrically connected to the control chip, and the other end is electrically connected to at least one of the light emitting unit and the driving transistor.
Compared with the prior art, the array substrate in the embodiment of the invention comprises a substrate, an array layer and a shielding layer, wherein the shielding layer is arranged between the substrate and the array layer, used for shielding electric charges or light rays at the substrate side from entering the array layer and influencing the normal operation of elements of the array layer, in the present embodiment, at least a partial region of the shielding layer is multiplexed into the first signal line, and the first signal line is multiplexed by using the original shielding layer without additionally forming a film layer for disposing the first signal line, the production cost can be reduced, and the first signal line of the shielding layer and the first signal line of the signal routing layer are connected in parallel, according to the series-parallel resistance law, after the first signal lines at different layers are connected in parallel, the total impedance of the first signal lines is reduced, therefore, the voltage drop of the first signal line is reduced, the uniformity of the voltage signal transmitted by the first signal line is improved, and the problem of display uniformity of the array substrate when the array substrate is applied to a display panel is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a circuit in the related art;
fig. 2 is a diagram illustrating a structure of a film layer of an array substrate according to an embodiment of the invention;
fig. 3 is a diagram illustrating a structure of a film layer of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic circuit diagram provided by an embodiment of the present invention;
fig. 5 is a schematic circuit diagram according to another embodiment of the present invention.
In the drawings:
1-a substrate; 11-a first substrate; 12-a first aqueous oxygen barrier layer; 13-a second substrate; 14-a second water oxygen barrier layer; 2-an array layer; 21-an active layer; 22-gate layer; 23-a first source drain layer; 24-a second source drain layer; 3-a shielding layer; 4-a first signal line; 5-a buffer layer; 6-a light-emitting unit; t1 — first drive transistor; t2 — second drive transistor.
Detailed Description
Features of various aspects and exemplary embodiments of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention can be combined with each other without contradiction.
In the related art, a signal line is connected to a control chip, a voltage signal is transmitted from one end of the control chip to one end of the signal line away from the control chip, as shown in fig. 1, since the signal line itself has a resistance, I is a current passed by the signal line according to a voltage formula U ═ R, I is a resistance of the signal line, and R is a resistance of the signal line, that is, an IR Drop located at a far end is the maximum, a voltage of a first sub-pixel 1 input by the signal line < a voltage of a second sub-pixel 2 < a voltage of a third sub-pixel 3, that is, currents passing through 3 sub-pixels are not uniform, light emission intensities are different, that is, a uniformity problem is generated, and a display effect of the display panel is affected.
In order to solve the above problems, embodiments of the present invention provide an array substrate and a display panel, in which at least a partial region of a shielding layer is multiplexed into a first signal line, and the first signal line of the shielding layer and the first signal line of a signal routing layer are connected in parallel to reduce a resistance of the first signal line, thereby reducing a voltage drop of the first signal line and improving a uniformity of a voltage signal transmitted by the first signal line.
Embodiments of the array substrate and the display panel will be described below with reference to fig. 2 to 5.
Referring to fig. 2, fig. 2 is a film structure diagram of an array substrate according to an embodiment of the invention.
An array substrate provided in an embodiment of the present invention includes: a substrate 1; the array layer 2 is arranged on one side of the substrate 1, the array layer 2 comprises at least one signal wiring layer, and the signal wiring layer comprises a first signal wire 4; and the shielding layer 3 is arranged between the substrate 1 and the array layer 2, at least partial area of the shielding layer 3 is multiplexed into a first signal line 4, and the first signal line 4 of the shielding layer 3 is connected with the first signal line 4 of the signal routing layer in parallel.
In the embodiment of the invention, the array substrate comprises a substrate 1, an array layer 2 and a shielding layer 3, wherein the shielding layer 3 is arranged between the substrate 1 and the array layer 2 and is used for shielding electric charges or light rays on the side of the substrate 1 from entering the array layer 2 to influence the normal operation of components of the array layer 2, in the implementation, at least partial area of the shielding layer 3 is multiplexed into a first signal wire 4 without additionally forming a film layer provided with the first signal wire 4, the original shielding layer 3 is utilized to multiplex the first signal wire 4, the production cost can be reduced, the first signal wire 4 of the shielding layer 3 and the first signal wire 4 of a signal routing layer are connected in parallel, according to a series-parallel resistance rule, after the first signal wires 4 on different layers are connected in parallel, the total impedance of the first signal wire 4 can be reduced, the voltage drop of the first signal wire 4 is further reduced, the uniformity of voltage signals transmitted by the first signal wire 4 is improved, thereby improving the display uniformity of the array substrate when the array substrate is applied to a display panel.
It should be noted that, because the shielding layer 3 needs to shield the charges on the substrate 1 side, the shielding layer 3 is usually made of a conductive material such as metal to absorb the charges on the substrate 1 side, and the first signal line 4 also needs to transmit signals, and the requirements of the two on the manufacturing materials are basically the same, so that in the embodiment provided by the present invention, at least a partial region of the shielding layer 3 can be multiplexed as the first signal line 4, and the first signal line 4 is formed without adding an additional mask plate, so that the production cost is reduced, and at the same time, the total impedance of the first signal line 4 can be effectively reduced.
It can be understood that, the two resistors are connected in parallel, and the total resistance of the two resistors will be reduced, in this embodiment, the total impedance of the first signal line 4 is reduced by using this rule, according to the voltage formula U ═ I × R, wherein the total impedance R of the first signal line 4 is reduced, that is, the voltage drop U of the first signal line 4 can be reduced, so as to reduce the light emitting difference of the light emitting units 6 respectively connected to the first signal line 4 at the far end and the near end with respect to the control chip, thereby improving the display uniformity problem of the array substrate when applied to the display panel.
In the present embodiment, the substrate 1 may be a hard substrate, such as a glass substrate; the flexible substrate can also be made of polyimide, polystyrene, polyethylene terephthalate, parylene, polyethersulfone or polyethylene naphthalate. The substrate 1 base plate is primarily used to support devices disposed thereon. And the substrate 1 can be a single-layer substrate 1 or a multi-layer substrate 1, for example, the substrate 1 can adopt a double-layer substrate 1 structure to improve the water and oxygen barrier and the bearing capacity.
In some optional embodiments, the array substrate further includes a buffer layer 5, the buffer layer 5 is disposed between the substrate 1 and the array layer 2, and the shielding layer 3 and the buffer layer 5 are disposed on the same layer; alternatively, the shield layer 3 is provided between the substrate 1 and the buffer layer 5.
It should be noted that the shielding layer 3 and the buffer layer 5 are disposed on the same layer, specifically, the shielding layer 3 may be disposed inside the buffer layer 5, or the shielding layer 3 may be disposed in a groove for fixing in a manner that a groove is disposed on a surface of one side of the buffer layer 5.
In this embodiment, the buffer layer 5 is disposed between the substrate 1 and the array layer 2, and is used to slowly release an acting force of the array substrate when being subjected to external impact, so as to protect the routing and components of the array layer 2 from being damaged, and optionally, the buffer layer 5 may be made of an organic material. For example, the material of the buffer layer 5 may be hexamethyldisiloxane, epoxy resin, or Polyimide (PI), or may be other organic materials with slightly higher impact strength, which is not limited in this embodiment.
When the substrate 1 adopts a double-layer substrate 1 structure, the substrate 1 may specifically include a first substrate 1, a first water and oxygen barrier layer 12, a second substrate 13, and a second water and oxygen barrier layer 14, which are stacked, and the shielding layer 3 may be disposed between the second water and oxygen barrier layer 14 and the buffer layer 5.
Referring to fig. 3 to 5, fig. 3 is a film structure diagram of an array substrate according to an embodiment of the invention; FIG. 4 is a schematic circuit diagram provided by an embodiment of the present invention; fig. 5 is a schematic circuit diagram according to another embodiment of the present invention.
In some alternative embodiments, the array layer 2 includes an active layer 21, a gate layer 22, a first source drain layer 23, and a second source drain layer 24, which are stacked in the thickness direction of the array substrate; the signal wiring layer and at least one of the gate layer 22, the first source drain layer 23, and the second source drain layer 24 are disposed in the same layer.
It can be understood that at least one of the signal routing layer and the gate layer 22, the first source drain layer 23, and the second source drain layer 24 are disposed in the same layer, that is, at least one of the signal routing layer and the gate layer 22, the first source drain layer 23, and the second source drain layer 24 are formed together by the same process, and the signal routing layer and the gate layer 22, the first source drain layer 23, and the second source drain layer 24 are made of the same material, so as to reduce the production cost and the production process.
Because the signal routing layer includes the first signal line 4, when the signal routing layer and the gate layer 22, the first source drain layer 23, and the second source drain layer 24, or two or three of them, are disposed in the same layer, the first signal lines 4 located in different layers are disposed in parallel, and according to the series-parallel resistance rule, the more the first signal lines 4 connected in parallel, the smaller the total impedance of the first signal lines 4 is, the two layers of the first signal lines 4 are disposed in parallel as shown in fig. 4, and the three layers of the first signal lines 4 are disposed in parallel as shown in fig. 5.
Referring to fig. 3 and fig. 5, in this embodiment, the signal routing layer and the first source/drain layer 23 and the second source/drain layer 24 may be disposed in the same layer, that is, the first signal line 4 in the same layer as the first source/drain layer 23 and the second source/drain layer 24, the first signal line 4 in the shielding layer 3, and the first signal lines 4 in three layers in total are connected in parallel, so as to further reduce the total impedance of the first signal line 4.
In order to realize the connection between the first signal lines 4 in different layers, in some alternative embodiments, an insulating layer is disposed between two adjacent layers of the active layer 21, the gate layer 22, the first source drain layer 23, and the second source drain layer 24; the first source drain electrode layer 23 and the second source drain electrode layer 24 are provided with signal wiring layers on the same layer, and the first signal lines 4 on the signal wiring layers on different layers and the first signal lines 4 on the shielding layer 3 are connected in parallel through via holes penetrating through the insulating layer.
It should be noted that the insulating layer may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, so as to avoid the problems of short circuit and the like between the active layer 21, the gate layer 22, the first source drain layer 23, and the second source drain layer 24.
In this embodiment, the first signal lines 4 on the signal routing layers of different layers and the first signal lines 4 on the shielding layer 3 are connected in parallel through via holes penetrating through the insulating layer, where it should be noted that the connection through the via holes specifically means that via holes are formed between the first signal lines 4 on different layers through processes such as etching, and conductive connection lines need to be formed in the via holes, and the connection lines may be formed together with the adjacent first signal lines 4, or may be formed separately, and are not particularly limited.
In some alternative embodiments, the array layer 2 comprises drive transistors, and the orthographic projection of the shield layer 3 on the substrate 1 covers the orthographic projection of the drive transistors on the substrate 1.
It is understood that, after the driving transistor of the array layer 2 is exposed to external charges or external light, the electrical property of the driving transistor may change, for example, after the active layer 21 of the driving transistor is exposed to external light, photo-generated carriers may be generated back in the channel of the active layer 21, and the generation of the photo-generated carriers may affect the electrical characteristics of the driving transistor, such as leakage current when the driving transistor is turned off. Or, the driving transistor is affected by external charges, which may cause the display panel to generate phenomena such as rubbing of copper bars, greenness, short image, and the like.
Alternatively, the shielding layer 3 may be made of a light-impermeable material such as metal, for example, molybdenum.
In some alternative embodiments, the driving transistors include a first driving transistor T1 and a second driving transistor T2, one of the first driving transistor T1 and the second driving transistor T2 is a low temperature polysilicon transistor, and the other is an indium gallium zinc oxide transistor.
It should be noted that the array substrate provided in the embodiment of the invention may be an LTPO (Low Temperature Polycrystalline Oxide) array substrate, which includes an LTPS (Low Temperature Polycrystalline Silicon) transistor and an IGZO (indium gallium zinc Oxide) transistor, that is, the first driving transistor T1 and the second driving transistor T2 in the embodiment of the invention, and the shielding layer 3 is disposed to shield the first driving transistor T1 and the second driving transistor T2, so as to prevent the charges of the substrate 1 layer from entering the array layer 2 and affecting the electrical properties of the first driving transistor T1 and the second driving transistor T2.
In some alternative embodiments, the first signal line 4 is a high-level voltage signal line or a low-level voltage signal line, that is, the first signal line 4 may be VDD (high-level voltage signal line) or VSS (low-level voltage signal line), and both the VDD signal line and the VSS signal line have one end connected to the control chip and the other end electrically connected to at least one of the light emitting unit 6 and the driving transistor to transmit a voltage signal to the light emitting unit 6 or the driving transistor.
In some alternative embodiments, the shielding layer 3 includes at least one metal layer to facilitate signal transmission in which the shielding layer 3 is multiplexed as a partial region of the first signal line 4. Optionally, the shielding layer 3 includes a copper metal layer, and may also be other metals, such as silver, molybdenum, and other metals with good conductivity; alternatively, the shielding layer 3 includes a titanium aluminum titanium composite metal layer, and is not particularly limited.
An embodiment of the present invention further provides a display panel, including: the array substrate is the array substrate in any one of the embodiments.
Optionally, the display panel further includes a control chip and a light emitting layer disposed on one side of the array substrate, the light emitting layer includes a light emitting unit 6, and the array layer 2 includes a driving transistor electrically connected to the light emitting unit 6; one end of the first signal line 4 is electrically connected to the control chip, and the other end is electrically connected to at least one of the light emitting unit 6 and the driving transistor. The control chip provides voltage signals to the light-emitting unit 6 and the driving transistor through the first signal line 4, and then controls the light-emitting display of the display panel. Alternatively, the light emitting unit 6 includes an anode layer, a light emitting material layer, and a cathode layer, which are stacked.
The display panel provided by the embodiment of the present invention has the technical effects of the technical solutions of the substrates in any of the embodiments, and the structures and terms identical to or corresponding to those in the embodiments are not repeated herein.
The display panel provided by the embodiment of the invention can be applied to a mobile phone and can also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.
As will be apparent to those skilled in the art, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
Claims (10)
1. An array substrate, comprising:
a substrate;
the array layer is arranged on one side of the substrate and comprises at least one signal wiring layer, and the signal wiring layer comprises a first signal wire;
the shielding layer is arranged between the substrate and the array layer, at least partial region of the shielding layer is multiplexed into the first signal line, and the first signal line of the shielding layer is connected with the first signal line of the signal routing layer in parallel.
2. The array substrate of claim 1, further comprising a buffer layer disposed between the substrate and the array layer, wherein the shielding layer and the buffer layer are disposed on the same layer;
or, the shielding layer is arranged between the substrate and the buffer layer.
3. The array substrate of claim 2, wherein the substrate comprises a first substrate, a first water and oxygen barrier layer, a second substrate, and a second water and oxygen barrier layer stacked on one another, and the shielding layer is disposed between the second water and oxygen barrier layer and the buffer layer.
4. The array substrate according to claim 1, wherein the array layer comprises an active layer, a gate layer, a first source drain layer and a second source drain layer which are stacked in a thickness direction of the array substrate;
the signal wiring layer and at least one of the gate layer, the first source drain layer and the second source drain layer are arranged on the same layer.
5. The array substrate according to claim 4, wherein an insulating layer is disposed between two adjacent layers of the active layer, the gate layer, the first source drain layer and the second source drain layer;
the same layer of the first source drain layer and the second source drain layer is provided with the signal wiring layer, and the first signal wire of the signal wiring layer and the first signal wire of the shielding layer are connected in parallel through a through hole penetrating through the insulating layer.
6. The array substrate of claim 1, wherein the array layer comprises a driving transistor, and an orthographic projection of the shielding layer on the substrate covers an orthographic projection of the driving transistor on the substrate;
preferably, the driving transistor includes a first driving transistor and a second driving transistor, one of the first driving transistor and the second driving transistor is a low temperature polysilicon transistor, and the other is an indium gallium zinc oxide transistor.
7. The array substrate of claim 1, wherein the first signal line is a high level voltage signal line or a low level voltage signal line.
8. The array substrate of claim 1, wherein the shielding layer comprises at least one metal layer;
preferably, the shielding layer comprises a copper metal layer; or the like, or, alternatively,
the shielding layer comprises a titanium-aluminum-titanium composite metal layer.
9. A display panel, comprising:
an array substrate according to any one of claims 1 to 8.
10. The display panel according to claim 9, wherein the display panel further comprises a control chip and a light emitting layer provided on one side of the array substrate, the light emitting layer includes a light emitting unit, and the array layer includes a driving transistor electrically connected to the light emitting unit;
one end of the first signal line is electrically connected to the control chip, and the other end is electrically connected to at least one of the light emitting unit and the driving transistor.
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