CN1149185A - Method and device for extending memory - Google Patents
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Abstract
A method for extending memory space features that the memory space can be elastically extended without any additional decoder circuit or changes in application circuit. The data stored in the extended memory space can be accessed as well.
Description
The present invention relates to a kind of data access method and device, relate in particular to a kind of extending method and device of storage space.
Traditional mode in order to the access memory data has two kinds, and a kind of is string type, and another kind is a parallel type.
Be example with the serial mode reading memory data now, see also Fig. 1, it is traditional circuit block diagram with the serial mode reading memory data, comprising: an input register 11, a decoding storage unit 12 and an output register 13.Wherein, the data storing of desiring to read is in decode stored unit 12, and this input register 11, this decoding storage unit 12 and this output register 13 are positioned within the same IC packing 10, and this IC packing 10 has pin (pin) AIN, DOUT, CLK and CS.
Fig. 2 is sequential signal figure in Fig. 1, below cooperate Fig. 1,2 illustrate the action of reading of string type: when this pin CS is LOW (low), the circuit that is positioned at this IC10 is enabled, this pin CLK is then in order to the receive clock pulse signal, this pin AIN is then in order to the receiver address signal, suppose that these decode stored unit 12 each group addresss are 14, then this pin AIN receives 14 address signal A0-A13 successively with each one serial mode, and also receiver address signal A0-A13 in regular turn of this input register 11, after treating that address signal A0-A13 accepts to finish fully, OPADD signal A0-A13 is to this decoding storage unit 12 again; Certainly, this decoding storage unit 12 is behind receiver address signal A0-A13, just with its decoding and export data D0-D7 that correspondence is positioned at address A0-A13 simultaneously to this output register 13, and this output register 13 is exported with a serial mode of one D0-D7 again from this pin DOUT.
String type reads the advantage of mode, be that the interface circuit that reads this decoding storage unit 12 only needs an address pin and a data output pin, therefore, when the memory span of decoding storage unit 12 is expanded, as long as increase the figure place (being external a plurality of identical IC packing 10) of Input Address, must not change the pin number that IC packs 10 inner packagings.
Yet, when the memory span of using surpasses maximum single memory capacity, except that external a plurality of identical IC packings 10, still need to cooperate and increase the external decoder circuit, in order to distinguish the storage space of a plurality of the same memory capacity, this situation promptly as shown in Figure 3, Fig. 3 is the block schematic diagram that expands with serial memory, among Fig. 3, one string type extended storage 30 comprises four single serial memory 31-34, wherein, any serial memory in these four single serial memories comprises pin (pin) AIN1-AIN4 respectively, DOUT1-DOUT4, among CLK1-CLK4 and the CS1-CS4 any one; Certainly, this serial memory 30 also has AIN, DOUT, CLK and CS.
Because this expansion of Fig. 3, so except that need increase by one group 2 pairs 4 demoders 35, still needing increases extra two signal line EXT0 and EXT1, can predict simultaneously, as desire to be extended for bigger storage space, then certainly will increase many group demoders and extra signal wire again, thus, will increase the complexity of integrated circuit.
Again, be example with the parallel mode reading memory data again, see also Fig. 4, Fig. 4 is traditional circuit block diagram with the parallel type reading memory data.Fig. 4 has represented decoding storage unit 4, be with Fig. 1 difference, Fig. 4 imports 14 address signal the pin of one decoding storage unit 4 simultaneously, 14 address signal A0-A13 exports after by 4 decodings of this decoding storage unit more simultaneously to data that should address signal A0-A13, therefore, this decoding storage unit 4 must possess 14 addresses and receive pin PA0-PA13, and 8 data output pin PD0-PD7, in addition, this decoding storage unit 4 has also comprised a wafer selection pin CS and an output enable pin OE.Fig. 5 has then represented the clock signal of each pin of Fig. 4 circuit.
The advantage that parallel type reads is: address of each and data are all received or output by corresponding pin, therefore read once get final product complete data, reading rate is fast.
Right its shortcoming is that the pin in the single wafer is too much, and it is big to form packing cost; In addition, outside controller in order to control decoding storage unit 4 must provide the pin position of equal number to control these addresses and data pin, has taken the control pin of too much controller; In addition, in case when this decoding storage unit 4 was expanded, the number of pins of whole this decoding storage unit 4 obviously increased, the essential redesign of the layout of the control system of its outer peripheral, this situation sees also the 6th figure, and Fig. 6 is the block schematic diagram that expands with the parallel type storer; Among Fig. 6, one parallel type extended storage 60 comprises four single serial memory 61-64, wherein, any serial memory in these four single parallel type storeies comprises any one among pin (pin) A01-A04, A11-A14, A21-A24, A31-A34, A41-A44, A51-A54, WR1-WR4 and the CS1-CS4 respectively; Certainly, this parallel type storer 60 also has A0--A5, WR and CS.
In like manner, because this expansion of Fig. 6, so except that need increase by one group 2 pairs 4 demoders 65, still needing increases extra two signal line A6 and A7, can predict simultaneously, as desire to be extended for bigger storage space, then certainly will increase many group demoders and extra signal wire again, thus, also will increase the complexity of integrated circuit.
Fundamental purpose of the present invention is to provide a kind of extending method and device of storage space, can need not to increase under any situation that adds the decoding circuit, promotes the expansion elasticity of storage space and the storage data in access memory space at random.
The invention relates to a kind of extending method of storage space, its step comprises: a) provide one to have the storage space in plural groups quantum memory space; Wherein, arbitrary group of quantum memory space in this plural groups quantum memory space can supply access plural groups storage data; B) set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary; C) input one access address; D) this access address and this plural groups substrate address are carried out a difference computing respectively, to obtain this plural groups arithmetic address result; And e) one group of arithmetic address result in this plural groups arithmetic address result be positioned at during the space address in this group quantum memory space of correspondence, deposit a storage data in and to this group quantum memory space or certainly read this storage data in this group quantum memory space.
Certainly, wherein in this step (a) the big I of the wantonly two groups storage space in this plural groups quantum memory space equate.
Certainly, wherein in this step (a) the big I in the wantonly two groups of quantum memory spaces in this plural groups quantum memory space unequal.
Certainly, wherein in this step (b) first group of substrate address in this plural groups substrate address can be the start address of this storage space.
Certainly, arbitrary group of substrate address between second group of substrate address in this plural groups substrate address to this plural groups substrate address wherein, can be before this arbitrary group of substrate address one group of substrate address and this last group of substrate address the sum total of whole space address in corresponding quantum memory space.
Certainly, wherein this difference computing in this step (d) refers to a subtraction.
Certainly, wherein in this step (e) one group of arithmetic address result among so-called this plural groups arithmetic address result be positioned at the space address in this group quantum memory space of correspondence, be meant the start address of this group arithmetic address result, and be less than or equal to the termination address in this group quantum memory space more than or equal to this group quantum memory space.
The invention provides a kind of extending method of storage space, its step comprises: a) provide one to have the storage space in plural groups quantum memory space; Wherein, arbitrary group of quantum memory space in this plural groups quantum memory space can supply access plural groups storage data; B) set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary; C) input one access address; Wherein, this access address has a low level and high-order access address; D) this low level access address is exported to this place, plural groups quantum memory space; E) should high position access address and the high-order substrate of this plural groups address carry out a difference computing respectively, to obtain the high-order arithmetic address result of this plural groups; And (f) one of in the high-order arithmetic address result of this plural groups the high-order arithmetic address result of group and the address combination of this low level access address be positioned at during the space address in corresponding this group quantum memory space, deposit a storage data in and to this group quantum memory space or certainly read this storage data in this group quantum memory space.
The invention provides a kind of expanding device of storage space, it has the plural groups access device and is electrically connected on one of this plural groups access device access address end, an access data end and an access selecting side; Wherein, a storage space has plural groups quantum memory space, and this plural groups quantum memory space is electrically connected on this plural groups access device respectively; Arbitrary group of access device in this plural groups access device comprises; One substrate address storage device, it stores a substrate address in order to input; One difference computing comparison means, be electrically connected on the quantum memory space that this substrate address storage device, this access address end and this arbitrary group of access device are electrically connected, this difference computing comparison means will be in order to will one of importing the access address and a difference computing is carried out in this substrate address from this access address end, when being positioned at definitely the location scope with arithmetic address result when gained, export this arithmetic address result to this place, group quantum memory space, and produce output one access data enable signal; An and data buffer device, be electrically connected on this difference computing comparison means, this group quantum memory space, this access data end and this access selecting side, this data buffer device in order to respond this access data enable signal and certainly this access selecting side one of import access and select signal, and this access data end deposits a storage data in to this group quantum memory space or read this storage data to this access data end place in this group quantum memory space certainly certainly.
Certainly, wherein this substrate address storage device can be a substrate address register.
Certainly, wherein this difference computing comparison means can comprise a subtracter and comparer.
Certainly, wherein this difference computing can be a subtraction.
Certainly, wherein this certain address realm is meant the space address in the quantum memory space that this group is electrically connected.
Certainly, arithmetic address result that wherein should the what is called gained is positioned at the space address in the quantum memory space that this group is electrically connected, be meant the start address of this arithmetic address result, and be less than or equal to the termination address in this group quantum memory space more than or equal to this group quantum memory space.
Certainly, wherein this data buffer device can be a two-way data buffer device.
Certainly, wherein this arbitrary group of access device more can comprise an address buffer device, be electrically connected on this access address end and this difference computing comparison means, this address buffer device can be in order to being received from this access address that this access address end is imported, and exported in this difference computing comparison means.
Certainly, wherein this arbitrary group of access device more can comprise an address buffer device, be electrically connected on this group quantum memory space that this access address end, this difference computing comparison means are electrically connected with this access device, this address buffer device can be in order to be received from this access address that this access address end is imported, and exported the low level access address in this access address to this place, group quantum memory space, the high-order access address in this access address is then exported in this difference computing comparison means.
Certainly, wherein this certain address realm is meant the high-order space address in the quantum memory space that this group is electrically connected.
Certainly, arithmetic address result that wherein should the what is called gained is positioned at the high-order space address in the quantum memory space that this group is electrically connected, be meant the reference position of this arithmetic address result, and be less than or equal to the termination address of high bit space in this group quantum memory more than or equal to high bit space in this group quantum memory.
Certainly, wherein the quantum memory space that is electrically connected with this arbitrary group of access device of this arbitrary group of access device can be located in the integrated circuit (IC).
Below with reference to drawings and Examples storage space extending method of the present invention and device are described in further detail.
Fig. 1 is traditional circuit block diagram with the serial mode reading memory data;
Fig. 2 is the sequential chart of the interface pin of Fig. 1 circuit.
The block schematic diagram of Fig. 3 for expanding with serial memory.
Fig. 4 is traditional circuit block diagram with the parallel mode reading memory data.
Fig. 5 is the sequential chart of the interface pin of Fig. 4 circuit.
The block schematic diagram of Fig. 6 for expanding with the parallel type storer.
Fig. 7 is that notion of the present invention is implemented synoptic diagram.
Fig. 8 is the schematic flow sheet of one of the method for the invention preferred embodiment.
Fig. 9 is the schematic flow sheet of another preferred embodiment of the method for the invention.
Figure 10 (a) is the block schematic diagram of one of device of the present invention preferred embodiment.
The synoptic diagram of an integrated circuit (IC) is located in the quantum memory space that Figure 10 (b) is electrically connected with this arbitrary group of access device for this arbitrary group of access device in one of the device of the present invention preferred embodiment together.
Figure 11 (a) is the block schematic diagram of another preferred embodiment of device of the present invention.
The synoptic diagram of an integrated circuit (IC) is located in the quantum memory space that Figure 11 (b) is electrically connected with this arbitrary group of access device for this arbitrary group of access device in another preferred embodiment of device of the present invention together.
Figure 12 is for being the application exemplary plot that the example application implementation is extended for 4K byte (bytes) storage space with the structure shown in Figure 10 (b).
Figure 13 is for being the application exemplary plot that the example application implementation is extended for 4K byte (bytes) storage space with the structure shown in Figure 11 (b).
See also Fig. 7, it is that notion of the present invention is implemented synoptic diagram, and among Fig. 7, the arbitrary quantum memory space in the n+1 group quantum memory element all only occupies the subregion of storage space (m).In case when having an outside Input Address between substrate address 2 and substrate address 3, should have only selected quantum memory element (2) (this substrate address 2 is the corresponding substrate addresses of its institute) to enable and wherein import/go out certainly a storage values; In like manner, when this outside Input Address is between substrate address n and substrate address n+1, then should only there be selected quantum memory element (n) (this substrate address n is the corresponding substrate address of its institute) to enable and wherein import/go out certainly another storage values; Certainly, this storage values or the physical holding of the stock address of this another storage values in real memory determine according to following relationship:
This storage values or the physical holding of the stock address of this another storage values in actual storage:
=this outside Input Address-corresponding substrate address of chosen quantum memory element institute
The present invention is when this n+1 group quantum memory element is made, be about to deposit in respectively wherein with respect to the substrate address of this n+1 group quantum memory element, decide this outside Input Address respectively in its sole discretion for this n+1 group quantum memory element and whether fall within quantum memory space own, judge according to this that more whether the quantum memory space in the chosen quantum memory element enables, and the access storage data.
For further disclosing content of the present invention, now enumerate some preferred embodiments and be illustrated.
See also Fig. 8, it is the schematic flow sheet of one of the method for the invention preferred embodiment, and it comprises:
A1: beginning;
A2: provide one to have the storage space in plural groups quantum memory space; Wherein, but the equal access plural groups storage data in arbitrary group of quantum memory space in this plural groups quantum memory space; Wherein, the big I in the wantonly two groups of quantum memory spaces in this plural groups quantum memory space equates that certainly, the size in these wantonly two groups of quantum memory spaces also can be unequal;
A3: set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary; Wherein, first group of substrate address in this plural groups substrate address can be the start address of this storage space, and arbitrary group of substrate address between second group of substrate address in this plural groups substrate address to this plural groups substrate address wherein, can be before this arbitrary group of substrate address one group of substrate address and this last group of substrate address the sum total of whole space address in corresponding quantum memory space;
A4: import an access address;
A5: this access address and this plural groups substrate address are carried out a subtraction respectively, to obtain this plural groups arithmetic address result;
A6: one group of arithmetic address result in this plural groups arithmetic address result is more than or equal to the start address in this group quantum memory space, and the termination address that is less than or equal to this group quantum memory space deposits a storage data in and to this group quantum memory space or certainly reads this storage data in this group quantum memory space; And
A7: finish.
See also Fig. 9 again, it is the schematic flow sheet of another preferred embodiment of the method for the invention, and it comprises:
B1: beginning;
B2: provide one to have the storage space in plural groups quantum memory space; Wherein, but arbitrary group of quantum memory space access plural groups storage data in this plural groups quantum memory space;
B3: set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary;
B4: import an access address; Wherein this access address has the access address of a low level and a high position;
B5: export this low level access address to this place, plural groups quantum memory space;
B6: the high-order access address and the high-order substrate of this plural groups address of this access address are carried out a difference computing respectively, to obtain the high-order arithmetic address result of this plural groups;
B7: when one group of high-order arithmetic address result among the high-order arithmetic address result of this plural groups and the address combination of the low level substrate address of this access address be positioned at during the space address in corresponding this group quantum memory space, deposit a storage data in and to this group quantum memory space or certainly read this storage data in this group quantum memory space; And
B8: finish.
Now see also Figure 10 (a) again, it is the block schematic diagram of a preferred embodiment of device of the present invention, in Figure 10 (a), a kind of expanding device 101 of storage space comprises: plural groups access device E0-En, an access address end 1011, an access data end 1012 and an access selecting side 1013; One storage space 102 then comprises plural groups quantum memory space M 0-Mn, and this plural groups quantum memory space M 0-Mn start address and termination address separately should be respectively M01-Mn1 and M0m-Mnm; Certainly, this plural groups access device E0-En comprises respectively: any one among a substrate address storage device E01-En1, an address buffer device E02-En2, a difference computing comparison means E03-En3 and the data buffer device E04-En4; Certainly, this substrate address storage device E01-En1 all can be respectively a substrate address register, and this difference computing comparison means E03-En3 all can comprise a subtracter and comparer (not shown) respectively, to carry out a subtraction and a comparison operation; And this data buffer device E04-En4 can be all a two-way data buffer device.
The preferably, the plural groups quantum memory space M 0-Mn that this plural groups access device E0-En can be electrically connected with this plural groups access device E0-En respectively is with being located in the integrated circuit (IC), this situation can be consulted Figure 10 (b), and it is located at the synoptic diagram of an integrated circuit (IC) together for the quantum memory space M 0-Mn that is electrically connected respectively with this institute among this plural groups access device E0-En in one of the device of the present invention preferred embodiment; Certainly, in Figure 10 (b), be the synoptic diagram that can form integrated circuit (IC) zone by the device that dotted line covered of label 1030-103n.
See also Figure 10 (a) again, wherein, the principle of work of arbitrary group of access device among this plural groups access device E0-En is an example with this group access device E0 now for convenience of description; Wherein, comprise among this group access device E0: this address buffer device E01, this substrate address storage device E02, this difference computing comparison means E03 and this data buffer device E04; And this group access device E0 is electrically connected on this group quantum memory space M 0, with a storage data that will be positioned at this access data end 1012 input to this group quantum memory space M 0 or certainly this group quantum memory space M 0 read this storage data to this access data end 1012.
Simultaneously, one substrate address is imported in the high voltage mode in advance and is stored among the storage device E02 of this substrate address, afterwards, import an access address to this address buffer device E01 from these access address end 1011 places, E03 carries out a subtraction with this access address and this substrate address for this difference computing comparison means, and, when being positioned at definitely the location scope as the arithmetic address result of gained, export this arithmetic address result to this group quantum memory space M 0 place, and produce output one access data enable signal E05 to this data buffer device E04; At this moment, this data buffer device E04, promptly in order to respond this access data enable signal E05 and certainly this access selecting side 1013 one of import access and select signal, and this access data end 1012 deposits a storage data in to this group quantum memory space M 0 or read this storage data to these access data end 1012 places in this group quantum memory space M 0 certainly certainly.
Wherein, the arithmetic address result of aforementioned so-called gained is positioned at definitely that the location scope means the start address M01 of this arithmetic address result more than or equal to this group quantum memory space M 0, and is less than or equal to the termination address M0m of this group quantum memory space M 0.
Certainly, the circuit working principle of all the other this access device E1-En also is equal to this access device E0; Thus, according to aforementioned explanation at notion enforcement of the present invention shown in Figure 7, only there is one group of quantum memory space to be enabled when understanding in this plural groups quantum memory space M 0-Mn, and import in the quantum memory space that this group is enabled certainly/go out to correspond to one of this access address storage data, only can finish the expansion of memory span and the work of access fast with easy circuit operation.
Certainly, be the circuit of simplifying this difference computing comparison means E03-En3 and the speed of quickening this difference computing, another preferred embodiment of device of the present invention graphic sees also Figure 11 (a), and it is the block schematic diagram of another preferred embodiment of the described device of this case; In Figure 11 (a), the expanding device 111 of another kind of storage space comprises: plural groups access device F0-Fn, an access address end 1111, an access data end 1112 and an access selecting side 1113; Wherein, the expanding device 111 of this storage space also is applied to access this storage space 102 as shown in Figure 10 (a).
Certainly, wherein internal structure, this access address end 1111, this access data end 1112 and this access selecting side 1113 of any one among this substrate address storage device F01-Fn1, an address buffer device F02-Fn2 and the data buffer device F04-Fn4, be equal among this substrate address storage device E01-En1, this address buffer device E02-En2 among Figure 10 (a) and this data buffer device E04-En4 any one internal structure, this access address end 1011, this access data end 1012 and this access selecting side 1013 respectively, promptly no longer given unnecessary details at this.
Yet the main difference of Figure 11 (a) and Figure 10 (a) is this access address that this address buffer device F02-Fn2 is exported among Figure 11 (a), is to distinguish the low level access address L that is output as in this access address and the high-order access address H in this access address; Wherein, this address buffer device F02-Fn2 can be in order to be received from this access address that this access address end 1111 is imported, and exported this low level access address L to this group quantum memory space M 0-Mn place, should then be exported among this difference computing comparison means F03-Fn3 by high position access address H.
Certainly, as group arithmetic address result one of among each arithmetic address result of this difference computing comparison means F03-Fn3 gained, it is the high-order space address that is positioned at the quantum memory space that this group is electrically connected, promptly should organize the start address of the address combination of arithmetic address result and this low level access address L more than or equal to high bit space in this group quantum memory, and when being less than or equal to the termination address of high bit space in this group quantum memory, obviously, can deposit a storage data in to this group quantum memory space or read this storage data to these access data end 1112 places in this group quantum memory space certainly from this access data end 1112.
In like manner, the preferably, the plural groups quantum memory space M 0-Mn that this plural groups access device F0-Fn can be electrically connected with this plural groups access device F0-Fn respectively is with being located in the integrated circuit (IC), this situation can see also Figure 11 (b), it is in another preferred embodiment of device of the present invention, and the quantum memory space M 0-Mn that is electrically connected respectively with this institute among this plural groups access device F0-Fn is with the synoptic diagram of being located at an integrated circuit (IC); Certainly, be the synoptic diagram that can form integrated circuit (IC) zone by the device that dotted line covered of label 1120-112n among Figure 11 (b).
At last, principle of work of the present invention is easier to be understood by the people in order to make, and existing Figure 10 (b) and the structure shown in Figure 11 (b) utilized respectively is with the quantum memory space of 1K byte, desire expands the example of finishing 4K bytes of memory device space and does an explanation, so that further disclose spirit of the present invention.
See also Figure 12, it is to be extended for the application exemplary plot in 4K byte memory space with the structure shown in Figure 10 (b) (wherein, each quantum memory space M 0-M3 is an example with the 1K byte all) application implementation; And please cooperate and consult Figure 10 (b).
At first, the right of among this each quantum memory space M 0-M3 any one all indicates 000H-3FFH, represent a relative address (because of this each quantum memory space M 0-M3 is an example with the 1K byte all), indicate 000H-FFFH person altogether as for this quantum memory space M 0 certainly to the left side of this quantum memory space M 3, represented a specific address (because of this each quantum memory space M 0-M3 amounts to the 4K byte).
So this each corresponding substrate address of quantum memory space M 0-M3 promptly is respectively 000H, 400H, 800H and COOH, and these substrate addresses should be input to respectively among this substrate address storage device E02, the E32; If if this access address that this moment, this access address 1012 was imported is 600H, then the address arithmetic result of this difference computing comparison means E03-E33 is respectively:
(a) about indicating 1030 IC:
600H (this access address)-000H (storage values of this substrate address storage device E02)=600H, the address arithmetic result of right this 600H is obviously greater than the memory span (000H-3FFH of this quantum memory space M 0, the 1K byte), so this access data enable signal obviously is in disabled state, and this quantum memory space M 0 can't be carried out the action of access storage data;
(b) about indicating 1031 IC:
600H (this access address)-400H (storage values of this substrate address storage device E12)=200H, the address arithmetic result of this 200H obviously is positioned at the memory span of this quantum memory space M 1, so this access data enable signal obviously is in enabled state, and this quantum memory space M 1 address arithmetic result of 200H according to this carries out the action of access storage data (indicating DATA person) in this quantum memory space M 1;
(c) about indicating 1032 IC:
600H (this access address)-800H (storage values of this substrate address storage device E22)=-200H, right this-the address arithmetic result of 200H is negative value (illegal), obviously, this access address does not fall within the memory address range of this storage space M2, so this access data enable signal obviously is in disabled state, and this quantum memory space M 2 can't be carried out the action of access storage data; And
(d) about the IC of label 1033:
600H (this access address)-C00H (storage values of this substrate address storage device E32)=-600H, right this-the address arithmetic result of 600H is negative value (illegal), obviously, this access address does not fall within the memory address range of this storage space M3, so this access data enable signal obviously is in disabled state, and this quantum memory space M 3 can't be carried out the action of access storage data.
See also Figure 13 again, it is to be extended for the application exemplary plot in 4K byte memory space with the structure shown in Figure 11 (b) (wherein, each quantum memory M0--M3 is an example with the 1K byte all) application implementation; And please cooperate and consult Figure 11 (b).
With shown in Figure 12, the right of among this each quantum memory space M 0-M3 any one all indicates 000H-3FFH, represent a relative address, indicated 000H-FFFH person altogether, represent a specific address as for this quantum memory space M 0 certainly to the left side of this quantum memory space M 3.
If if this address buffer device F01-F31 is all 8, then the low level access address of this access address is 8; Amount to 4K byte (being 12) because of this quantum memory space M 0-M3 respectively again, therefore, the high-order access address of this access address is 4 (12 subtract 8) position.
Therefore, this each corresponding substrate address of quantum memory space M 0-M3 promptly is respectively 0H, 4H, 8H and CH, and these substrate addresses should input to respectively among the storage device F02-F32 of this substrate address; If if this access address that this moment, this access address 1012 was imported is 600H, then this low level access address among this address buffer device F01-F31 is all 00H, and exported to respectively respectively among this quantum memory space M 0-M3, be all 6H as for this high position access address among this address buffer device F01-F31; Therefore, the address arithmetic result of this difference computing comparison means F03-F33 is respectively:
(a) about indicating 1120 IC:
6H (this high position access address)-0H (storage values of this substrate address storage device F02)=6H, the address arithmetic result of right this 6H is obviously greater than high-order regional memory address range (0H-3H) in this quantum memory space M 0, so this access data enable signal obviously is in disabled state, and this quantum memory space M 0 can't be carried out the action of access storage data;
(b) about indicating 1121 IC:
6H (this high position access address)-4H (storage values of this substrate address storage device F12)=2H, the address arithmetic result of this 2H obviously is arranged in the memory address range (0H-3H) in this quantum memory space M 1 high-order zone, so this access data enable signal obviously is in enabled state, and this quantum memory space M 1 address arithmetic result of 200H according to this carries out the action of access storage data (DATA) in this quantum memory space M 1;
(c) about indicating 1122 IC:
6H (this high position access address)-8H (storage values of this substrate address storage device F22)=-2H, right this-the address arithmetic result of 2H is negative value (illegal), obviously, this high position access address does not fall within the memory address range interior (0H-3H) in high-order zone among this storage space M2, so this access data enable signal obviously is in disabled state, and this quantum memory space M 2 can't be carried out the action of access storage data; And
(d) about indicating 1123 IC:
6H (this high position access address)-CH (storage values of this substrate address storage device F32)=-6H, right this-the address arithmetic result of 6H is negative value (illegal), obviously, this high position access address does not fall within the memory address range interior (0H-3H) in high-order zone among this storage space M3, so this access data enable signal obviously is in disabled state, and this quantum memory space M 3 can't be carried out the action of access storage data.
Certainly, the expansion of storer of the present invention is not limited to respectively that this quantum memory space all need have identical storage space, and in brief, the present invention also is suitable for the respectively mutually different situation of memory span in this quantum memory space.
In sum, from the present invention memory interface expand or the application of access on, the storer (comprising ROM (read-only memory) and random access memory) of actual applicable all kinds, simultaneously, also the utmost point is suitable for EPROM, EEPROM, users such as FLASH MEMORY write the application of data voluntarily; Again, because the address substrate among the present invention can write big so more range of application of the present invention; In addition, the present invention also is applicable in the application of non-storer of same addressing interface, for example, the address space of general PC interface card is set, application that if can be suitable can improve overlapping and the puzzlement that can not be shared of existing I/O address, so the present invention one has the industrial value invention.
According to design of the present invention, those skilled in the art also can make all conversion and modification to this, but they all belong to scope of the present invention.
Claims (20)
1. the extending method of a storage space is characterized in that may further comprise the steps:
A) provide one to have the storage space in plural groups quantum memory space; Wherein, arbitrary group of quantum memory space in this plural groups quantum memory space can supply access plural groups storage data;
B) set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary;
C) input one access address;
D) this access address and this plural groups substrate address are carried out a difference computing respectively, to obtain this plural groups arithmetic address result; And
E) one group of arithmetic address result in this plural groups arithmetic address result be positioned at during the space address in this group quantum memory space of correspondence, deposit a storage data in and to this group quantum memory space or certainly read this storage data in this group quantum memory space.
2. the extending method of storage space as claimed in claim 1 is characterized in that the big I in the wantonly two groups of quantum memory spaces in this plural groups quantum memory space in this step (a) equates.
3. the extending method of storage space as claimed in claim 1 is characterized in that the big I in the wantonly two groups of quantum memory spaces in this plural groups quantum memory space in this step (a) is unequal.
4. the extending method of storage space as claimed in claim 1 is characterized in that in this step (b) first group of substrate address in this plural groups substrate address can be the start address of this storage space.
5. the extending method of storage space as claimed in claim 4, it is characterized in that arbitrary group of substrate address between second group of substrate address to this plural groups substrate address in this plural groups substrate address, can be before this arbitrary group of substrate address one group of substrate address and this last group of substrate address the sum total of whole space address in corresponding quantum memory space.
6. the extending method of storage space as claimed in claim 1 is characterized in that this difference computing in this step (d) refers to a subtraction.
7. the extending method of storage space as claimed in claim 1, it is characterized in that in this step (e) one group of arithmetic address result among so-called this plural groups arithmetic address result be positioned at the space address in this group quantum memory space of correspondence, be meant the start address of this group arithmetic address result, and be less than or equal to the termination address in this group quantum memory space more than or equal to this group quantum memory space.
8. the extending method of a storage space is characterized in that may further comprise the steps:
A) provide one to have the storage space in plural groups quantum memory space; Wherein, arbitrary group of quantum memory space in this plural groups quantum memory space can supply access plural groups storage data;
B) set and this plural groups quantum memory space institute corresponding this plural groups substrate address out of the ordinary;
C) input one access address; Wherein, this access address has a low level and high-order access address;
D) this low level access address is exported to this place, plural groups quantum memory space;
E) should high position access address and the high-order substrate of this plural groups address carry out a difference computing respectively, to obtain the high-order arithmetic address result of this plural groups; And
When f) this corresponding with the address combination seat institute of this low level access address of the high-order arithmetic address result of group organized in the space address in quantum memory space one of in the high-order arithmetic address result of this plural groups, deposit a storage data in and to this group quantum memory space or certainly read this storage data in this group quantum memory space.
9. the expanding device of a storage space comprises the plural groups access device and is electrically connected on one of this plural groups access device access address end, an access data end and an access selecting side; It is characterized in that a storage space has plural groups quantum memory space, and this plural groups quantum memory space is electrically connected on this plural groups access device respectively; Arbitrary group of access device in this plural groups access device comprises:
One pedestal address storage device, it stores a substrate address in order to input;
One difference computing comparison means, be electrically connected on the quantum memory space that this substrate address storage device, this access address end and this arbitrary group of access device are electrically connected, this difference computing comparison means will be in order to will one of importing the access address and a difference computing is carried out in this substrate address from this access address end, when being positioned at definitely the location scope with arithmetic address result when gained, export this arithmetic address result to this place, group quantum memory space, and produce output one access data enable signal; And
One data buffer device, be electrically connected on this difference computing comparison means, this group quantum memory space, this access data end and this access selecting side, this data buffer device in order to respond this access data enable signal and certainly this access selecting side one of import access and select signal, and this access data end deposits a storage data in to this group quantum memory space or read this storage data to this access data end place in this group quantum memory space certainly certainly.
10. the expanding device of storage space as claimed in claim 9 is characterized in that this substrate address storage device can be a substrate address register.
11. the expanding device of storage space as claimed in claim 9 is characterized in that this difference computing comparison means can comprise a subtracter and comparer.
12. the expanding device of storage space as claimed in claim 11 is characterized in that this difference computing can be a subtraction.
13. the expanding device of storage space as claimed in claim 9 is characterized in that this certain address realm is meant the space address in the quantum memory space that this group is electrically connected.
14. the expanding device of storage space as claimed in claim 13, the arithmetic address result who it is characterized in that this what is called gained is positioned at the space address in the quantum memory space that this group is electrically connected, be meant the big son of this arithmetic address result or equal the start address in this group quantum memory space, and be less than or equal to the termination address in this group quantum memory space.
15. the expanding device of storage space as claimed in claim 9 is characterized in that this data buffer device can be a two-way data buffer device.
16. the expanding device of storage space as claimed in claim 9, it is characterized in that this arbitrary group of access device more can comprise an address buffer device, be electrically connected on this access address end and this difference computing comparison means, this address buffer device can be in order to being received from this access address that this access address end is imported, and exported in this difference computing comparison means.
17. the expanding device of storage space as claimed in claim 9, it is characterized in that this arbitrary group of access device more can comprise an address buffer device, be electrically connected on this access address end, this group quantum memory space that this difference computing comparison means is electrically connected with this access device, this address buffer device can be in order to accept this access address from this access address end is imported, and exported the low level access address in this access address to this place, group quantum memory space, the high-order access address in this access address is then exported in this difference computing comparison means.
18. the expanding device of storage space as claimed in claim 17 is characterized in that this certain address realm is meant the high-order space address in the quantum memory space that this group is electrically connected.
19. the expanding device of storage space as claimed in claim 18, the arithmetic address result who it is characterized in that this what is called gained is positioned at the high-order space address in the quantum memory space that this group is electrically connected, be meant the big son of this arithmetic address result or equal the start address of high bit space in this group quantum memory, and be less than or equal to the termination address of high bit space in this group quantum memory.
20. the expanding device of storage space as claimed in claim 9 is characterized in that the quantum memory space that this arbitrary group of access device is electrically connected with this arbitrary group of access device can be located in the integrated circuit (IC).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95116772 CN1149185A (en) | 1995-10-13 | 1995-10-13 | Method and device for extending memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95116772 CN1149185A (en) | 1995-10-13 | 1995-10-13 | Method and device for extending memory |
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| CN1149185A true CN1149185A (en) | 1997-05-07 |
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|---|---|---|---|
| CN 95116772 Pending CN1149185A (en) | 1995-10-13 | 1995-10-13 | Method and device for extending memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419570B (en) * | 2007-10-25 | 2012-07-04 | 晨星半导体股份有限公司 | Memory device addressing apparatus and method |
| CN103594106A (en) * | 2013-11-11 | 2014-02-19 | 无锡普雅半导体有限公司 | Serial memory chip capacity expansion structure |
| US8762683B2 (en) | 2007-10-16 | 2014-06-24 | Mstar Semiconductor, Inc. | Device and method for memory addressing |
-
1995
- 1995-10-13 CN CN 95116772 patent/CN1149185A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8762683B2 (en) | 2007-10-16 | 2014-06-24 | Mstar Semiconductor, Inc. | Device and method for memory addressing |
| CN101419570B (en) * | 2007-10-25 | 2012-07-04 | 晨星半导体股份有限公司 | Memory device addressing apparatus and method |
| CN103594106A (en) * | 2013-11-11 | 2014-02-19 | 无锡普雅半导体有限公司 | Serial memory chip capacity expansion structure |
| CN103594106B (en) * | 2013-11-11 | 2016-01-06 | 无锡普雅半导体有限公司 | A kind of serial memory chip capacity expansion structure |
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