CN114914295B - UMOS device with excellent forward and reverse conduction characteristics - Google Patents

Abstract

The invention provides a UMOS device structure with excellent forward and reverse conduction characteristics, belonging to the technical field of power semiconductor devices. The invention proposes a UMOS device with excellent forward and reverse conduction characteristics. By removing the oxide layer at the bottom of the groove gate, the shielding layer at the bottom of the groove, the drift region and the substrate form a diode structure. At the same time, the gate polysilicon has two different doping types, upper and lower, which can not only improve the switching speed in the case of forward conduction, but also serve as a diode conduction current in the reverse conduction condition. Therefore, in the case of reverse conduction, the device not only has a strong current driving capability, but also greatly reduces the reverse conduction voltage of the device due to the existence of the polysilicon diode. Therefore, on the basis of ensuring the original basic electrical performance of UMOS, the structure of the present invention effectively improves the switching speed of the device under forward conduction, and optimizes the three-quadrant characteristics of the device, which is suitable for silicon carbide devices.

Description

A UMOS device with excellent forward and reverse conduction characteristics

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a UMOS device with excellent forward and reverse conduction characteristics.

Background technique

With the continuous development of power semiconductors towards higher frequency and higher voltage applications, Si-based power devices are limited by their own material parameters, and it is difficult to further reduce device switching losses in high-frequency environments, and the operating temperature of Si-based devices cannot reach above 150°C. As the third-generation wide-bandgap semiconductor material, SiC is more suitable for high-frequency, high-voltage, and high-temperature working conditions due to its wide bandgap, high critical breakdown electric field, and large thermal conductivity.

The power SiC MOSFET device is usually used as a power switch tube for power processing in the circuit. When the SiC MOSFET is used in a bridge circuit, the device not only needs to work in the forward conduction state to play a switching role, but also needs to work as a freewheeling diode in the reverse conduction state.

Since SiC devices have a smaller cell area than Si-based devices of the same magnitude, their switching speed is very fast, but the existence of the device's own parasitic capacitance still affects the switching speed of the device, thereby increasing the switching loss of the device. Among the device parasitic capacitances, the Miller capacitance has the most obvious influence on the switching of the device. To further increase the switching speed of the device and reduce the conduction loss, reducing the Miller capacitance is an extremely effective measure.

In addition, due to the wide band gap of the SiC material, the conduction voltage drop of the parasitic body diode is about four times larger than that of the Si-based diode, resulting in a large reverse conduction loss of the device. In order to make the device have lower conduction loss and stronger current driving capability in the case of reverse conduction, integrating diodes inside the device structure is a common device-level improvement method.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to propose a UMOS device with excellent forward and reverse conduction characteristics, which can effectively reduce the Miller capacitance of the device, increase the forward switching speed of the device, and thereby reduce the conduction rate of the device. loss. In addition, the reverse conduction voltage of the device can be effectively reduced, the reverse conduction loss of the device can be reduced, and the reverse current driving capability of the device can be improved.

In order to realize the foregoing invention object, the technical scheme of the present invention is as follows:

A UMOS device with excellent forward and reverse conduction characteristics, comprising a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1, a heavily doped first conductivity type semiconductor substrate located on the heavily doped first conductivity type A lightly doped first conductivity type semiconductor body region 3 on the semiconductor substrate 2, a first conductivity type semiconductor highly doped region 8 located on the lightly doped first conductivity type semiconductor body region 3;

A highly doped second conductivity type semiconductor body region 9 located on the first conductivity type semiconductor highly doped region 8; a heavily doped first conductivity type semiconductor region immediately adjacent to the highly doped second conductivity type semiconductor body region 9 The semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12; the heavily doped first conductivity type semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12 are in the form of ohmic contact with the metal direct contact with the source electrode 14;

The upper part of the lightly doped first conductivity type semiconductor body region 3 also has a trench structure, and the upper surface of the trench is electrically isolated from the metallized source 14 through the dielectric layer 13; the side of the trench has a gate oxide layer 6. The gate oxide layer 6 is in direct contact with the sides of the first conductivity type semiconductor highly doped region 8, the highly doped second conductivity type semiconductor body region 9, and the heavily doped first conductivity type semiconductor source region 11; the highly doped The second conductive type semiconductor body region 9 close to the trench wall is a channel region; the trench is filled with a heavily doped first conductive type polysilicon gate electrode region 10 and a lightly doped second conductive type polysilicon body region 7, the The lightly doped second conductivity type polysilicon body region 7 is located under the heavily doped first conductivity type polysilicon gate electrode region 10 and directly contacts its lower surface; the lightly doped second conductivity type polysilicon body region 7 has heavily doped first The second conductivity type polysilicon source electrode region 5; the heavily doped second conductivity type polysilicon source electrode region 5 has a heavily doped second conductivity type semiconductor shielding layer 4;

The heavily doped first conductivity type polysilicon gate electrode region 10 completely covers the sides of the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to the gate potential connected; the heavily doped polysilicon source electrode region 5 of the second conductivity type realizes the potential connection with the metallized source electrode 14 through a layout design through a through hole;

The heavily doped polysilicon gate electrode region 10 of the first conductivity type completely covers the channel region, which can realize the switching performance of the semiconductor device; the heavily doped polysilicon gate electrode region 10 of the first conductivity type is connected to the gate potential; the The heavily doped polysilicon source region 5 of the second conductivity type and the metallized source 14 are connected to the source potential; when the semiconductor device works in reverse, the gate contact and the drain contact are short-circuited.

As a preferred manner, the lightly doped polysilicon body regions 7 of the second conductivity type are arranged alternately between the heavily doped polysilicon source regions 5 of the second conductivity type directly below the polysilicon body regions 7 of the lightly doped second conductivity type.

As a preferred manner, the first conductivity type is n-type, and the second conductivity type is p-type.

As a preferred manner, the first conductivity type is p-type, and the second conductivity type is n-type.

In a preferred embodiment, the semiconductor is SiC.

As a preferred manner, the doping concentration of heavy doping is greater than 1E19cm ^-3 , the doping concentration of light doping is less than 1E17cm ^-3 , and the doping concentration of high doping is between 1E19cm ^-3 and 1E17cm ^-3 .

The beneficial effect of the present invention is: a kind of UMOS device that the present invention proposes has excellent positive and negative characteristics, conventional polysilicon electrode area is made into N ⁺ P ^- P ⁺ (when the first conduction type When the semiconductor is an n-type semiconductor), the structure of the gate-source potential difference in the forward working state is used to realize the reverse bias of the polysilicon PN junction. In the case of ensuring that the gate-source electrode region of the polysilicon does not undergo punch-through breakdown, not only the polysilicon The electrical isolation between the gate-source electrode regions also reduces the overlapping area of the gate-drain, thereby reducing the Miller capacitance of the device and improving the switching speed of the device in the forward working state. In addition, the presence of the highly doped P ⁺ shielding layer (when the first conductivity type semiconductor is an n-type semiconductor) effectively protects the oxide layer at the bottom of the trench, improving the withstand voltage capability of the device. When the device works in reverse conduction, both the gate and the drain are connected to zero potential. Since the SiC parasitic body diode has a large turn-on voltage drop, the polysilicon diode is preferentially turned on to continue the circuit. When the source When the potential rises to two or three volts, the SiC body diode is turned on, and the device has a strong reverse current drive capability. In the present invention, there are two parasitic body diodes in the device, one is composed of highly doped second conductivity type semiconductor body region 9, first conductivity type semiconductor highly doped region 8, lightly doped first conductivity type semiconductor body region 3 and The parasitic body diode formed by heavily doping the semiconductor substrate 2 of the first conductivity type; the other is the heavily doped second conductivity type semiconductor shielding layer 4, the lightly doped first conductivity type semiconductor body region 3 and the heavily doped first A parasitic body diode formed by the conductivity type semiconductor substrate 2 . Therefore, in the case of reverse conduction, the entire cell area can provide a current path, which greatly alleviates the problem of device junction temperature rise caused by current concentration.

Description of drawings

Fig. 1 is a schematic structural view of a UMOS device with excellent positive and negative conduction characteristics according to Embodiment 1 of the present invention;

Fig. 2 is a schematic diagram of a part of the trench after thickening the oxide layer at the bottom of the UMOS device with excellent forward and reverse conduction characteristics in Example 1 of the present invention;

3 is an equivalent circuit diagram of a UMOS device with excellent forward and reverse conduction characteristics including parasitic capacitance and parasitic diode according to Embodiment 1 of the present invention;

4 is a schematic structural diagram of a UMOS device with excellent forward and reverse conduction characteristics according to Embodiment 2 of the present invention;

Figure 5 is a top view of the polysilicon source electrode region and the corresponding polysilicon localized view of a UMOS device with excellent forward and reverse conduction characteristics according to Example 2 of the present invention; wherein (a) is a partial top view of the polysilicon at the bottom of the groove, (b) is the overall cross-sectional view of the device along section line AA'.

6 is a plan view of another polysilicon source electrode region design and a corresponding polysilicon localized view of a UMOS device with excellent forward and reverse conduction characteristics according to Example 2 of the present invention; wherein, (a) is a partial plan view of polysilicon at the bottom of the trench , the alternating arrangement direction of the polysilicon is perpendicular to Fig. 5(a), (b) is the overall cross-sectional view of the device along the section line BB', and (c) is the overall cross-sectional view of the device along the section line CC'.

Among them, 1 is the metallized drain, 2 is the heavily doped first conductivity type semiconductor substrate, 3 is the lightly doped first conductivity type semiconductor body region, 4 is the heavily doped second conductivity type semiconductor shielding layer, and 5 is the heavily doped semiconductor body region. Doped second conductivity type polysilicon source electrode region, 6 is gate oxide layer, 7 is lightly doped second conductivity type polysilicon body region, 8 is first conductivity type semiconductor highly doped region, 9 is highly doped second conductivity type Type semiconductor body region, 10 is heavily doped first conductivity type polysilicon gate electrode region, 11 is heavily doped first conductivity type semiconductor source region, 12 is heavily doped second conductivity type semiconductor contact region, 13 is a dielectric layer, 14 is the metallized source.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Example 1

As shown in Figure 1, this embodiment provides a UMOS device with excellent forward and reverse conduction characteristics, including a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1, The lightly doped first conductivity type semiconductor body region 3 located on the heavily doped first conductivity type semiconductor substrate 2, the first conductivity type semiconductor body region 3 located on the lightly doped first conductivity type semiconductor body region 3 doped region 8;

A highly doped second conductivity type semiconductor body region 9 located on the first conductivity type semiconductor highly doped region 8; a heavily doped first conductivity type semiconductor region immediately adjacent to the highly doped second conductivity type semiconductor body region 9 The semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12; the heavily doped first conductivity type semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12 are in the form of ohmic contact with the metal direct contact with the source electrode 14;

The upper part of the lightly doped first conductivity type semiconductor body region 3 also has a trench structure, and the upper surface of the trench is electrically isolated from the metallized source 14 through the dielectric layer 13; the side of the trench has a gate oxide layer 6. The gate oxide layer 6 is in direct contact with the sides of the first conductivity type semiconductor highly doped region 8, the highly doped second conductivity type semiconductor body region 9, and the heavily doped first conductivity type semiconductor source region 11; the highly doped The second conductive type semiconductor body region 9 close to the trench wall is a channel region; the trench is filled with a heavily doped first conductive type polysilicon gate electrode region 10 and a lightly doped second conductive type polysilicon body region 7, the The lightly doped second conductivity type polysilicon body region 7 is located under the heavily doped first conductivity type polysilicon gate electrode region 10 and directly contacts its lower surface; the lightly doped second conductivity type polysilicon body region 7 has heavily doped first The second conductivity type polysilicon source electrode region 5; the heavily doped second conductivity type polysilicon source electrode region 5 has a heavily doped second conductivity type semiconductor shielding layer 4;

The heavily doped first conductivity type polysilicon gate electrode region 10 completely covers the sides of the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to the gate potential connected; the heavily doped polysilicon source electrode region 5 of the second conductivity type realizes the potential connection with the metallized source electrode 14 through a layout design through a through hole;

The heavily doped polysilicon gate electrode region 10 of the first conductivity type completely covers the channel region, which can realize the switching performance of the semiconductor device; the heavily doped polysilicon gate electrode region 10 of the first conductivity type is connected to the gate potential; the The heavily doped polysilicon source region 5 of the second conductivity type and the metallized source 14 are connected to the source potential; when the semiconductor device works in reverse, the gate contact and the drain contact are short-circuited.

The first conductivity type is n-type, and the second conductivity type is p-type.

Or the first conductivity type is p-type, and the second conductivity type is n-type.

Preferably, the semiconductor is SiC.

The doping concentration of heavy doping is greater than 1E19cm ^-3 , the doping concentration of light doping is less than 1E17cm ^-3 , and the doping concentration of high doping is between 1E19cm ^-3 and 1E17cm ^-3 .

In the above embodiment, the length of the lightly doped second conductivity type polysilicon body region should be long enough to ensure that the middle lightly doped second conductivity type polysilicon body region does not punch through when the gate-source voltage drops at both ends of the polysilicon. Breakdown, so as to ensure that the device can work normally in the forward conduction state.

Taking Embodiment 1 as an example, the working principle of the present invention is explained with the first conductivity type being n-type and the second conductivity type being p-type:

When the device works in the forward conduction condition, the heavily doped polysilicon gate electrode region 10 of the first conductivity type is connected to the gate potential, the gate is applied with a positive potential, and the metallized source 14 is connected to the heavily doped second conductivity type The polysilicon source electrode regions 5 are all connected to the ground potential, and the metallized drain 1 is connected to the high potential. The polysilicon diode formed by the heavily doped polysilicon gate electrode region of the first conductivity type and the polysilicon body region of the lightly doped second conductivity type is reverse-biased to form a PN junction self-isolation, thereby realizing the electrical isolation of the gate electrode and the source electrode. Moreover, since the polysilicon gate electrode region is connected to a positive potential, the channel region is inverted, thereby realizing the forward conduction function of the device. At the same time, due to the reverse-biased PN junction between the heavily doped polysilicon gate electrode region and the heavily doped polysilicon source electrode region, the overlapping area between the polysilicon gate electrode and the drain is reduced, thereby effectively reducing the Miller capacitance of the device. Improve the switching speed of the device and reduce the switching loss. In addition, in order to ensure the normal operation of the device in the forward conduction state, it is necessary to ensure that the polysilicon gate electrode region and the polysilicon source electrode region do not have punch-through breakdown, so the doping concentration of the lightly doped polysilicon body region should be low and have a certain width. The value can be adjusted according to the highest gate voltage applied in actual work.

When the device works in the reverse blocking condition, the polysilicon gate electrode area and the metal source are connected to the ground potential, and the metal drain is connected to the high potential. At this time, the channel is turned off, and the polysilicon diode composed of the polysilicon gate electrode region, the lightly doped polysilicon body region and the polysilicon source electrode region is zero-biased, and no conduction path appears between the gate and the source. The heavily doped semiconductor shielding layer can effectively shield the electric field of the oxide layer and effectively improve the reliability of the oxide layer of the device.

When the device works in the reverse conduction condition, the polysilicon gate electrode area and the metal drain are both connected to the ground potential, and the polysilicon source electrode area is connected to the metal source with positive potential. At this time, the polysilicon diode composed of the polysilicon gate electrode region, the lightly doped polysilicon body region and the polysilicon source electrode region is forward-biased, and it is also the first to be turned on, so the current first flows from the polysilicon source electrode region to the polysilicon gate electrode region. When the metal source and the polysilicon source electrode region When the potential on the polysilicon source electrode region rises further, the SiC body diode formed by the lightly doped first conductivity type semiconductor body region and the heavily doped second conductivity type semiconductor shielding layer and the lightly doped first conductivity type semiconductor body region and the second SiC body diodes composed of highly doped body regions of two conductivity types are all forward-conducting, as shown in FIG. 3 . Body diode1 is a body diode composed of highly doped second conductivity type semiconductor body region 9, first conductivity type semiconductor highly doped region 8 and lightly doped first conductivity type semiconductor body region 3; body diode2 is heavily doped A body diode composed of the second conductivity type semiconductor shielding layer 4 and the lightly doped first conductivity type semiconductor body region 3; polySidiode is a polysilicon diode. The two diodes and the polysilicon diode can be used as the current path under the reverse conduction condition, which can not only improve the reverse current driving capability of the device, but also effectively alleviate the problem of excessive local junction temperature caused by current concentration.

Example 2

As shown in FIG. 4 , this embodiment provides a UMOS device with excellent forward and reverse conduction characteristics. Lightly doped second conductivity type polysilicon body regions 7 are alternately arranged between the two conductivity type polysilicon source electrode regions 5 .

Its top view is shown in Figure 5. By designing the polysilicon source electrode region into this structure with alternating heavy and light doping, the anode injection efficiency of the polysilicon diode can be effectively controlled, thereby shortening the reverse recovery time. Fig. 6 is another design structure of the polysilicon source electrode region, which is similar to Fig. 5, but the arrangement direction of heavy and light doping in the polysilicon source electrode region has changed.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (6)

1. A UMOS device having excellent forward and reverse conduction characteristics, comprising a metalized drain (1), a heavily doped first conductivity type semiconductor substrate (2) on the metalized drain (1), a lightly doped first conductivity type semiconductor body (3) on the heavily doped first conductivity type semiconductor substrate (2), a first conductivity type semiconductor highly doped region (8) on the lightly doped first conductivity type semiconductor body (3);

a highly doped second conductivity type semiconductor body region (9) located over said first conductivity type semiconductor highly doped region (8); a heavily doped first conductivity type semiconductor source region (11) and a heavily doped second conductivity type semiconductor contact region (12) located immediately above the highly doped second conductivity type semiconductor body region (9); the heavily doped first-conductivity-type semiconductor source region (11) and the heavily doped second-conductivity-type semiconductor contact region (12) are both in direct contact with the metalized source (14) in the form of ohmic contacts;

the upper part of the lightly doped first conductivity type semiconductor body region (3) is also provided with a groove structure, and the upper surface of the groove is electrically isolated from the metalized source electrode (14) through a dielectric layer (13); the side surface of the groove is provided with a gate oxide layer (6), and the gate oxide layer (6) is in direct contact with the side surfaces of the first conductive type semiconductor high doping area (8), the high doping second conductive type semiconductor body area (9) and the heavily doping first conductive type semiconductor source area (11); the part of the high-doped second conductive type semiconductor body region (9) close to the trench wall is a channel region; the trench is filled with a heavily doped first-conductivity-type polysilicon gate electrode region (10) and a lightly doped second-conductivity-type polysilicon body region (7), and the lightly doped second-conductivity-type polysilicon body region (7) is positioned below the heavily doped first-conductivity-type polysilicon gate electrode region (10) and is in direct contact with the lower surface of the heavily doped first-conductivity-type polysilicon gate electrode region; a heavily doped second conductivity type polycrystalline silicon source electrode region (5) is arranged right below the lightly doped second conductivity type polycrystalline silicon body region (7); a heavily doped second conductivity type semiconductor shielding layer (4) is arranged right below the heavily doped second conductivity type polycrystalline silicon source electrode region (5);

the heavily doped first conductivity type polysilicon gate electrode region (10) completely covers the side surface of the highly doped second conductivity type semiconductor body region (9); the heavily doped first conductivity type polysilicon gate electrode region (10) is connected with a gate potential; the heavily doped second conductive type polycrystalline silicon source electrode region (5) is connected with the potential of the metalized source electrode (14) through a through hole by layout design;

the method is characterized in that: the heavily doped first conductivity type polysilicon gate electrode region (10) completely covers the channel region, so that the switching performance of the semiconductor device can be realized; the heavily doped first conductivity type polysilicon gate electrode region (10) is connected with a gate potential; the heavily doped second conductivity type polysilicon source electrode region (5) and the metallized source electrode (14) are connected to a source potential; under the reverse operation of the semiconductor device, the gate contact and the drain contact are shorted.

2. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: lightly doped second conductivity type polycrystalline silicon body regions (7) are alternately arranged between heavily doped second conductivity type polycrystalline silicon source electrode regions (5) right below the lightly doped second conductivity type polycrystalline silicon body regions (7).

3. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the first conductivity type is n-type and the second conductivity type is p-type.

4. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the first conductivity type is p-type and the second conductivity type is n-type.

5. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the semiconductor is SiC.

6. A UMOS device having excellent forward and reverse turn-on characteristics as claimed in any one of claims 1 to 5, wherein: the doping concentration of heavy doping is more than 1E19cm ^-3 The doping concentration of the light doping is less than 1E17cm ^-3 The doping concentration of the high doping is 1E19cm ^-3 And 1E17cm ^-3 Between them.

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