CN114879418A - Array substrate and display panel - Google Patents
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- CN114879418A CN114879418A CN202210810567.XA CN202210810567A CN114879418A CN 114879418 A CN114879418 A CN 114879418A CN 202210810567 A CN202210810567 A CN 202210810567A CN 114879418 A CN114879418 A CN 114879418A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The utility model belongs to the technical field of show, concretely relates to array substrate and display panel, array substrate include the pixel unit that a plurality of arrays were arranged, and the pixel unit includes a plurality of sub-pixels, and the sub-pixel includes pixel electrode and thin film transistor, the pixel electrode includes main part electrode portion and connection electrode portion, main part electrode portion has the slit that a plurality of relative column direction slopes to set up, connection electrode portion with thin film transistor connects in a plurality of sub-pixels: the connecting electrode part of the pixel electrode in the sub-pixel is connected with the edge position of the main electrode part of the sub-pixel; and the connecting electrode part of the pixel electrode in the sub-pixel is connected with the middle position of the main electrode part of the sub-pixel. According to the scheme, the connection electrode parts of the sub-pixels in one pixel unit are connected with the main body connection part at different positions, so that the generation of black domain lines of one pixel unit can be reduced, the problem of black domain lines of the whole display panel is further reduced, and the display effect of the display panel is improved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
Most of the liquid crystal displays are backlight liquid crystal displays, which include a housing, a liquid crystal display panel disposed in the housing, and a backlight module disposed in the housing. The lcd needs to emit light normally by the light source provided by the backlight module.
Generally, a liquid crystal display panel is formed by bonding two Glass substrates (Array Glass and Color Filter Glass), liquid crystal is filled between the two Glass substrates, pixel electrodes and common electrodes are respectively arranged on the opposite inner sides of the two Glass substrates, the rotation direction of liquid crystal molecules is controlled by using voltage field intensity, and light of a backlight module is refracted out to generate a picture.
When the Vertical Alignment (VA) type liquid crystal display panel is scratched, a black domain line (Tracemura) is easy to appear and is not easy to disappear, and the display effect of the Vertical Alignment (VA) type liquid crystal display panel is seriously influenced.
Disclosure of Invention
An object of the present application is to provide an array substrate and a display panel, which can effectively reduce the occurrence of black domain lines (Tracemura).
The first aspect of the present application provides an array substrate, including a plurality of pixel units arranged in an array, the pixel unit includes a plurality of sub-pixels, the sub-pixel includes pixel electrode and thin film transistor, the pixel electrode includes main part electrode portion and connection electrode portion, the main part electrode portion has a plurality of slits that set up to the slope of column direction relatively, the connection electrode portion with thin film transistor connects in a plurality of sub-pixels:
the connecting electrode part of the pixel electrode in the sub-pixel is connected with the edge position of the main electrode part of the sub-pixel;
and the connecting electrode part of the pixel electrode in the sub-pixel is connected with the middle position of the main electrode part of the sub-pixel.
In an exemplary embodiment of the present application, the plurality of subpixels includes a first subpixel, a second subpixel, and a third subpixel arranged in sequence in a row direction;
the connecting electrode part of the pixel electrode in the first sub-pixel is connected with the edge position of the main electrode part of the pixel electrode, which is close to the second sub-pixel;
the connecting electrode part of the pixel electrode in the second sub-pixel is connected with the middle position of the main electrode part of the second sub-pixel;
and the connecting electrode part of the pixel electrode in the third sub-pixel is connected with the edge position of the main electrode part of the third sub-pixel, which is close to the second sub-pixel.
In an exemplary embodiment of the present application, the main body electrode portion includes a column trunk extending in the column direction and a row trunk extending in the row direction, the column trunk and the row trunk intersect and divide the main body electrode portion into four slit electrode portions, each slit electrode portion has a plurality of electrode branches arranged at intervals, the slit is formed between two adjacent electrode branches in each slit electrode portion, an edge of each slit electrode portion away from the column trunk is the edge position, and the position of the column trunk is the middle position;
and the connection electrode part of the pixel electrode in the second sub-pixel is connected with one side of the column trunk close to the thin film transistor.
In one exemplary embodiment of the present application, the four slit electrode portions are a first slit electrode portion, a second slit electrode portion, a third slit electrode portion, and a fourth slit electrode portion, respectively;
the first slit electrode portions and the second slit electrode portions are arranged in this order in the row direction, and the extending directions of the electrode branches of the first slit electrode portions and the second slit electrode portions are symmetrical to each other with respect to the column direction;
the third slit electrode portions and the fourth slit electrode portions are arranged in this order in the row direction, and the extending directions of the electrode branches of the third slit electrode portions and the fourth slit electrode portions are symmetrical to each other with respect to the column direction;
the third slit electrode portion is provided on a side of the first slit electrode portion closer to the thin film transistor in the column direction, and extending directions of electrode branches of the third slit electrode portion and the first slit electrode portion are symmetrical to each other with respect to the row direction;
the fourth slit electrode portion is provided on a side of the second slit electrode portion closer to the thin film transistor in the column direction, and extending directions of electrode branches of the fourth slit electrode portion and the second slit electrode portion are symmetrical to each other with respect to the row direction.
In an exemplary embodiment of the present application, in the first sub-pixel: the connecting electrode part of the pixel electrode is connected with the edge position, close to the second sub-pixel, in the electrode branch of the fourth slit electrode part;
in the third sub-pixel: the connecting electrode part of the pixel electrode is connected with the edge of the electrode branch of the third slit electrode part close to the second sub-pixel.
In an exemplary embodiment of the present application, the first slit electrode portion, the second slit electrode portion, the third slit electrode portion, and the fourth slit electrode portion are each provided with a side line connected to an edge of at least a part of the electrode branches;
the array substrate further comprises a substrate and a common electrode wire, and the common electrode wire is arranged on one side of the pixel electrode close to the substrate;
wherein, the orthographic projection of the side line and the column trunk on the substrate base plate is at least partially overlapped with the orthographic projection of the common electrode line on the substrate base plate.
In an exemplary embodiment of the present application, each of the first slit electrode portion and the second slit electrode portion includes a first side line extending in the row direction and a second side line extending in the column direction, the first side line is connected to the column trunk and a side of a part of the electrode branches away from the thin film transistor, and the second side line is connected to the row trunk and a side of a part of the electrode branches close to the data line;
the third slit electrode part comprises a third edge line extending along the column direction, and the third edge line is connected with the row main part and one side of part of the electrode branches close to the data line;
the fourth slit electrode part comprises a fourth edge line extending along the column direction, and the fourth edge line is connected with the row main part and one side of part of the electrode branches close to the data line; wherein,
in the first sub-pixel, the second sub-pixel, and the third sub-pixel: a first opening is arranged between the first side line and the second side line;
in the first sub-pixel: the connection electrode part of the pixel electrode and the fourth edge line thereof are provided with a second opening;
in the third sub-pixel: the connection electrode part of the pixel electrode and the third line thereof have a third opening.
In an exemplary embodiment of the present application, the electrode branches and the column stems have an inclination angle α, which is 30 ° to 60 °.
In one exemplary embodiment of the present application, pitches between adjacent slits in the first slit electrode section, the second slit electrode section, the third slit electrode section, and the fourth slit electrode section are the same.
The second aspect of the present application provides a display panel, comprising liquid crystal molecules, a counter substrate and the array substrate of any one of the above, wherein the liquid crystal molecules are disposed between the counter substrate and the array substrate.
The scheme of the application has the following beneficial effects:
the array substrate comprises a plurality of pixel units arranged in an array, wherein one pixel unit comprises a plurality of sub-pixels, a connecting electrode part of a pixel electrode in one sub-pixel is connected with the edge position of a main electrode part of the pixel electrode in the sub-pixel in the plurality of sub-pixels, and the connecting electrode part of the pixel electrode in one sub-pixel is connected with the middle position of the main electrode part of the pixel electrode in the sub-pixel; the connection electrode parts of the pixel electrodes in the sub-pixels in one pixel unit and the main electrode part at least have two different connection positions, so that when the display panel is stroked along different directions, at least one sub-pixel in one pixel unit can not generate a black domain line (Tracemura), and the occurrence of the black domain line (Tracemura) in one pixel unit is further reduced. In addition, this application scheme still includes display panel, and this display panel includes array substrate and the opposition base plate that set up to the box and is located the liquid crystal molecule between array substrate and the opposition base plate, through reducing black domain line (Tracemura) in the array substrate pixel unit, and then reduces the appearance of whole display panel black domain line (Tracemura) from the macroscopic, improves display panel's display effect.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 shows a schematic structural diagram of an array substrate according to a first embodiment of the present application.
Fig. 2 shows a schematic structural diagram of a pixel unit according to a first embodiment of the present application.
Fig. 3 shows a schematic structural diagram of a sub-pixel and a common electrode line according to a first embodiment of the present application.
Fig. 4 shows a schematic structural diagram of a pixel electrode in a first sub-pixel according to a first embodiment of the present application.
Fig. 5 shows a schematic structural diagram of a pixel electrode in a second sub-pixel according to a first embodiment of the present application.
Fig. 6 shows a schematic structural diagram of a pixel electrode in a third sub-pixel according to a first embodiment of the present application.
Fig. 7 shows a schematic structural diagram of a display panel provided in the second embodiment of the present application.
Description of reference numerals:
1. a sub-pixel; 1a, a first sub-pixel; 1b, a second sub-pixel; 1c, a third sub-pixel; 10. a pixel electrode; 11. a main electrode section; 11a, a first slit electrode portion; 11b, a second slit electrode portion; 11c, a third slit electrode portion; 11d, a fourth slit electrode portion; 111. arranging trunks; 112. a trunk line; 113. electrode branching; 114. a slit; 115. a side line; 115a, a first edge line; 115b, a second edge line; 115c, a third edge line; 115d, a fourth edge line; 116. a first opening; 117. a second opening; 118. a third opening; 12. a connection electrode section; 20. a thin film transistor; 30. a substrate base plate; 40. a common electrode line; 50. scanning a line; 60. a data line; 100. a display panel; 101. an array substrate; 102. a pixel unit; 103. an opposing substrate; 104. liquid crystal molecules.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
In the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.
Example one
Referring to fig. 1, an array substrate 101 according to an embodiment of the present disclosure includes a plurality of pixel units 102 arranged in an array along a row direction X and a column direction Y.
As shown in fig. 1, one pixel unit 102 may include a plurality of sub-pixels 1, each sub-pixel 1 includes a pixel electrode 10 and a thin film transistor 20, each pixel electrode 10 includes a main electrode portion 11 and a connection electrode portion 12, each main electrode portion 11 has a plurality of slits 114 arranged obliquely with respect to the column direction Y, each connection electrode portion 12 is connected to the thin film transistor 20, and in each of the plurality of sub-pixels 1: the connecting electrode part 12 of the pixel electrode 10 in the sub-pixel 1 is connected with the edge position of the main electrode part 11; the connection electrode portion 12 of the pixel electrode 10 in one sub-pixel 1 is connected to the middle of the main electrode portion 11.
It should be noted that, the main electrode portion 11 of the pixel electrode 10 is located in the display area to transmit the light generated by the backlight module, and the main electrode portion 11 can also drive the liquid crystal molecules 104 to rotate to control the deflection angle of the light; the connecting electrode part 12 is connected with the main electrode part 11, transmits a data signal to the main electrode part 11 through the thin film transistor 20, and controls the voltage of the main electrode part 11 to drive the liquid crystal molecules 104 to deflect; in addition, the connecting electrode portion 12 is located in the non-display region, so as to prevent the connecting electrode portion 12 from affecting the display effect of the display panel 100, and also increase the display range of the display panel 100, thereby improving the display effect of the display panel 100.
It is noted that when the display panel 100 is pressed or stroked, the arrangement of the liquid crystal molecules 104 between the array substrate 101 and the counter substrate 103 becomes irregular, thereby generating a black domain line (Trace mura). The starting point of the black domain line (Trace mura) is derived from the non-display region, and since the black matrix is provided on the counter substrate 103 corresponding to the non-display region, photo alignment cannot be performed, and the topography of the thin film transistor 20 in the non-display region is complicated, and the liquid crystal molecules 104 themselves are not regular; therefore, when the display panel 100 is pressed or stroked, the liquid crystal molecules 104 in the non-display region are diffused to the liquid crystal molecules 104 in the connecting electrode portion 12, and then the liquid crystal molecules 104 in the non-display region are gradually diffused to the liquid crystal molecules 104 in the main electrode portion 11 through the electric field on the connecting electrode portion 12 and the electric field routing; that is, the liquid crystal molecules 104 in the non-display region enter the main electrode portion 11, and the liquid crystal molecules in the main electrode portion 11 are pressed, so that the arrangement of the liquid crystal molecules 104 at the main electrode portion 11 becomes irregular, and a black domain line (Trace mura) is generated. In other words, the black domain lines (Trace mura) are diffused from the non-display region to the display region; alternatively, the black domain lines (Trace mura) are transferred from the non-display region to the display region along the electrode traces on the connection electrode portion 12.
Therefore, the present disclosure provides an array substrate, which can change the connection Trace direction between the connection electrode 12 and the main electrode 11 of the sub-pixel 1 in one pixel unit 102, so as to avoid the generation of a black domain line (Trace mura).
For example, as shown in fig. 1, in one pixel unit 102, the connection electrode portion 12 of one sub-pixel 1 is connected to the edge position of the main electrode portion 11, and the connection electrode portion 12 of one sub-pixel 1 is connected to the center position of the main electrode portion 11.
Thus, when the display panel 100 is pressed or scratched, by the different connection relationship between the connection electrode portion 12 and the main electrode portion 11 in the sub-pixel 1 in one pixel unit 102, the liquid crystal molecules 104 reaching the connection electrode portion 12 in a part of the sub-pixel 1 enter the main electrode portion 11 along the edge, and the other part is connected with the center of the main electrode portion 11 and does not enter the main electrode portion 11 through the connection electrode portion 12; of course, depending on the stroking direction, some of the connection electrode portions 12 of the sub-pixels 1 may enter the main electrode portion 11 along the center position of the main electrode portion 11, and another portion may not enter the main electrode portion 11 due to the connection with the edge position.
It should be understood that in one pixel unit 102, due to the fact that the connection electrode portion 12 and the main electrode portion 11 in the sub-pixel 1 are different in connection relationship, a part of the sub-pixel 1 may generate a black domain line (Trace mura) along the electrode Trace of the connection electrode portion 12, and another part of the sub-pixel 1 may not generate the black domain line (Trace mura) along the electrode line of the connection electrode portion 12. Thus, the generation of the black domain lines (Trace mura) in one pixel unit 102 can be reduced, and from the macroscopic view of the whole display panel 100, the generation of the black domain lines (Trace mura) of the whole display panel 100 is improved, so that the severity of the generation of the black domain lines (Trace mura) of the display panel 100 is reduced, and the display effect of the display panel 100 is improved.
Illustratively, referring to fig. 2 and 3, the plurality of sub-pixels 1 includes a first sub-pixel 1a, a second sub-pixel 1b, and a third sub-pixel 1c arranged in sequence in the row direction X, and the first sub-pixel 1a, the second sub-pixel 1b, and the third sub-pixel 1c correspond to one pixel unit 102. The connection electrode part 12 of the pixel electrode 10 in the first sub-pixel 1a is connected with the edge position of the main electrode part 11 close to the second sub-pixel 1 b; the connection electrode portion 12 of the pixel electrode 10 in the second sub-pixel 1b is connected to the middle position of the main electrode portion 11 thereof; the connection electrode portion 12 of the pixel electrode 10 in the third sub-pixel 1c is connected to the edge position of the main electrode portion 11 thereof near the second sub-pixel 1 b.
Thus, when the display panel 100 is stroked along the Trace direction of the connection electrode portion 12 of the first sub-pixel 1a, only the liquid crystal molecules 104 in one sub-pixel 1 in one pixel unit 102 are diffused to the display area along the electrode line of the connection electrode portion 12, and then black domain lines (Trace mura) appear, while the other two sub-pixels 1 are different from the Trace line because the electrode Trace of the connection electrode portion 12 and the electrode Trace of the main electrode portion 11 are different, so the liquid crystal molecules 104 in the other two sub-pixels 1 are not diffused along the electrode Trace of the connection electrode portion 12, and the generation of the black domain lines (Trace mura) is reduced; that is, only one sub-pixel 1 in one pixel unit 102 generates a black domain line (Trace mura), which reduces the number of the generated black domain lines (Trace mura) in one pixel unit 102, and further reduces the macro-scale expression of the black domain lines (Trace mura) of the display panel 100, thereby improving the display effect of the display panel 100.
When the display panel 100 is stroked along the routing direction of the connecting electrode portion 12 of the second sub-pixel 1b, and when the display panel 100 is stroked along the routing direction of the connecting electrode portion 12 of the second sub-pixel 1b, the principle is the same as above, and the description thereof is omitted.
The first subpixel 1a, the second subpixel 1B, and the third subpixel 1c correspond to a red color resist R, a green color resist G, and a blue color resist B on the counter substrate 103, respectively. Of course, the first sub-pixel 1a, the second sub-pixel 1B, and the third sub-pixel 1c may correspond to the green color resist G, the red color resist R, and the blue color resist B on the counter substrate 103, respectively, and are not limited specifically.
In addition, the plurality of sub-pixels 1 may also be a first sub-pixel 1a, a second sub-pixel 1b, and a third sub-pixel 1c that are sequentially arranged in the column direction Y, and may be specifically designed according to different panel structures.
The connection electrode portions 12 and the main electrode portions 11 in the same column of the sub-pixels 1 may be connected in the same manner or in different manners. For example, the connection electrode portion 12 of the first sub-pixel 1a is connected to the edge position, and the connection electrode portions 12 of the first sub-pixels 1a in adjacent rows may be connected to the edge position or the middle position.
In an alternative embodiment, the connection electrode portions 12 and the main electrode portions 11 in the row of sub-pixels 1 are connected in the same manner, so that the manufacturing cost is reduced, and the production efficiency of the array substrate 101 is improved.
In another alternative embodiment, the connection electrode portions 12 and the main electrode portions 11 in one column of the sub-pixels 1 are connected in a different manner, so that the sub-pixels in adjacent columns can be prevented from generating black domain lines (Trace mura) at the same time, which can be better prevented from generating the black domain lines (Trace mura).
In addition, the electrode traces of the connection electrode part 12 and the main electrode part 11 of the sub-pixels 1 in different rows can be in the same horizontal area, so that the area of the non-display area is saved.
Further, the sub-pixel 1 may be designed as a single domain, a two domain, a four domain or an eight domain, and may be specifically designed according to a specific implementation manner, which is not specifically limited herein.
For example, when the sub-pixel 1 is a single domain, the connection electrode portion 12 in the first sub-pixel 1a is connected to the edge of the main electrode portion 11 close to the second sub-pixel 1b, and the slit 114 of the main electrode portion 11 may be designed obliquely downward and leftward; the connection electrode portion 12 in the second sub-pixel 1b is connected to the center position of the main electrode portion 11, and the slit 114 of the main electrode portion 11 can be designed in the same direction as the slit 114 in the first sub-pixel 1 a; the connection electrode portion 12 in the third sub-pixel 1c is connected to the edge of the main electrode portion 11 close to the second sub-pixel 1b, the slit 114 of the main electrode portion 11 in the third sub-pixel 1c may be designed with the same inclination angle as the slit 114 in the first sub-pixel 1a, or may be designed complementary to the inclination angle in the first sub-pixel 1a, that is, the slit 114 of the main electrode portion 11 in the third sub-pixel 1c may be designed obliquely and vertically, so as to ensure that at least two different routing ways exist in one pixel unit 102, so that when the display panel 100 is scratched in different directions, only one black domain line (Trace mura) is generated in one pixel unit 102, thereby reducing the generation of the black domain line (Trace mura) of the entire display panel 100 and improving the display effect of the display panel 100.
For another example, referring to fig. 2 or 3, when the sub-pixel 1 is a four-domain sub-pixel, the main body electrode portion 11 includes a column trunk 111 extending in the column direction Y and a row trunk 112 extending in the row direction X, the column trunk 111 and the row trunk 112 intersect and divide the main body electrode portion 11 into four slit electrode portions, each slit electrode portion has a plurality of electrode branches 113 arranged at intervals, a slit 114 is formed between two adjacent electrode branches 113 in each slit electrode portion, an edge of each slit electrode portion away from the column trunk 111 is an edge position, and the position of the column trunk 111 is an intermediate position; the connection electrode 12 of the pixel electrode 10 in the second sub-pixel 1b is connected to the side of the column trunk 111 close to the thin film transistor 20.
In an alternative embodiment, referring to fig. 2 or fig. 3, the row stems 112 and the column stems 111 are perpendicular to each other, and the centers of the row stems 112 and the column stems 111 converge at a point, and the centers of the row stems 112 and the column stems 111 correspond to the middle position.
Further, referring to fig. 2 or 3, four slit electrode portions are a first slit electrode portion 11a, a second slit electrode portion 11b, a third slit electrode portion 11c, and a fourth slit electrode portion 11d, respectively; the first slit electrode portions 11a and the second slit electrode portions 11b are arranged in this order in the row direction X, and the third slit electrode portions 11c and the fourth slit electrode portions 11d are arranged in this order in the row direction X; the first slit electrode portion 11a and the third slit electrode portion 11c are arranged in this order in the column direction Y, and the third slit electrode portion 11c is provided on the side of the first slit electrode portion 11a close to the thin film transistor 20.
That is, the first slit electrode portion 11a and the second slit electrode portion 11b are arranged in this order from left to right, and the first slit electrode portion 11a and the third slit electrode portion 11c are arranged in this order from top to bottom.
Further, the extending directions of the electrode branches 113 of the first slit electrode portion 11a and the second slit electrode portion 11b are symmetrical to each other with respect to the column direction Y; the extending directions of the electrode branches 113 of the third slit electrode portion 11c and the fourth slit electrode portion 11d are symmetrical to each other with respect to the column direction Y; the extending directions of the electrode branches 113 of the first slit electrode portion 11a and the third slit electrode portion 11c are symmetrical to each other with respect to the row direction X; the extending directions of the electrode branches 113 of the second slit electrode portion 11b and the fourth slit electrode portion 11d are symmetrical to each other with respect to the row direction X.
For example, as shown in fig. 3, the electrode branches 113 in the first slit electrode portion 11a extend in the upper left direction with respect to the column trunk 111; the electrode branches 113 in the second slit electrode portion 11b extend in the upper right direction with respect to the column trunk 111; the electrode branches 113 in the third slit electrode portion 11c extend to the lower left with respect to the column trunk 111; the electrode branches 113 in the fourth slit electrode portion 11d extend to the lower right with respect to the column trunk 111.
Further, the third slit electrode portion 11c is provided on the side of the first slit electrode portion 11a closer to the thin film transistor 20 in the column direction; the fourth slit electrode portion 11d is provided on the side of the second slit electrode portion 11b closer to the thin film transistor 20 in the column direction.
Further, as shown in fig. 2 or fig. 3, the connection electrode portion 12 of the pixel electrode 10 in the first sub-pixel 1a is connected to the edge position of the electrode branch 113 in the fourth slit electrode portion 11d near the second sub-pixel 1 b; the connection electrode portion 12 of the pixel electrode 10 in the second sub-pixel 1b is connected to the column trunk 111; the connection electrode portion 12 of the pixel electrode 10 in the third sub-pixel 1c is connected to the edge position of the electrode branch 113 in the third slit electrode portion 11c near the second sub-pixel 1 b.
That is, the wiring manner of the connection electrode portion 12 and the main electrode portion 11 in the first sub-pixel 1a, the wiring manner of the connection electrode portion 12 and the main electrode portion 11 in the second sub-pixel 1b, and the wiring manner of the connection electrode portion 12 and the main electrode portion 11 in the third sub-pixel 1c are different; that is, the connection electrode portion 12 in the first sub-pixel 1a is connected to the end of the electrode branch 113 extending to the lower right as shown in fig. 4; the connection electrode section 12 in the second subpixel 1b is connected to the column stem 111, as shown in fig. 5; the connection electrode portion 12 in the third sub-pixel 1c is connected to the end of the electrode branch 113 extending to the lower left, as shown in fig. 6. Thus, along different stroking directions, only one sub-pixel 1 in one pixel unit 102 generates a black domain line (Trace mura), which reduces the generation of the black domain line (Trace mura) in one pixel unit 102, further reduces the generation of the black domain line (Trace mura) of the whole display panel 100, and improves the display effect of the display panel 100.
For example, when the display panel 100 is stroked along the upper left direction, since the electrode branch 113 in the first sub-pixel 1a extends downward and rightward, which is the same as the stroking direction, the connection electrode portion 12 in the first sub-pixel 1a and the liquid crystal molecules 104 in the thin film transistor 20 will gradually transfer to the fourth slit electrode portion 11d along with the electrode Trace of the connection electrode portion 12, so as to form a black domain line (Trace mura); since the connection electrode portion 12 in the second sub-pixel 1b is connected to the column trunk 111, when the liquid crystal molecules are stroked along the upper left, the direction of the stroking is different from that of the connection electrode portion 12, the liquid crystal molecules 104 located at the connection electrode portion 12 and the thin film transistor 20 will not enter the main electrode portion 11 along with the routing of the connection electrode portion 12, that is, a black domain line (Trace mura) will not be formed; the connection electrode portion 12 in the third sub-pixel 1c is connected to the electrode branch 113 in the third slit electrode portion 11c, and the extending direction of the electrode branch 113 in the third slit electrode portion 11c and the extending direction of the electrode branch 113 in the fourth slit electrode portion 11d are symmetrical to each other with respect to the column trunk 111, that is, when the display panel 100 is stroked along the upper left, the liquid crystal molecules 104 at the connection electrode portion 12 and the thin film transistor 20 in the third sub-pixel 1c are not transferred into the main body electrode portion 11 along the routing direction of the connection electrode portion 12.
Similarly, when stroking is performed in the vertical direction, the first sub-pixel 1a and the third sub-pixel 1c do not generate a black domain line (Trace mura), and the second sub-pixel 1b generates a black domain line (Trace mura); when stroking along the upper right, the first sub-pixel 1a and the second sub-pixel 1b do not generate a black domain line (Trace mura), and the third sub-pixel 1c generates a black domain line (Trace mura); the specific principle can be analyzed by referring to the above-mentioned principle of moving along the upper left direction, and is not described in detail herein.
In this way, only one sub-pixel 1 in one pixel unit 102 generates a black domain line (Trace mura), and the other two sub-pixels 1 do not generate a black domain line (Trace mura), so that the generation of the black domain line (Trace mura) of the entire display panel 100 is reduced, and the display effect of the display panel 100 is improved.
Next, the ends of the electrode branches 113 of the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c, and the fourth slit electrode portion 11d may be provided with the borderline 115, or may not be provided with the borderline 115.
For example, referring to fig. 1, 2 or 3, the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c and the fourth slit electrode portion 11d are each provided with a side line 115 connected to an edge of at least a part of the electrode branch 113; the array substrate 101 further includes a substrate 30 and a common electrode line 40, and the common electrode line 40 is disposed on one side of the pixel electrode 10 close to the substrate 30.
Note that, there is a partial overlap between the orthographic projections of the side lines 115 and the column trunks 111 on the substrate 30 and the orthographic projection of the common electrode lines 40 on the substrate 30, so as to form storage capacitors. In addition, the common electrode line 40 is used for receiving a common signal and forms a storage capacitance with the pixel electrode 10.
As shown in fig. 3, a part of the common electrode line 40 overlaps with the orthogonal projection of the column trunk 111 on the substrate 30, and another part overlaps with the orthogonal projection of the edge line 115 on the substrate 30. In this way, by providing the borderline 115 in the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c, and the fourth slit electrode portion 11d, the storage area of the capacitor can be increased.
In addition, the thin film transistor 20 may include a gate electrode, an active layer, and a first electrode and a second electrode disposed at the same layer, and a gate insulating layer may be disposed between the gate electrode and the active layer to insulate the gate electrode and the active layer from each other; the first electrode and the second electrode may be respectively connected to the source and drain doped regions of the active layer, and the connection relationship between the first electrode and the source and drain doped regions of the active layer may be determined according to whether the thin film transistor 20 is N-type or P-type, which will not be described in detail herein.
For example, the thin film transistor 20 of the embodiment of the present application may be a bottom gate type, that is: the gate electrode may be formed on the substrate base plate 30 first; then, a gate insulating layer is formed on the substrate base plate 30, and the gate insulating layer covers the gate electrode; an active layer is then formed on the side of the gate insulating layer facing away from the substrate base plate 30, namely: the active layer is positioned on the side of the gate electrode far away from the substrate 30, and the active layer overlaps with the orthographic projection of the gate electrode on the substrate 30, for example, the orthographic projection of the active layer on the substrate 30 can be positioned in the orthographic projection of the gate electrode on the substrate 30; the first pole and the second pole can be formed after the active layer is formed, and at least part of the first pole can be lapped on a doping area of the source and drain doping areas of the active layer; at least a portion of the second pole may overlap another doped region of the source and drain doped regions of the active layer.
Note that the thin film transistor 20 according to the embodiment of the present invention is not limited to the bottom gate type described above, and may be a top gate type. It should be noted that the gate of the thin film transistor 20 can be understood as the control terminal thereof, the first electrode can be understood as the first terminal, and the second electrode can be understood as the second terminal.
In addition, the array substrate 101 further includes a scan line 50 extending in the row direction X and a data line 60 extending in the column direction Y, the data line 60 is located between two sub-pixels 1, and the scan line 50 is located between adjacent pixel units 102.
The scan line 50 may be connected to a control terminal of the thin film transistor 20 to control the thin film transistor 20 to be turned on or off. Alternatively, the scan line 50 may be disposed on the same layer as the gate electrode of the thin film transistor 20 and integrally connected thereto.
In the present application, "same layer arrangement" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then performing a patterning process once using the same mask plate. That is, one mask (also called as a photomask) is corresponding to one patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost and improving the production efficiency.
For example, the scan line 50 may be made of a metal or alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity, but is not limited thereto, and may also be made of other materials with good conductivity.
The data line 60 may extend in the column direction Y, wherein the data line 60 may be connected to the second terminal (i.e., the aforementioned second pole) of the thin film transistor 20 to write a data signal to the second terminal of the thin film transistor 20. Alternatively, the data line 60 may be disposed at the second opposite layer of the thin film transistor 20 and integrally connected thereto.
The data line 60 may be made of metal or alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity, but is not limited thereto, and may also be made of other material with good conductivity.
The pixel electrode 10 may be connected to a first terminal (i.e., the aforementioned first pole) of the thin film transistor 20, and when the thin film transistor 20 is turned on in response to the scan signal provided by the scan line 50, the data signal provided by the data line 60 may flow into the first pole of the thin film transistor 20 through the second pole to be written into the pixel electrode 10, so as to form a voltage difference with the common voltage on the opposite substrate 103 side, and then deflect the liquid crystal molecules 104 between the opposite substrate 103 and the array substrate 101, thereby implementing a display function.
The pixel electrode 10 of the present embodiment can be a transparent electrode, for example, it can be made of ITO (indium tin oxide) material to improve light transmittance, but is not limited thereto, and it can also be made of other transparent conductive materials.
In addition, the substrate 30 may be a glass substrate or a PI (polyimide) substrate, and the aforementioned sub-pixels 1, the common electrode lines 40, the data lines 60, and the scan lines 50 are formed on one substrate 30 to form the array substrate 101.
It should be noted that the common electrode line 40 and the scan line 50 may be disposed on the same layer, that is, the common electrode line 40 and the scan line 50 may be formed by the same film forming process, and then formed by a one-time composition process using the same mask plate, so that the manufacturing process may be simplified, the manufacturing cost may be saved, and the production efficiency may be improved.
It should be understood that the common electrode line 40 and the scan line 50 are disconnected from each other to ensure that the scan signal and the common signal are independent from each other, thereby avoiding a situation where a shot (mottle, flash) is generated due to crosstalk between the signals, and thus improving the display effect.
When the scan lines 50 are made of a metal material, the common electrode lines 40 are also made of the same metal material, so as to improve the conductivity thereof.
Further, as shown in fig. 2 or fig. 3, each of the first slit electrode portion 11a and the second slit electrode portion 11b is provided with a first side line 115a extending along the row direction X and a second side line 115b extending along the column direction Y, and the first side line 115a is provided at one end of the column trunk 111 away from the thin film transistor 20 and is connected to one side of the column trunk 111 and the partial electrode branches 113 of the first slit electrode portion 11a and the second slit electrode portion 11b away from the thin film transistor 20.
Still further, the second side line 115b is connected to the side of the row trunk 112 and the partial electrode branch 113 in the second slit electrode portion 11b near the data line 60; the third slit electrode portion 11c and the fourth slit electrode portion 11d are respectively provided with a third line 115c and a fourth line 115d extending in the column direction Y, the third line 115c and the fourth line 115d are respectively provided at both ends of the row trunk 112, and the third line 115c is connected to one side of the partial electrode branches 113 of the row trunk 112 and the third slit electrode portion 11c, which is close to the data line 60; the fourth side line 115d is connected to the row trunk 112 and a side of the partial electrode branch 113 in the fourth slit electrode portion 11d near the data line 60.
The first sideline 115a may be connected to the second sidelines 115b at both ends, or may have an opening with the second sidelines 115b at both ends.
For example, referring to fig. 3, a first opening 116 is disposed between the first edge line 115a and the second edge line 115b at two ends to prevent the liquid crystal molecules 104 corresponding to the first edge line 115a from being disturbed by the liquid crystal molecules 104 corresponding to the second edge line 115b, so as to influence the deflection of the liquid crystal molecules 104, improve the deflection stability of the liquid crystal molecules 104, and further improve the display effect of the display panel 100.
Further, the third side line 115c is collinear and connected with the second side line 115b at the first slit electrode portion 11 a; the fourth side line 115d is collinear with and connected to the second side line 115b at the second slit electrode portion 11 b.
Further, the connection electrode portion 12 of the pixel electrode 10 in the first sub-pixel 1a and the fourth line 115d thereof have the second opening 117, and may be connected to the fourth line 115 d; the connection electrode portion 12 of the pixel electrode 10 in the third subpixel 1c may have a third opening 118 with a third line 115c thereof, or may be connected to the third line 115 c.
For example, referring to fig. 3 or 4, the connection electrode portion 12 of the pixel electrode 10 in the first sub-pixel 1a and the fourth side line 115d thereof have a second opening 117. In this way, the liquid crystal molecules 104 at the fourth line 115d and the connecting electrode portion 12 are prevented from being disturbed to influence the deflection angle of the liquid crystal molecules 104, and in addition, the liquid crystal molecules 104 at the fourth line 115d are reduced, so that the deflection effect of the liquid crystal molecules 104 at the position can be improved, light rays of the backlight module can better pass through refraction, more light rays can penetrate through, the light ray intensity of the display panel 100 is further improved, and the display panel 100 is brighter; the connection electrode portion 12 of the pixel electrode 10 in the third sub-pixel 1c and the third side line 115c thereof have a third opening 118, as shown in fig. 3 or fig. 6; the function of the second opening 117 formed between the connection electrode portion 12 and the fourth edge line 115d in the first sub-pixel 1a is the same, and the description thereof is omitted.
The connection electrode portion 12 in the first sub-pixel 1a is connected to at least one electrode branch 113 of the fourth slit electrode portion 11d, and the connection electrode portion 12 in the third sub-pixel 1c is connected to at least one electrode branch 113 of the third slit electrode portion 11 c.
Illustratively, referring to fig. 4, the connection electrode portion 12 in the first sub-pixel 1a is connected to the two electrode branches 113 of the fourth slit electrode portion 11 d; referring to fig. 6, the connection electrode portion 12 in the third sub-pixel 1c is connected to the two electrode branches 113 of the third slit electrode portion 11 c; thus, the connection stability between the connection electrode portion 12 and the electrode branch 113 can be ensured, and the signal transmission effect can be improved.
Of course, the connection electrode portion 12 may be connected to three or four electrode branches 113, and may be designed according to different embodiments, and is not limited in detail here.
Further, referring to fig. 2 or fig. 3, the electrode branches 113 and the column trunk 111 have an inclination angle α, which is 30 ° to 60 °.
Illustratively, the electrode branches 113 at the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c, and the fourth slit electrode portion 11d form an inclination angle of 45 ° with the column trunk 111. In this way, the signal transmission effect can be ensured, and also the connection electrode portion 12 and the electrode branch 113 can be better connected.
Furthermore, the inclination angle α may also be 30 °, 50 ° or 60 °.
Further, referring to fig. 3, the distances between adjacent slits 114 in the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c, and the fourth slit electrode portion 11d are the same or different.
For example, the distances between adjacent slits 114 in the first slit electrode portion 11a, the second slit electrode portion 11b, the third slit electrode portion 11c and the fourth slit electrode portion 11d are the same, so that the number of liquid crystal molecules 104 between the slit electrode portions is the same, the display effect is ensured, the sub-pixel 1 is more stable, and the display effect of the display panel 100 is improved.
Example two
Referring to fig. 7, a second embodiment of the present application provides a display panel 100, where the display panel 100 may be a liquid crystal display panel. The display panel 100 may include the array substrate 101 described in the first embodiment, and the description thereof is not repeated herein. And the display panel 100 further includes a counter substrate 103 disposed opposite to the array substrate 101 and liquid crystal molecules 104 between the array substrate 101 and the counter substrate 103.
The opposite substrate 103 may include a glass substrate, and a color resist layer, a BM layer, a common electrode plate, an alignment film, etc. formed on the glass substrate, which will not be described in detail herein.
It should be understood that, by changing the routing manner of the connection electrode portion 12 and the main electrode portion 11 in the pixel unit 102 in the array substrate 101, the generation of the black domain lines (Trace mura) in the pixel unit 102 is reduced, and then the generation of the black domain lines (Trace mura) in the entire display panel 100 is reduced, thereby improving the display effect of the display panel 100.
In addition, the display panel 100 may adopt a vertical alignment mode. For example, an MVA (multi-domain vertical alignment) display panel 100 or a pva (patterned vertical alignment).
In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and should not be construed as limiting the present application and that various changes, modifications, substitutions and alterations can be made therein by those skilled in the art within the scope of the present application, and therefore all changes and modifications that come within the meaning of the claims and the description of the invention are to be embraced therein.
Claims (10)
1. An array substrate, comprising a plurality of pixel units arranged in an array, wherein each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a pixel electrode and a thin film transistor, the pixel electrode comprises a main electrode part and a connecting electrode part, the main electrode part is provided with a plurality of slits obliquely arranged relative to the column direction, the connecting electrode part is connected with the thin film transistor, and in the plurality of sub-pixels:
the connecting electrode part of the pixel electrode in the sub-pixel is connected with the edge position of the main electrode part of the sub-pixel;
and the connecting electrode part of the pixel electrode in the sub-pixel is connected with the middle position of the main electrode part of the sub-pixel.
2. The array substrate of claim 1, wherein the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence in a row direction;
the connecting electrode part of the pixel electrode in the first sub-pixel is connected with the edge position of the main electrode part of the pixel electrode, which is close to the second sub-pixel;
the connecting electrode part of the pixel electrode in the second sub-pixel is connected with the middle position of the main electrode part of the second sub-pixel;
and the connecting electrode part of the pixel electrode in the third sub-pixel is connected with the edge position of the main electrode part of the third sub-pixel, which is close to the second sub-pixel.
3. The array substrate according to claim 2, wherein the main body electrode portion comprises a column trunk extending in the column direction and a row trunk extending in the row direction, the column trunk and the row trunk intersect and divide the main body electrode portion into four slit electrode portions, each slit electrode portion has a plurality of electrode branches arranged at intervals, the slits are formed between two adjacent electrode branches in each slit electrode portion, an edge of each slit electrode portion away from the column trunk is the edge position, and the position of the column trunk is the middle position;
and the connection electrode part of the pixel electrode in the second sub-pixel is connected with one side of the column trunk close to the thin film transistor.
4. The array substrate according to claim 3, wherein the four slit electrode portions are a first slit electrode portion, a second slit electrode portion, a third slit electrode portion, and a fourth slit electrode portion, respectively;
the first slit electrode portions and the second slit electrode portions are arranged in this order in the row direction, and the extending directions of the electrode branches of the first slit electrode portions and the second slit electrode portions are symmetrical to each other with respect to the column direction;
the third slit electrode portions and the fourth slit electrode portions are arranged in this order in the row direction, and the extending directions of the electrode branches of the third slit electrode portions and the fourth slit electrode portions are symmetrical to each other with respect to the column direction;
the third slit electrode portion is provided on a side of the first slit electrode portion closer to the thin film transistor in the column direction, and extending directions of electrode branches of the third slit electrode portion and the first slit electrode portion are symmetrical to each other with respect to the row direction;
the fourth slit electrode portion is provided on a side of the second slit electrode portion closer to the thin film transistor in the column direction, and extending directions of electrode branches of the fourth slit electrode portion and the second slit electrode portion are symmetrical to each other with respect to the row direction.
5. The array substrate of claim 4, wherein in the first sub-pixel: the connecting electrode part of the pixel electrode is connected with the edge position, close to the second sub-pixel, in the electrode branch of the fourth slit electrode part;
in the third sub-pixel: the connecting electrode part of the pixel electrode is connected with the edge position of the electrode branch of the third slit electrode part close to the second sub-pixel.
6. The array substrate according to claim 4 or 5, wherein the first slit electrode portion, the second slit electrode portion, the third slit electrode portion and the fourth slit electrode portion are each provided with a border line connecting edges of at least some of the electrode branches;
the array substrate further comprises a substrate and a common electrode wire, and the common electrode wire is arranged on one side of the pixel electrode close to the substrate;
wherein, the orthographic projection of the side line and the column trunk on the substrate base plate is at least partially overlapped with the orthographic projection of the common electrode line on the substrate base plate.
7. The array substrate according to claim 6, wherein the first slit electrode portion and the second slit electrode portion each include a first side line extending in the row direction and a second side line extending in the column direction, the first side line being connected to the column trunk and a side of a portion of the electrode branches away from the thin film transistor, the second side line being connected to the row trunk and a side of a portion of the electrode branches close to the data line;
the third slit electrode part comprises a third edge line extending along the column direction, and the third edge line is connected with the row main part and one side of part of the electrode branches close to the data line;
the fourth slit electrode part comprises a fourth edge line extending along the column direction, and the fourth edge line is connected with the row main part and one side of part of the electrode branches close to the data line; wherein,
in the first sub-pixel, the second sub-pixel, and the third sub-pixel: a first opening is arranged between the first side line and the second side line;
in the first sub-pixel: the connection electrode part of the pixel electrode and the fourth edge line thereof are provided with a second opening;
in the third sub-pixel: the connection electrode part of the pixel electrode and the third line thereof have a third opening.
8. The array substrate of claim 3, wherein the electrode branches and the column trunk have an inclination angle α, and the inclination angle α is 30 ° to 60 °.
9. The array substrate according to claim 4, wherein the first slit electrode portion, the second slit electrode portion, the third slit electrode portion, and the fourth slit electrode portion have the same pitch between adjacent slits.
10. A display panel comprising liquid crystal molecules, a counter substrate, and the array substrate according to any one of claims 1 to 9, wherein the liquid crystal molecules are disposed between the counter substrate and the array substrate.
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| CN116699909A (en) * | 2023-08-07 | 2023-09-05 | 苏州华星光电技术有限公司 | Array substrate and display panel |
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| CN109634012A (en) * | 2019-01-25 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN110221490A (en) * | 2019-06-10 | 2019-09-10 | 惠科股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN110850647A (en) * | 2019-11-29 | 2020-02-28 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111474789A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111474779A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN114089566A (en) * | 2021-11-30 | 2022-02-25 | 长沙惠科光电有限公司 | Array substrate, display panel and display device |
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| CN116699909A (en) * | 2023-08-07 | 2023-09-05 | 苏州华星光电技术有限公司 | Array substrate and display panel |
| CN116699909B (en) * | 2023-08-07 | 2023-10-31 | 苏州华星光电技术有限公司 | Array substrate and display panel |
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