CN114695067A - Quadrupole rod control device, quadrupole rod equipment and mass spectrometer - Google Patents
Quadrupole rod control device, quadrupole rod equipment and mass spectrometer Download PDFInfo
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- H—ELECTRICITY
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Abstract
The utility model relates to a quadrupole control device, quadrupole equipment and mass spectrograph, quadrupole control device includes the host computer, data processor and amplifier circuit, send to data processor behind the host computer configuration scanning parameter, data processor carries out the partitioning with the scanning parameter according to the scanning mode, configure into the scanning coefficient, and establish the scanning time sequence according to the scanning coefficient, generate scanning signal according to the scanning time sequence, and give amplifier circuit with scanning signal transmission, enlarge and produce different voltages according to scanning signal, drive quadrupole work. Through host computer configuration parameter, data processor analysis parameter, establish the scanning time sequence that generates to different scanning coefficients inside, generate scanning signal, make amplifier circuit can produce different voltages according to scanning signal, drive quadrupole rod work, can the fast switch excitation quadrupole rod's voltage, make the quadrupole rod scan multiple ion, it is nimble to use, voltage switching speed is fast, work efficiency is high, uses convenient and reliable.
Description
Technical Field
The application relates to the technical field of mass spectrometers, in particular to a quadrupole rod control device, quadrupole rod equipment and a mass spectrometer.
Background
A mass spectrometer, also called a mass spectrometer, is an instrument that separates and detects the composition of substances according to the mass difference of substance atoms, molecules or molecular fragments based on the principle that charged particles can deflect in an electromagnetic field. The quadrupole is a main device of a mass spectrometer, ions are focused near the central axis of the quadrupole under the action of an electric field, the voltage application mode is that a group of opposite poles apply voltages with consistent polarity, adjacent poles apply voltages with opposite polarities, complex oscillation motion starts under the combined action of a radio frequency electric field and a direct current electric field, and the ions with different mass-to-charge ratios are selected by utilizing the electric field changing along with time.
In a traditional method for controlling the voltage of the quadrupole, the scanning of the quadrupole is usually controlled by building an analog circuit, however, the method has poor flexibility, complex circuit debugging, low working efficiency and unreliable use.
Disclosure of Invention
In view of the above, it is necessary to provide a quadrupole control device, a quadrupole device and a mass spectrometer, which are directed to the problem that the conventional voltage control method for quadrupole is unreliable.
A quadrupole rod control device, comprising:
configuring scanning parameters and sending the scanning parameters to an upper computer of a data processor; the scan parameters include a scan pattern;
partitioning the scanning parameters according to the scanning mode, configuring the scanning parameters into scanning coefficients, establishing a scanning time sequence according to the scanning coefficients, generating scanning signals according to the scanning time sequence, and transmitting the scanning signals to the data processor of the amplifying circuit;
the amplifying circuit generates different voltages according to the scanning signals and drives the quadrupole rods to work;
the upper computer is connected with the data processor, the data processor is connected with the amplifying circuit, and the amplifying circuit is connected with the quadrupole rod.
A quadrupole rod device comprises a quadrupole rod and a quadrupole rod control device as described above.
A mass spectrometer comprising a quadrupole rod device as described above.
The quadrupole rod control device comprises an upper computer, a data processor and an amplifying circuit, wherein the upper computer is connected with the data processor, the data processor is connected with the amplifying circuit, and the amplifying circuit is connected with the quadrupole rod. The upper computer is configured with scanning parameters and sends the scanning parameters to the data processor, the scanning parameters comprise scanning modes, the data processor divides the scanning parameters into blocks according to the scanning modes, the scanning parameters are configured into scanning coefficients, scanning time sequences are established according to the scanning coefficients, scanning signals are generated according to the scanning time sequences and are transmitted to the amplifying circuit, different voltages are generated according to the scanning signals in an amplifying mode, and the four-pole rod is driven to work. The upper computer is used for configuring parameters and issuing the parameters to the data processor, the data processor analyzes the parameters, scanning time sequences generated aiming at different scanning coefficients are built in the data processor, scanning signals are generated according to the scanning time sequences, the amplifying circuit can generate different voltages according to the scanning signals to drive the quadrupole rods to work, the voltage for exciting the quadrupole rods can be switched rapidly, the quadrupole rods can scan various ions, and the device is flexible to use, high in voltage switching speed, high in working efficiency and convenient and reliable to use.
In one embodiment, the upper computer further comprises an upper computer scanning execution module for sending execution commands to the data processor, wherein the execution commands comprise starting scanning and stopping scanning.
In one embodiment, the data processor further comprises a processor scan execution module for establishing a scan timing according to the scan coefficient according to the execution command.
In one embodiment, the upper computer further comprises an upper computer communication protocol module for encapsulating information to be sent to the data processor into a data packet according to a preset transmission protocol, and the upper computer communication protocol module is connected with the data processor.
In one embodiment, the data processor further comprises a processor communication protocol module for analyzing the received data packet and extracting data, and the processor communication protocol module is connected with the upper computer communication protocol module.
In one embodiment, the data processor further comprises a state control module, and the state control module is connected with the amplifying circuit.
In one embodiment, the amplifying circuit includes a digital-to-analog converter and a radio frequency circuit module, the data processor is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the radio frequency circuit module, and the radio frequency circuit module is connected to the quadrupole rod.
In one embodiment, the data processor is an FPGA.
Drawings
FIG. 1 is a block diagram of a quadrupole control device in one embodiment;
FIG. 2 is a schematic diagram of a quadrupole rod control device in one embodiment;
figure 3 is a flow chart of the operation of a four pole control device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described more fully below by way of examples in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In one embodiment, please refer to fig. 1, which provides a quadrupole control device, including an upper computer 110, a data processor 120, and an amplifying circuit 130, where the upper computer 110 is connected to the data processor 120, the data processor 120 is connected to the amplifying circuit 130, the amplifying circuit 130 is connected to a quadrupole 200, the upper computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120, the scanning parameters include a scanning mode, the data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures the scanning parameters into scanning coefficients, constructs a scanning timing sequence according to the scanning coefficients, generates scanning signals according to the scanning timing sequence, transmits the scanning signals to the amplifying circuit 130, amplifies the scanning signals to generate different voltages, and drives the quadrupole 200 to operate. The parameters are configured through the upper computer 110 and are issued to the data processor 120, the data processor 120 analyzes the parameters, scanning time sequences generated by different scanning coefficients are built in the data processor, scanning signals are generated according to the scanning time sequences, the amplifying circuit 130 can generate different voltages according to the scanning signals, the quadrupole rods 200 are driven to work, the voltage for exciting the quadrupole rods 200 can be switched rapidly, the quadrupole rods 200 can scan various ions, and the ion scanning device is flexible to use, high in voltage switching speed, high in working efficiency and convenient and reliable to use.
The quadrupole 200 is one of the main components of the mass spectrometer, and the fundamental principle of the quadrupole 200 scanning technology is as follows: ions are focused near the central axis of the quadrupole 200 under the action of an electric field, voltages with the same polarity are applied to one group of opposite polars, voltages with opposite polarities are applied to adjacent polars, complex oscillation motion starts under the combined action of a radio frequency electric field and a direct current electric field, and ions with different mass-to-charge ratios are selected by utilizing the electric field changing along with time. The ions from the quadrupole 200 hit the high-energy dynode to generate electrons, the electrons generate electric signals through the electron multiplier, the electric signals from the electron multiplier are sent to the computer for storage, and the signals are processed by the computer to obtain a chromatogram, a mass spectrum and other various information.
Specifically, the type and structure of the upper computer 110 are not exclusive, and in this embodiment, the upper computer 110 is a visualization platform capable of implementing human-computer interaction, and may include, for example, a main processing chip and a touch screen, where the main processing chip is used for data processing, and the touch screen is used for displaying data and receiving an operation instruction input by a user. The upper computer 110 is a master control device of a four-pole control device, the data processor 120 is used as a slave execution, the system is generally an invisible platform, all functions are realized by code development of research personnel, and the system has high-strength confidentiality and safety. The connection and communication mode of the upper computer 110 and the data processor 120 is not unique, in this embodiment, only the unique interface of the upper computer 110 and the data processor 120 can mutually transmit data, the upper computer 110 is responsible for sending commands, the data processor 120 is responsible for executing the commands to complete the work of the whole scanning system, and the upper computer 110 and the data processor 120 use a private protocol for communication, so that the safety of the system is improved. The upper computer 110 is flexible in control and operation and can realize efficient scheduling of the whole system.
Further, referring to fig. 2, the part of the upper computer 110 related to data processing may include an upper computer parameter configuration module 111, where the upper computer parameter configuration module 111 configures a scanning parameter, and sends the scanning parameter to the data processor 120, the scanning parameter is a parameter that needs to be executed, and is configured to the upper computer 110 in a simple manner, and the type of the scanning parameter is not unique. The scanning parameters may further include an initial voltage, a number of scanning protons, a difference voltage, a scanning trend, an initial settling time, a voltage interval settling time, a single proton scanning time, and a single/cyclic scanning selection, wherein a user may only set the scanning parameters used for this scanning, and others all maintain default values. The scanning parameters are selected and configured according to the needs of the user, all the parameters can be sent as 2 bytes, the 2 bytes are appointed by the upper computer 110 and the lower computer, and after configuration, the lower computer takes the 2 bytes as the configuration values of the parameters. It can be understood that, in other embodiments, the structure of the upper computer 110, the structure of the scanning parameters, or the configuration of the scanning parameters may also be other, and may be adjusted according to actual requirements, as long as those skilled in the art think it can be implemented.
The data processor 120 blocks the scan parameters according to a scan pattern, configures scan coefficients, constructs a scan timing according to the scan coefficients, generates a scan signal according to the scan timing, and transmits the scan signal to the amplifying circuit 130. Referring to fig. 2, the data processor 120 includes a parameter analyzing module 122, a processor parameter configuring module 123 and an amplifying circuit control module 125, the parameter analyzing module 122 divides the scanning parameters into blocks according to the scanning mode, and the processor parameter configuring module 123 places the contents of the parameter blocks into corresponding scanning coefficients according to the current configuration requirements, configures the scanning coefficients, and waits for the scanning trigger. The parameter analysis module 122 further constructs a scan timing sequence according to the scan coefficients, generates a scan signal according to the scan timing sequence, and transmits the scan signal to the amplifying circuit 130. Specifically, the parameter analyzing module 122 is configured to analyze and partition the scanning parameters issued by the upper computer 110, distinguish different parameter blocks from the scanning parameters according to the scanning mode, calculate a value sent to the amplifying circuit 130 and query a corresponding gain and bias voltage according to the voltage parameter, calculate a real time corresponding to each time parameter according to the issued time parameter and the clock count of itself, and construct an overall scanning timing sequence according to the initial voltage, the number of scanning protons, the differential voltage, and the scanning trend. The amplifying circuit control module 125 generates a scan signal according to the scan timing and transmits the scan signal to the amplifying circuit 130.
The amplifier circuit control module 125 has a different structure and performs different operations according to the structure of the amplifier circuit 130. In this embodiment, when the amplifying circuit 130 includes a DAC (Digital-to-Analog Converter), the amplifying circuit control module 125 is a DAC control module, and the DAC control module sends the Digital signal to the DAC according to the scan requirement during the scan process according to the timing requirement of different DACs, so as to complete the sequential control of voltage output by the data processor 120.
The amplifying circuit 130 generates different voltages according to the scan signal to drive the quadrupole rods 200 to operate. The structure of the amplifying circuit 130 is not unique, in this embodiment, referring to fig. 2, the amplifying circuit 130 includes a DAC module and a radio frequency circuit module 132, the DAC module converts the digital signal from the data processor 120 into an analog voltage signal, and the radio frequency circuit module 132 amplifies the analog signal sent from the DAC module to a voltage amplitude required by the quadrupole rod 200 to drive the quadrupole rod 200 to operate.
The type of the data processor 120 is not unique, in this embodiment, the data processor 120 is an FPGA (Field Programmable Gate Array), the quadrupole rod control device uses the architecture of the upper computer 110+ the FPGA to implement the control scanning of the quadrupole rod 200, the FPGA can implement the high-speed correspondence of the system, and the scanning voltage switching control can be implemented as nanosecond-level control. In the embodiment, the FPGA uses a 100MHz system clock, and the accurate control of the FPGA can reach 10ns level. Host computer 110 control and flexible operation can realize the high-efficient dispatch of entire system, use FPGA to realize the scanning in the system, belong to hardware programming and realize that its portability is strong, and security is strong, and in addition, the quadrupole 200 scanning system of FPGA design can adapt to the realization environment under the multiple host computer 110 platform according to the different interfaces of different host computers 110, saves development cost.
In one embodiment, referring to fig. 2, the upper computer 110 further includes an upper computer scan execution module 112 that sends an execution command to the data processor 120, where the execution command includes starting scanning and stopping scanning.
The host scan execution module 112 may issue an execution command to the data processor 120, where the execution command includes starting scanning and stopping scanning, so as to control the data processor 120 to start or stop working. Further, when the upper computer 110 further includes an upper computer parameter configuration module 111, the upper computer scanning execution module 112 is connected to the upper computer parameter configuration module 111, the upper computer parameter configuration module 111 configures the scanning parameters to be executed to the upper computer 110 in a simple manner, and the upper computer scanning execution module 112 is an execution command issued to the data processor 120 at the end of the upper computer 110, and includes starting scanning and stopping scanning.
In one embodiment, referring to fig. 2, the data processor 120 further includes a processor scan execution module 124 for establishing a scan timing according to the scan coefficients according to the execution command.
When the upper computer 110 includes the upper computer scanning execution module 112 that sends an execution command to the data processor 120, the data processor 120 also sets a corresponding processor scanning execution module 124, which is used to establish a scanning time sequence according to the scanning coefficients after receiving the execution command, so as to implement the on-demand work of the processor scanning execution module 124 and reduce the workload. Specifically, the processor scan execution module 124 executes the scanning operation according to a scan start command issued by the upper computer 110, specifically, sends different voltage values to the amplifying circuit 130 according to a time convention and a sequence, and forcibly stops the scanning process according to a scan stop command issued by the upper computer 110, and the scanning parameters are kept unchanged. Further, when the data processor 120 further includes a parameter analyzing module 122, a processor parameter configuring module 123 and an amplifying circuit control module 125, the parameter analyzing module 122 is connected to the processor parameter configuring module 123, the processor parameter configuring module 123 is connected to the processor scanning executing module 124, and the processor scanning executing module 124 is connected to the amplifying circuit control module 125, and the functions of the modules have been described in detail before, and are not described herein again.
In an embodiment, referring to fig. 2, the upper computer 110 further includes an upper computer communication protocol module 113 that encapsulates information to be sent to the data processor 120 into data packets according to a preset transmission protocol, and the upper computer communication protocol module 113 is connected to the data processor 120. The upper computer communication protocol module 113 encapsulates information to be sent to the data processor 120 into a data packet according to a preset transmission protocol, and then sends the data packet to the data processor 120, so that the safety and stability of communication can be improved.
Specifically, the upper computer communication protocol module 113 encapsulates the information sent to the data processor 120 according to a preset transmission protocol, where the preset transmission protocol may be a private protocol, and the security is higher. The communication mode between the upper computer 110 and the data processor 120 is not unique, in this embodiment, the upper computer 110 and the data processor 120 use rg45 network transmission, and the protocol uses udp transmission protocol to realize gigabit ethernet transmission. It is understood that in other embodiments, the upper computer 110 and the data processor 120 can communicate in other manners, as long as the implementation is considered by those skilled in the art. In an extensible manner, when the upper computer 110 further includes an upper computer parameter configuration module 111 and an upper computer scanning execution module 112, the upper computer parameter configuration module 111 is connected to the upper computer scanning execution module 112, the upper computer scanning execution module 112 is connected to the upper computer communication protocol module 113, and functions of each module have been described in detail before, and are not described herein again.
In one embodiment, please refer to fig. 2, the data processor 120 further includes a processor communication protocol module 121 for parsing the received data packet and extracting data, and the processor communication protocol module 121 is connected to the upper computer communication protocol module 113.
When the upper computer 110 further includes an upper computer communication protocol module 113 that encapsulates information to be sent to the data processor 120 into a data packet according to a preset transmission protocol, correspondingly, the data processor 120 also includes a processor communication protocol module 121 connected to the upper computer communication protocol module 113, and the processor communication protocol module 121 parses the received data packet and extracts data. The protocol content adopted by the upper computer communication protocol module 113 and the processor communication protocol module 121 can be the same, so that data transmission can be better carried out. The processor communication protocol module 121 can realize the analysis of the data packet issued by the upper computer 110 at the data processor 120 end, extract the actual data, add a private protocol in addition to the udp transmission protocol, and define the verification of the packet header, the packet trailer and the packet, so as to further improve the transmission data security.
In an extensible manner, when the data processor 120 further includes a parameter analyzing module 122, a processor parameter configuring module 123, an amplifying circuit control module 125, and a processor scanning executing module 124, the processor communication protocol module 121 is connected to the parameter analyzing module 122, the parameter analyzing module 122 is connected to the processor parameter configuring module 123, the processor parameter configuring module 123 is connected to the processor scanning executing module 124, and the processor scanning executing module 124 is connected to the amplifying circuit control module 125.
In one embodiment, referring to fig. 2, the data processor 120 further includes a state control module 126, and the state control module 126 is connected to the amplifying circuit 130. The state control module 126 can monitor the working state of the amplifying circuit 130, further, the state control module 126 can be connected to the upper computer 110, when abnormality is found, the abnormal information is reported to the upper computer 110, the upper computer 110 can display the abnormal condition, or the abnormal condition is reported to other devices for display, so as to remind a worker to process in time.
Specifically, the state control module 126 is connected to the amplifying circuit 130, and may be connected to a DAC in the amplifying circuit 130, and the state control module 126 is further connected to the upper computer 110. The state control module 126 can monitor the overall system state before, during, and after the scanning process, including monitoring the parameter configuration status, the transmission timing state, the DAC transmission state, and the like. The parameter configuration monitoring means that the lower computer transmits the received parameter configuration back to the upper computer 110, the upper computer 110 compares and judges the issued parameters, whether the data processor 120 receives the parameters normally or not, after the parameters issued by the upper computer 110 appear, the data processor 120 does not respond or the responded parameters are inconsistent with the issued parameters, and the upper computer 110 judges that the issued parameters are wrong at this time and issues the parameters again. The transmission timing state monitoring is performed by using a check bit in the transmission protocol, and if the check bit is abnormal, the transmission is judged to be present or not, and the state is reported to the upper computer 110. The DAC transmission state monitoring means monitoring an abnormality indication pin of the DAC chip, and reporting the abnormality indication pin to the upper computer 110 when the abnormality is detected. It is understood that in other embodiments, the state control module 126 may be connected to other devices to achieve other functions, as long as the implementation is deemed possible by one skilled in the art.
In one embodiment, referring to fig. 2, the amplifying circuit 130 includes a digital-to-analog converter 131 and a radio frequency circuit module 132, the data processor 120 is connected to the digital-to-analog converter 131, the digital-to-analog converter 131 is connected to the radio frequency circuit module 132, and the radio frequency circuit module 132 is connected to the quadrupole rod 200.
Specifically, the digital-to-analog converter 131 is a DAC module, the DAC module converts the digital signal from the data processor 120 into an analog voltage signal, and the rf circuit module 132 amplifies the analog signal sent from the DAC module to a voltage amplitude required by the quadrupole rod 200 to drive the quadrupole rod 200 to operate. Further, the voltage value is multiplied to the voltage required for driving the quadrupole 200, and the oscillation circuit is used for driving the quadrupole 200 to operate. The oscillation circuit is a sine wave generated by a DDS (Direct Digital Frequency Synthesis, Direct Digital Frequency synthesizer algorithm) and acts on a Direct current amplifier to generate alternating current with a peak value of 1000v, and the oscillation Frequency of the alternating current is 1 MHz. It is understood that in other embodiments, the amplifying circuit 130 may have other structures as long as the implementation is considered by those skilled in the art.
In one embodiment, the data processor 120 is an FPGA. The quadrupole rod control device adopts the framework of the upper computer 110+ FPGA to realize the control scanning of the quadrupole rod 200, the FPGA can realize the high-speed correspondence of the system, and the control of switching of scanning voltage can be realized in nanosecond level. In the embodiment, the FPGA uses a 100MHz system clock, and the accurate control of the FPGA can reach 10ns level. The upper computer 110 is flexible to control and operate, can realize high-efficient scheduling of the whole system, uses the FPGA to realize scanning in the system, belongs to hardware programming realization, and has strong portability and strong security and confidentiality, in addition, the quadrupole 200 scanning system designed by the FPGA can adapt to the realization environment under various upper computer 110 platforms according to different interfaces of different upper computers 110, and the development cost is saved.
For a better understanding of the above embodiments, the following detailed description is given in conjunction with a specific embodiment. In one embodiment, referring to fig. 2, the quadrupole control device includes an upper computer 110, a data processor 120 and an amplifying circuit 130, and the data processor 120 is an FPGA. The upper computer 110 is used as a main control unit to realize man-machine interaction, a visual platform, the FPGA is used as a slave execution unit, the system is an invisible platform, all functions are developed and realized by research personnel codes, and the system has high-strength confidentiality and safety. The upper computer 110 and the FPGA only have unique interfaces and can mutually transmit data, the upper computer 110 is responsible for sending commands, the FPGA is responsible for executing the commands to complete the work of the whole scanning system, the upper computer 110 and the FPGA communicate by using a proprietary protocol to increase the safety of the system, and the amplifying circuit 130 and the quadrupole rod 200 are function realization units. The upper computer 110 is connected with the FPGA chip through a hardware interface, the FPGA chip is connected with the amplifying circuit 130 through a hardware interface, and the amplifying circuit 130 is connected with the quadrupole rod 200.
The upper computer 110 comprises an upper computer parameter configuration module 111, an upper computer scanning execution module 112 and an upper computer communication protocol module 113, the upper computer parameter configuration module 111 configures parameters to be executed to the upper computer 110 in a simple mode, and basic parameters comprise a scanning mode, initial voltage, the number of scanned protons, difference voltage, a scanning trend, initial stabilization time, voltage interval stabilization time, single proton scanning time and single/cycle scanning selection. All the parameters are selected and configured according to the needs of the user, all the parameters are sent to be 2 bytes, the user only needs to set the parameters used in the scanning, the other parameters keep default values, the 2 bytes are agreed by the upper computer 110 and the lower computer, and after configuration, the lower computer takes the 2 bytes as the configuration values of the parameters. The upper computer scanning execution module 112 issues execution commands including start scanning and stop scanning to the FPGA at the upper computer 110. The upper computer communication protocol module 113 encapsulates the information issued to the FPGA according to a transmission protocol, in this embodiment, the upper computer 110 and the FPGA use rg45 network transmission, and the protocol uses a udp transmission protocol, so as to implement gigabit ethernet transmission. Information mutually transmitted by the upper computer 110 and the FPGA can be packaged and analyzed according to a protocol, and the safety and the stability of communication are guaranteed.
The FPGA includes a processor communication protocol module 121, a parameter parsing module 122, a processor parameter configuration module 123, a processor scan execution module 124, an amplification circuit control module 125, and a state control module 126. The protocol content of the processor communication protocol module 121 is the same as that of the upper computer communication protocol module 113, the analysis of the data packet sent by the upper computer is realized at the FPGA end, the actual data is extracted, a private protocol is added to the protocol except for the udp transmission protocol, and the verification of the header, the trailer and the packet is defined.
The parameter analyzing module 122 analyzes and divides the scanning parameters issued by the upper computer 110 into blocks, distinguishes the scanning parameters into different parameter blocks according to the scanning mode, calculates the numerical value sent to the DAC and the gain and bias voltage corresponding to the query according to the voltage parameter, calculates the real time corresponding to each time parameter according to the issued time parameter and the clock count thereof, and constructs the whole scanning time sequence according to the initial voltage, the number of scanning protons, the difference voltage and the scanning trend. The parameter analyzing module 122 divides the received parameters into different parameter blocks at the FPGA end according to modes, and in the embodiment, there are mainly full scan and point scan, but the embodiment is not limited to these two scan modes, and can also be extended to more scan modes.
The processor scanning execution module 124 executes the scanning operation according to a start command issued by the upper computer 110, specifically, sends different voltage values to the DAC module according to time convention and sequence, and monitors whether the flow is correct in real time. And forcibly stopping the scanning process according to a stop command issued by the upper computer 110, wherein the scanning parameters are kept unchanged. And a scanning time sequence is constructed according to the current scanning coefficient after receiving a scanning command issued by the upper computer 110, and the FPGA uses a 100MHz system clock and can achieve accurate control in the level of 10 ns.
The amplifying circuit control module 125 may specifically be a DAC control module, and in the scanning process, according to the timing requirements of different DACs, the digital signal is sent to the DAC according to the scanning requirements, so as to complete the sequential control of voltage output by the FPGA. And specifically, transmitting the DAC according to the required time sequence of the DAC according to different voltage values given by the scanning time sequence, and the inquired voltage gain value and voltage offset value.
The state control module 126 monitors the overall system state before, during, and after the scanning process, including monitoring the parameter configuration status, the transmission timing state, and the DAC transmission state. Wherein, parameter configuration monitoring comprises: the lower computer configures the received parameters and then transmits the parameters back to the upper computer 110, the upper computer 110 compares the parameters and judges whether the issued parameter FPGA receives the parameters normally, after the parameters are issued by the upper computer 110, the FPGA does not respond or the parameters responded are inconsistent with the issued parameters, and the upper computer 110 judges that the issued parameters are wrong and issues the parameters again. The transmission timing state monitoring is performed by using a check bit in the transmission protocol, and if the check bit is abnormal, the transmission is judged to be present or not, and the state is reported to the upper computer 110. The DAC transmission state monitoring means monitoring an abnormality indication pin of the DAC chip, and reporting the abnormality indication pin to the upper computer 110 when the abnormality is detected.
The amplifying circuit 130 comprises a digital-to-analog converter 131 and a radio frequency circuit module 132, the DAC module converts the digital signal of the FPGA into an analog voltage signal, and the radio frequency circuit module 132 amplifies the analog signal sent by the DAC to a voltage amplitude value required by the quadrupole rod 200 and generates an oscillator circuit to drive the quadrupole rod 200 to work. The oscillation circuit is a sine wave generated by DDA and acts with a direct current amplifier to generate alternating current with a peak value of 1000v, and the oscillation frequency of the oscillation circuit is 1 MHz. Quadrupole 200 is the device of mass spectrometer screening ion, and the oscillating voltage of different amplitudes can make different protons pass through.
Referring to fig. 3, the working flow of the four-pole control device includes the following steps:
step S201, the upper computer is in a waiting state;
step S202, configuring required parameters on an upper computer, encapsulating and issuing a protocol;
step S203, the FPGA resolves the data packet according to the communication protocol, resolves the issued effective data according to the private protocol, and extracts the parameters in the data packet;
step S204, partitioning the parameters to configure the parameters into scanning coefficients;
s205, the FPGA waits for an execution command of the upper computer;
step S206, the FPGA executes scanning logic according to the scanning coefficient, and controls different time points to transmit different values to the DAC;
step S207, if the scanning is finished, returning to the step S201, otherwise, continuing to scan;
step S208, if a stop command is received, returning to the step S201, otherwise, continuing to scan;
step S209, the DAC converts the digital signal into an analog signal and transmits the analog signal to the radio frequency circuit;
in step S210, the rf circuit multiplies the voltage value to the voltage required for driving the quadrupole rods, and drives the quadrupole rods to operate using the oscillation circuit.
The quadrupole rod control device comprises an upper computer 110, a data processor 120 and an amplifying circuit 130, wherein the upper computer 110 is connected with the data processor 120, the data processor 120 is connected with the amplifying circuit 130, and the amplifying circuit 130 is connected with the quadrupole rod 200. The upper computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120, the scanning parameters comprise a scanning mode, the data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures the scanning parameters into scanning coefficients, constructs a scanning time sequence according to the scanning coefficients, generates scanning signals according to the scanning time sequence, transmits the scanning signals to the amplifying circuit 130, amplifies the scanning signals to generate different voltages, and drives the quadrupole rod 200 to work. The parameters are configured through the upper computer 110 and are issued to the data processor 120, the data processor 120 analyzes the parameters, scanning time sequences generated by different scanning coefficients are built in the data processor, scanning signals are generated according to the scanning time sequences, the amplifying circuit 130 can generate different voltages according to the scanning signals, the quadrupole rods 200 are driven to work, the voltage for exciting the quadrupole rods 200 can be switched rapidly, the quadrupole rods 200 can scan various ions, and the ion scanning device is flexible to use, high in voltage switching speed, high in working efficiency and convenient and reliable to use.
In one embodiment, a quadrupole rod device is provided comprising a quadrupole rod 200 and a quadrupole rod control apparatus as described above.
The quadrupole rod device comprises an upper computer 110, a data processor 120 and an amplifying circuit 130, wherein the upper computer 110 is connected with the data processor 120, the data processor 120 is connected with the amplifying circuit 130, and the amplifying circuit 130 is connected with a quadrupole rod 200. The upper computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120, the scanning parameters comprise a scanning mode, the data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures the scanning parameters into scanning coefficients, constructs a scanning time sequence according to the scanning coefficients, generates scanning signals according to the scanning time sequence, transmits the scanning signals to the amplifying circuit 130, amplifies the scanning signals to generate different voltages, and drives the quadrupole rod 200 to work. The parameters are configured through the upper computer 110 and are issued to the data processor 120, the data processor 120 analyzes the parameters, scanning time sequences generated according to different scanning coefficients are built in the data processor, scanning signals are generated according to the scanning time sequences, the amplifying circuit 130 can generate different voltages according to the scanning signals, the quadrupole rods 200 are driven to work, the voltage for exciting the quadrupole rods 200 can be switched rapidly, the quadrupole rods 200 can scan various ions, and the ion scanning device is flexible to use, high in voltage switching speed, high in working efficiency and convenient and reliable to use.
In one embodiment, a mass spectrometer is provided comprising a quadrupole rod device as described above.
The mass spectrometer comprises an upper computer 110, a data processor 120 and an amplifying circuit 130, wherein the upper computer 110 is connected with the data processor 120, the data processor 120 is connected with the amplifying circuit 130, and the amplifying circuit 130 is connected with a quadrupole rod 200. The upper computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120, the scanning parameters comprise a scanning mode, the data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures the scanning parameters into scanning coefficients, constructs a scanning time sequence according to the scanning coefficients, generates scanning signals according to the scanning time sequence, transmits the scanning signals to the amplifying circuit 130, amplifies the scanning signals to generate different voltages, and drives the quadrupole rod 200 to work. The parameters are configured through the upper computer 110 and are issued to the data processor 120, the data processor 120 analyzes the parameters, scanning time sequences generated by different scanning coefficients are built in the data processor, scanning signals are generated according to the scanning time sequences, the amplifying circuit 130 can generate different voltages according to the scanning signals, the quadrupole rods 200 are driven to work, the voltage for exciting the quadrupole rods 200 can be switched rapidly, the quadrupole rods 200 can scan various ions, and the ion scanning device is flexible to use, high in voltage switching speed, high in working efficiency and convenient and reliable to use.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A quadrupole rod control device, comprising:
configuring scanning parameters and sending the scanning parameters to an upper computer of a data processor; the scan parameters include a scan pattern;
partitioning the scanning parameters according to the scanning mode, configuring the scanning parameters into scanning coefficients, establishing a scanning time sequence according to the scanning coefficients, generating scanning signals according to the scanning time sequence, and transmitting the scanning signals to the data processor of the amplifying circuit;
the amplifying circuit generates different voltages according to the scanning signals and drives the quadrupole rods to work;
the upper computer is connected with the data processor, the data processor is connected with the amplifying circuit, and the amplifying circuit is connected with the quadrupole rod.
2. The quadrupole rod control device of claim 1, wherein the host computer further comprises a host computer scan execution module for sending execution commands to the data processor, wherein the execution commands comprise start scanning and stop scanning.
3. The quadrupole control device of claim 2, wherein the data processor further comprises a processor scan execution module configured to establish a scan sequence in accordance with the scan coefficients based on the execution command.
4. The quadrupole rod control device of claim 1, wherein the upper computer further comprises an upper computer communication protocol module for encapsulating information to be sent to the data processor into data packets according to a preset transmission protocol, and the upper computer communication protocol module is connected with the data processor.
5. A quadrupole rod control device according to claim 4, wherein the data processor further comprises a processor communication protocol module for parsing the received data packets and extracting the data, the processor communication protocol module being connected to the upper computer communication protocol module.
6. The quadrupole rod control device of claim 1, wherein the data processor further comprises a state control module, the state control module being coupled to the amplification circuit.
7. The quadrupole rod control device of claim 1, wherein the amplifying circuit comprises a digital-to-analog converter and a radio frequency circuit module, the data processor is connected with the digital-to-analog converter, the digital-to-analog converter is connected with the radio frequency circuit module, and the radio frequency circuit module is connected with the quadrupole rod.
8. A quadrupole rod control device according to any of claims 1-7, wherein the data processor is an FPGA.
9. Quadrupole rod device, comprising a quadrupole rod and a quadrupole rod control device according to any of claims 1-8.
10. A mass spectrometer comprising the quadrupole rod set forth in claim 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117476431A (en) * | 2023-12-28 | 2024-01-30 | 杭州泽天春来科技股份有限公司 | Quadrupole radio frequency power supply scanning control method, system and readable storage medium |
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