CN114664271B - Common voltage correction circuit, display panel and display device - Google Patents
Common voltage correction circuit, display panel and display device Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
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Abstract
The application discloses public voltage correction circuit, display panel and display device, wherein, public voltage correction circuit includes: the offset detection circuit is used for determining the direct current offset degree of two ends of the liquid crystal layer, which is influenced by the environmental temperature, according to the first preset gray scale voltage and the second preset gray scale voltage and outputting an offset detection signal; and the input end of the correction voltage generating circuit is connected with the output end of the offset detection circuit, the output end of the correction voltage generating circuit is connected with the common electrode wire, and the correction voltage generating circuit is used for generating corresponding correction voltage according to the offset detection signal and outputting the correction voltage to the common electrode wire so as to correct the common voltage received by the common electrode wire until the degree of direct current offset influenced by the ambient temperature at the two ends of the liquid crystal layer is eliminated. According to the scheme, the problem that the display effect of the liquid crystal display panel is influenced by the ambient temperature can be solved.
Description
Technical Field
The present disclosure relates to display panel technologies, and in particular, to a common voltage correction circuit, a display panel and a display device.
Background
At present, under a high temperature or a low temperature, a dc bias voltage may exist in a liquid crystal layer of a liquid crystal display panel, so that a rotation degree of liquid crystal molecules may not be correctly changed along with a change of a driving voltage difference, thereby causing a poor display effect of the liquid crystal display panel.
Disclosure of Invention
The main purpose of this application is to provide a public voltage correction circuit, aim at solving the problem that ambient temperature influences the display effect of liquid crystal display panel.
In order to achieve the above object, the present application provides a common voltage correction circuit applied to a display panel, the display panel including: public electrode line, grey level voltage generating circuit and public voltage generating circuit, grey level voltage generating circuit is used for exporting first predetermined grey level voltage and the predetermined grey level voltage of second, public voltage generating circuit is used for exporting public voltage to public electrode line, public voltage correction circuit includes:
the offset detection circuit is used for determining the DC offset degree of two ends of the liquid crystal layer, which is influenced by the ambient temperature, according to the first preset gray scale voltage and the second preset gray scale voltage and outputting an offset detection signal; and the number of the first and second groups,
the correction voltage generating circuit is used for generating corresponding correction voltage according to the offset detection signal and outputting the correction voltage to the public electrode wire so as to correct the public voltage received by the public electrode wire until the direct current offset degree influenced by the environmental temperature at the two ends of the liquid crystal layer is eliminated.
Optionally, the offset detection circuit comprises:
the input end of the first offset detection circuit is used for accessing the first preset gray scale voltage, and the first offset detection circuit is used for determining the DC offset degree of the first preset gray scale voltage according to the first preset gray scale voltage and outputting a first offset degree detection signal;
the input end of the first offset detection circuit is used for accessing the second preset gray scale voltage, and the second offset detection circuit is used for determining the DC offset degree of the second preset gray scale voltage according to the second preset gray scale voltage and outputting a second offset degree detection signal; and the number of the first and second groups,
and the first input end and the second input end of the direct current bias determining circuit are respectively connected with the output end of the first deviation detecting circuit and the output end of the second deviation detecting circuit, and the direct current bias determining circuit is used for determining the direct current deviation degree influenced by the environmental temperature at the two ends of the liquid crystal layer according to the first deviation degree detecting signal and the second deviation degree detecting signal and outputting the deviation detecting signal.
Optionally, the input terminal of the first offset detection circuit includes a positive input terminal and a negative input terminal, and the first offset detection circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier;
the first end of the first resistor is the positive input end of the first offset detection circuit, the second end of the first resistor, the inverting input end of the first operational amplifier and the first end of the second resistor are interconnected, the second end of the second resistor is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is the output end of the first offset detection circuit, the first end of the third resistor is the negative input end of the first offset detection circuit, the second end of the third resistor, the non-inverting input end of the first operational amplifier and the first end of the fourth resistor are interconnected, and the second end of the fourth resistor is grounded.
Optionally, the input terminal of the second offset detection circuit includes a positive input terminal and a negative input terminal, and the second offset detection circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second operational amplifier;
the first end of the fifth resistor is the positive input end of the second offset detection circuit, the second end of the fifth resistor, the inverting input end of the second operational amplifier and the first end of the sixth resistor are interconnected, the second end of the sixth resistor is connected with the output end of the second operational amplifier, the output end of the second operational amplifier is the output end of the second offset detection circuit, the first end of the seventh resistor is the negative input end of the second offset detection circuit, the second end of the seventh resistor, the non-inverting input end of the second operational amplifier and the first end of the eighth resistor are interconnected, and the second end of the eighth resistor is grounded.
Optionally, the dc offset determination circuit includes:
and a positive phase input end, a negative phase input end and an output end of the third operational amplifier are respectively a first input end, a second input end and an output end of the direct current bias determination circuit.
Optionally, the correction voltage generation circuit includes:
the memory stores a mapping table of the preset DC offset degree-the preset correction voltage value;
the input end of the correction voltage generation circuit is connected with the output end of the offset detection circuit, the data end of the correction voltage generation circuit is in communication connection with the memory, and the correction voltage generation circuit is used for calling the preset direct current offset degree-preset correction voltage value mapping table according to the offset detection signal so as to search and obtain a preset correction voltage value corresponding to the offset detection signal and generate and output a corresponding correction voltage;
the input end of the digital-to-analog conversion circuit is connected with the output end of the correction voltage generation circuit, the output end of the digital-to-analog conversion circuit is the output end of the correction voltage generation circuit, and the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the accessed correction voltage and then outputting the correction voltage.
Optionally, the common voltage correction circuit further includes:
the first input end and the second input end of the buffer circuit are respectively connected with the output end of the correction voltage generating circuit and the output end of the public voltage generating circuit, the output end of the buffer circuit is connected with the public electrode wire, and the buffer circuit is used for correcting the public voltage according to the correction voltage, buffering the corrected public voltage signals and outputting the public voltage signals to the public electrode wire.
The present invention also provides a display panel, including:
a common electrode line;
the gray scale voltage generating circuit is used for outputting a first preset gray scale voltage and a second preset gray scale voltage;
a common voltage generating circuit connected to the common electrode line, for outputting a common voltage to the common electrode line: and the number of the first and second groups,
as the above-mentioned common voltage correction circuit, the common voltage correction circuit is connected to the common electrode line, the gray scale voltage generation circuit, and the common voltage generation circuit, respectively.
Optionally, the grayscale voltage generating circuit is configured to output N preset grayscale voltages, where N is a positive integer;
the preset gray scale voltage with the minimum voltage value in the N paths of preset gray scale voltages is the first preset gray scale voltage, and the preset gray scale voltage with the maximum voltage value in the N paths of preset gray scale voltages is the second preset gray scale voltage.
The invention also provides a display device which comprises the display panel.
This application technical scheme is through adopting skew detection circuitry to according to first predetermine grey level voltage with grey level voltage is predetermine to the second, confirms the direct current skew degree that the liquid crystal layer both ends are influenced by ambient temperature to output skew detected signal to correction voltage production circuit, so that correction voltage production circuit generates corresponding correction voltage and exports extremely public electrode line, with right public electrode line received public voltage rectifies, makes the public voltage after the correction can carry out the neutralization to the direct current offset voltage that brings because of unnecessary impurity electric charge, thereby has eliminated the influence of direct current offset voltage to the liquid crystal molecule, has also eliminated the direct current skew degree that the liquid crystal layer both ends are influenced by ambient temperature, and then has solved the problem that ambient temperature influences the liquid crystal display panel display effect. In addition, this application technical scheme presets grey scale voltage for automatic acquisition two ways and eliminates direct current skew, need not to set up ambient temperature detection module, is favorable to reducing the shared PCB area of this application public voltage correction circuit, and owing to for automatic acquisition, makes this application still can carry out real-time correction to public voltage along with ambient temperature's transform automatically to thoroughly reduce ambient temperature to the influence of liquid crystal layer to minimum, therefore be favorable to improving the display stability of liquid crystal display panel under full service temperature interval.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of a common voltage calibration circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of another embodiment of a common voltage calibration circuit according to the present application;
FIG. 3 is a schematic circuit diagram of a common voltage calibration circuit according to another embodiment of the present application;
fig. 4 is a block diagram of a display panel according to an embodiment of the present disclosure.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
50 | Gray scale |
| 11 | First |
60 | Common |
| 12 | Second offset detection circuit | U1 | D flip-flop |
| 13 | Direct current bias determining circuit | A1 | A first |
| 20 | Correction voltage generating circuit | A2 | A second |
| 21 | Memory device | A3 | Third |
| 22 | Correction voltage generating circuit | A4 | A fourth |
| 23 | Digital-to-analog conversion circuit | VCOM | |
| 30 | Buffer circuit | R1~R12 | First to |
| 40 | Common electrode wire |
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In addition, descriptions in this application as to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The first embodiment is as follows:
the application provides a public voltage correction circuit which can be applied to a liquid crystal display panel.
The liquid crystal display panel may include: the device comprises a common electrode wire, a gray scale voltage generating circuit and a common voltage generating circuit, wherein the gray scale voltage generating circuit is used for outputting a first preset gray scale voltage and a second preset gray scale voltage, and the common voltage generating circuit is used for outputting a common voltage to the common electrode wire. When the liquid crystal display panel is in a high temperature or low temperature environment, the TFT characteristics shift, the electron mobility and other characteristics change, so that the amount of unnecessary impurity charges existing in the liquid crystal cell increases, and a dc bias voltage exists on both sides of the liquid crystal layer, and the rotation degree of the liquid crystal molecules can no longer be correctly changed along with the change of the driving voltage difference. For example, after the same still image is displayed for a period of time by using the liquid crystal display device in a high temperature environment, an afterimage (i.e., image sticking) may occur, and at this time, even if the content of the display screen is changed, a trace of the previous still image can still be seen on the screen of the liquid crystal display device, which is a phenomenon of the high temperature afterimage of the liquid crystal display panel.
In view of this problem, referring to fig. 1 to 3, in an embodiment, the common voltage correction circuit includes:
the offset detection circuit 10 is configured to determine a dc offset degree of two ends of the liquid crystal layer, which is affected by an ambient temperature, according to the first preset gray scale voltage and the second preset gray scale voltage, and output an offset detection signal, wherein a first input end and a second input end of the offset detection circuit 10 are respectively connected to the gray scale voltage generation circuit 50 so as to be respectively connected to the first preset gray scale voltage and the second preset gray scale voltage; and the number of the first and second groups,
the input end of the correction voltage generation circuit 20 is connected to the output end of the offset detection circuit 10, the output end of the correction voltage generation circuit 20 is connected to the common electrode line 40, and the correction voltage generation circuit 20 is configured to generate a corresponding correction voltage according to the offset detection signal and output the correction voltage to the common electrode line 40, so as to correct the common voltage VCOM received by the common electrode line 40 until the degree of dc offset affected by the ambient temperature at the two ends of the liquid crystal layer is eliminated.
It should be noted that the gray scale voltage generating circuit 50 may output N predetermined gray scale voltages with sequentially increasing voltage values, and the number of N may be determined by the color depth (Bit) of the display panel. For example: in the 8-Bit display panel, the grayscale voltage generating circuit 50 can output 256 preset grayscale voltages with sequentially increasing voltage values, wherein the 1 st preset grayscale voltage value is the minimum and is used for correspondingly controlling the liquid crystal layer not to turn over; the 256 th preset gray scale voltage value is the maximum value to control the liquid crystal layer to generate maximum deflection. Under normal temperature, in the N preset grayscale voltages, a voltage difference value between a preset grayscale voltage with a larger voltage value and a preset grayscale voltage with a corresponding smaller voltage value is a preset voltage difference value, for example: the voltage difference value of the first preset gray scale voltage and the 256 th preset gray scale voltage; or, the voltage difference value of the second path of preset gray scale voltage and the 255 th path of preset gray scale voltage; or, the voltage difference between the third preset grayscale voltage and the 254 th preset grayscale voltage, etc. Therefore, if there is a dc bias voltage at the two ends of the liquid crystal layer, the dc bias voltage is reflected on the predetermined voltage difference, which changes the predetermined voltage difference, so that the offset detection circuit 10 can detect the dc bias voltage at the two ends of the liquid crystal layer by detecting the first predetermined gray scale voltage and the second predetermined gray scale voltage.
In this embodiment, the first predetermined gray scale voltage and the second predetermined gray scale voltage may be two predetermined gray scale voltages with a larger voltage difference or a largest voltage difference among the N predetermined gray scale voltages. The offset detection circuit 10 may operate a corresponding hardware circuit or a software program or algorithm, respectively determine the magnitude of the influence of the dc bias voltage on the first preset gray scale voltage and the second preset gray scale voltage at the ambient temperature, and further determine the degree of the influence of the dc bias voltage on the whole of the two ends of the liquid crystal layer at the ambient temperature, i.e., the dc offset degree, according to the determination result, and output an offset detection signal representing the dc offset degree; the magnitude of the predetermined gray scale voltage affected by the dc offset voltage can be divided into positive offset (increase) and negative offset (decrease).
The method specifically comprises the following steps: when the first preset gray scale voltage is determined to generate positive offset, the second preset gray scale voltage generates positive offset, and the positive offset of the first preset gray scale voltage is greater than that of the second preset gray scale voltage; alternatively, when it is determined that the first preset gray scale voltage generates a positive offset, the second preset gray scale voltage does not generate an offset or generates a negative offset, the dc offset degree may be a positive dc offset degree, and the offset detection circuit 10 may output an offset detection signal corresponding to the positive dc offset degree. When the first preset gray scale voltage is determined not to generate offset, the second preset gray scale voltage generates negative offset; or when the first preset gray scale voltage is determined to generate positive offset, the second preset gray scale voltage generates positive offset, and the positive offset of the first preset gray scale voltage is smaller than that of the second preset gray scale voltage; alternatively, when it is determined that the first preset gray scale voltage generates a negative offset, the second preset gray scale voltage generates a negative offset, and the negative offset of the first preset gray scale voltage is smaller than the negative offset of the second preset gray scale voltage, the dc offset degree may be a negative dc offset degree, and the offset detection circuit 10 may output an offset detection signal corresponding to the negative dc offset degree. It should be additionally noted that, when the first preset gray scale voltage and the second preset gray scale voltage both generate positive offset or negative offset, and the positive offset or the negative offset of the first preset gray scale voltage and the second preset gray scale voltage are equal, even if there is a dc offset voltage at two ends of the liquid crystal layer at this time, the voltage difference between the first preset gray scale voltage and the second preset gray scale voltage is still a preset voltage difference value, that is, the dc offset degree at this time may be zero dc offset degree, and at this time, the offset detection circuit 10 may output an offset detection signal corresponding to the characteristic zero dc offset degree.
The correction voltage generating circuit 20 may operate a corresponding hardware circuit or a corresponding software program and a corresponding algorithm to analyze the offset detection signal to obtain a dc offset degree represented by the offset detection signal, and may further determine a correction voltage value corresponding to the offset detection signal by invoking a preset mapping table or operating a corresponding correction voltage value calculating algorithm, and generate a correction voltage value with a corresponding magnitude to be output to the common electrode line 40 to be superimposed on the common voltage VCOM currently received by the common electrode line 40, so that the voltage value of the common voltage VCOM may be correspondingly increased, decreased or unchanged, thereby implementing the correction of the common voltage VCOM. The method comprises the following specific steps: when the deviation detection signal represents the positive DC deviation degree, the generated and output correction voltage is a positive voltage value, so that the common voltage VCOM is increased; when the offset detection signal represents the negative DC offset degree, the generated and output correction voltage is a negative voltage value, so that the common voltage VCOM is reduced; when the offset detection signal represents a zero dc offset degree, the generated and outputted correction voltage is zero voltage value, so that the common voltage VCOM is not changed.
By the arrangement, the corrected common voltage VCOM can neutralize the direct current bias voltage caused by redundant impurity charges, so that the influence of the direct current bias voltage on liquid crystal molecules is eliminated, the direct current offset degree of two ends of the liquid crystal layer influenced by the ambient temperature is also eliminated, and the problem that the display effect of the liquid crystal display panel is influenced by the ambient temperature is solved. In addition, this application technical scheme presets grey level voltage for automatic acquisition two ways and eliminates direct current skew, need not to set up ambient temperature detection module, is favorable to reducing the shared PCB area of this application common voltage correction circuit, and owing to be automatic acquisition, makes this application scheme still can carry out real-time correction to common voltage VCOM along with ambient temperature's transform automatically to reduce ambient temperature to the influence of liquid crystal layer to minimum, therefore be favorable to improving the display stability of liquid crystal display panel under full service temperature interval.
Referring to fig. 1 to 3, in an embodiment, the offset detection circuit 10 includes:
a first offset detection circuit 11, an input end of the first offset detection circuit 11 being configured to access the first preset grayscale voltage, the first offset detection circuit 11 being configured to determine a dc offset degree of the first preset grayscale voltage according to the first preset grayscale voltage, and output a first offset degree detection signal;
the input end of the first offset detection circuit 11 is used for accessing the second preset gray scale voltage, and the second offset detection circuit 12 is used for determining the dc offset degree of the second preset gray scale voltage according to the second preset gray scale voltage and outputting a second offset degree detection signal; and the number of the first and second groups,
a dc bias determining circuit 13, a first input end and a second input end of the dc bias determining circuit 13 are respectively connected to the output end of the first deviation detecting circuit 11 and the output end of the second deviation detecting circuit 12, and the dc bias determining circuit 13 is configured to determine a dc deviation degree affected by an ambient temperature at two ends of the liquid crystal layer according to the first deviation degree detecting signal and the second deviation degree detecting signal, and output the deviation detecting signal.
In this embodiment, the first detection offset circuit may compare the accessed first preset gray-scale voltage with a corresponding gray-scale voltage threshold or a preset reference voltage, and may determine, according to the determination result, a magnitude of the influence of the dc offset voltage at the ambient temperature on the first preset gray-scale voltage, that is, a dc offset degree of the first preset gray-scale voltage, and may generate and output a corresponding first offset degree detection signal, thereby implementing the dc offset detection of the first preset gray-scale voltage. The second detection offset circuit can compare the accessed second preset gray scale voltage with a corresponding gray scale voltage threshold or a preset reference voltage, determine the influence of the second preset gray scale voltage on the DC offset voltage at the ambient temperature according to the determination result, namely the DC offset degree of the second preset gray scale voltage, and generate and output a corresponding second offset degree detection signal, thereby realizing the DC offset detection of the second preset gray scale voltage. The dc offset determining circuit may perform corresponding operation on the first offset detection signal and the second offset detection signal, for example, after addition or subtraction, the operation result is used as the dc offset degree of the two ends of the liquid crystal layer affected by the ambient temperature, and outputs the corresponding offset detection signal, thereby implementing the dc offset degree detection of the two ends of the step-wise liquid crystal layer.
According to the scheme of the application, the offset detection circuit 10 is realized by adopting the mutually independent circuits of the first offset detection circuit 11, the second offset detection circuit 12 and the direct current offset circuit, so that the influence on the final output result of the direct current offset determination circuit 13 can be effectively reduced when the direct current offset detection of the first offset detection circuit 11 or the second offset detection circuit 12 fails.
Optionally, the input terminal of the first offset detection circuit 11 includes a positive input terminal and a negative input terminal, and the first offset detection circuit 11 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a first operational amplifier A1;
a first end of the first resistor R1 is a positive input end of the first offset detection circuit 11, a second end of the first resistor R1, an inverting input end of the first operational amplifier a1, and a first end of the second resistor R2 are interconnected, a second end of the second resistor R2 is connected to an output end of the first operational amplifier a1, an output end of the first operational amplifier a1 is an output end of the first offset detection circuit 11, a first end of the third resistor R3 is a negative input end of the first offset detection circuit 11, a second end of the third resistor R3, a non-inverting input end of the first operational amplifier a1, and a first end of the fourth resistor R4 are interconnected, and a second end of the fourth resistor R4 is grounded.
The first end of the first resistor R1 and the first end of the third resistor R3 may be connected to the negative output terminal and the positive output terminal of the gray scale voltage generating circuit 50 for outputting the first predetermined gray scale voltage in a one-to-one correspondence manner, so as to access the first predetermined gray scale voltage. In this embodiment, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the first operational amplifier a1 form a subtractor, so that the first operational amplifier a1 can subtract the input signal at the non-inverting input terminal from the input signal at the inverting input terminal, and can output the subtraction result as the first offset degree detection signal.
Optionally, the input terminal of the second offset detection circuit 12 includes a positive input terminal and a negative input terminal, and the second offset detection circuit 12 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a second operational amplifier A2;
a first end of the fifth resistor R5 is a positive input end of the second offset detection circuit 12, a second end of the fifth resistor R5, an inverting input end of the second operational amplifier a2, and a first end of the sixth resistor R6 are interconnected, a second end of the sixth resistor R6 is connected to an output end of the second operational amplifier a2, an output end of the second operational amplifier a2 is an output end of the second offset detection circuit 12, a first end of the seventh resistor R7 is a negative input end of the second offset detection circuit 12, a second end of the seventh resistor R7, a non-inverting input end of the second operational amplifier a2, and a first end of the eighth resistor R8 are interconnected, and a second end of the eighth resistor R8 is grounded.
The first end of the fifth resistor R5 and the first end of the seventh resistor R7 may be connected to the negative output terminal and the positive output terminal of the gray scale voltage generating circuit 50 for outputting the second predetermined gray scale voltage in a one-to-one correspondence manner, so as to enable the second predetermined gray scale voltage to be switched in. In this embodiment, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the second operational amplifier a2 constitute a subtractor, so that the second operational amplifier a2 can subtract the input signal at the non-inverting input terminal and the input signal at the inverting input terminal thereof, and can output the subtraction result as the second offset degree detection signal.
Optionally, the dc bias determining circuit 13 includes:
a positive input terminal, a negative input terminal, and an output terminal of the third operational amplifier A3 are respectively a first input terminal, a second input terminal, and an output terminal of the dc offset determination circuit 13 of the third operational amplifier A3.
In this embodiment, the third operational amplifier a3 functions as a comparator to compare the first deviation degree detection signal with the second deviation degree detection signal, and can output a corresponding level signal as a deviation detection signal according to the comparison result. The method specifically comprises the following steps: when the comparison result is that the first deviation degree detection signal is larger than the second deviation degree detection signal, outputting a deviation detection signal of a high level signal to represent the positive direct current deviation degree; and when the comparison result shows that the first deviation degree detection signal is smaller than the second deviation degree detection signal, outputting a deviation detection signal of the low-level signal, and outputting the deviation detection signal of the low-level signal to represent the negative direct current deviation degree.
Referring to fig. 1 to 3, in an embodiment, the correction voltage generation circuit 20 includes:
a memory 21 for storing a mapping table of a preset dc offset level to a preset correction voltage value;
the input end of the correction voltage generation circuit 22 is connected to the output end of the offset detection circuit 10, the data end of the correction voltage generation circuit 22 is connected to the memory 21 in a communication manner, and the correction voltage generation circuit 22 is configured to call the preset dc offset degree-preset correction voltage value mapping table according to the offset detection signal to find out a preset correction voltage value corresponding to the offset detection signal and generate and output a corresponding correction voltage;
an input end of the digital-to-analog conversion circuit 23 is connected to an output end of the correction voltage generation circuit 22, an output end of the digital-to-analog conversion circuit 23 is an output end of the correction voltage generation circuit 20, and the digital-to-analog conversion circuit 23 is configured to perform digital-to-analog conversion on the correction voltage that is accessed and then output the correction voltage.
In this embodiment, the memory 21 may be pre-stored with a plurality of preset dc offset degrees and a plurality of preset calibration voltage values, and each preset dc offset degree may be associated with a preset calibration voltage value to form a preset dc offset degree-preset calibration voltage value mapping table. The preset dc offset degrees, the correction voltage values, and the corresponding relationship between the preset dc offset degrees and the correction voltage values can be obtained through a large number of preliminary experiments, which is not limited herein. The correction voltage generation circuit 22 may be implemented using a processor or a flip-flop circuit. The calibration voltage generating circuit 22 may call a mapping table of the preset dc offset degree to the preset calibration voltage value after determining the dc offset degree corresponding to the offset detection signal, so as to look up a table to obtain the preset dc offset degree corresponding to or closest to the dc offset degree and the corresponding preset calibration voltage value. The correction voltage generation circuit 22 may also operate a corresponding hardware circuit or a software program and an algorithm to generate and output a correction voltage having a preset correction voltage value to the digital-to-analog conversion circuit 23, so as to be converted into an analog signal by the digital-to-analog conversion circuit 23 and then output the analog signal.
In the example of fig. 3, the memory 21 is implemented as a RAM, and the correction voltage generation circuit 22 is implemented as a D flip-flop U1 triggered by a rising edge. The clock terminal of the D flip-flop U1 is an input terminal of the correction voltage generation circuit 22, and the D terminal is a data terminal, so that when receiving the offset detection signal of the high level signal output by the third operational amplifier A3, the high level signal of the digital signal output by the memory 21 is accessed and output as the correction voltage, thereby generating and outputting the correction voltage having a positive voltage value. In another embodiment, the correction voltage generation circuit 22 may further include a falling edge triggered D flip-flop U1, the clock terminals of the two D flip-flops U1 are interconnected to form the input terminal of the correction voltage generation circuit 22, and the D terminals of the two D flip-flops U1 are respectively connected to the memory 21, so that the falling edge triggered D flip-flop U1 is connected to the low level signal of the digital signal output from the memory 21 and outputs the low level signal as the correction voltage when receiving the offset detection signal of the low level signal output from the third operational amplifier A3, thereby generating and outputting the correction voltage having a negative voltage value.
According to the scheme, the corresponding correction voltage value is quickly obtained by looking up the table, and compared with the method for calculating the correction voltage value in real time by adopting a programmable device, the correction voltage value is less influenced by the environmental temperature, and the high-brush design of the display device is more convenient.
Referring to fig. 1 to 3, in an embodiment, the common voltage correction circuit further includes:
a buffer circuit 30, a first input terminal and a second input terminal of the buffer circuit 30 are respectively connected to the output terminal of the correction voltage generation circuit 20 and the output terminal of the common voltage generation circuit 60, an output terminal of the buffer circuit 30 is connected to the common electrode line 40, and the buffer circuit 30 is configured to correct the common voltage VCOM according to the correction voltage, buffer the corrected common voltage VCOM, and output the buffered common voltage VCOM to the common electrode line 40.
In practical applications, it is found that if the correction voltage is directly outputted to the common electrode line 40 to achieve the correction, the common voltage VCOM on the common electrode line 40 may be unstable, and the display effect may be affected. In view of this problem, the present embodiment is designed with a buffer circuit 30, which corrects the common voltage VCOM according to the correction voltage through the buffer circuit 30, and outputs the corrected common voltage VCOM after signal buffering. It should be noted that, even if there is no correction voltage, the common electrode line 40 is connected to the common voltage VCOM buffered by the buffer circuit 30, so that when the correction voltage is superimposed halfway, the fluctuation of the common voltage VCOM on the common electrode line 40 can be effectively reduced, which is beneficial to improving the stability of the display.
In the embodiment shown in fig. 3, the buffer circuit 30 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a fourth operational amplifier; a first end of the ninth resistor R9 and a first end of the tenth resistor R10 are respectively a first input end and a second input end of the buffer circuit 30, a second end of the ninth resistor R9, a first end of the tenth resistor R10 and a non-inverting input end of the fourth operational amplifier are interconnected to realize superposition of the correction voltage and the common voltage VCOM, an inverting input end of an output end of the fourth operational amplifier, a second end of the eleventh resistor R11 and a first end of the twelfth resistor R12 are interconnected, a first end of the eleventh resistor R11 is connected with an output end of the fourth operational amplifier, a second end of the twelfth resistor R12 is connected with a preset voltage, and an output end of the fourth operational amplifier is an output end of the buffer circuit 30.
Example two:
the application also provides a display panel.
Referring to fig. 4, the display panel includes a common electrode line 40, a gray scale voltage generating circuit 50, and a common voltage correcting circuit, and the specific structure of the common voltage correcting circuit refers to the above embodiments.
The gray scale voltage generating circuit 50 is configured to output a first preset gray scale voltage and a second preset gray scale voltage; a common voltage generating circuit 60 connected to the common electrode line 40 for outputting a common voltage VCOM to the common electrode line; and a common voltage correction circuit respectively connected to the common electrode line 40, the gray scale voltage generation circuit 50 and the common voltage generation circuit 60 to respectively receive the first preset gray scale voltage, the second preset gray scale voltage and the common voltage VCOM and output the corrected common voltage VCOM value of the common electrode line 40.
Optionally, the grayscale voltage generating circuit 50 is configured to output N preset grayscale voltages, where N is a positive integer;
the preset gray scale voltage with the minimum voltage value in the N paths of preset gray scale voltages is the first preset gray scale voltage, and the preset gray scale voltage with the maximum voltage value in the N paths of preset gray scale voltages is the second preset gray scale voltage.
Taking 8Bit of the embodiment shown in fig. 3 as an example, N is 256, wherein the voltage value of the first predetermined grayscale voltage is the maximum voltage value, i.e. the 0 th predetermined grayscale voltage V0, and the remaining 256 predetermined grayscale voltages can be obtained by continuously dividing the previous grayscale voltage, so that the voltage value of the 256 predetermined grayscale voltage is the minimum voltage value, i.e. the 255 th predetermined grayscale voltage V255. In practical applications, the color depth of the display panel may also be designed to be 6Bit, 10Bit or 12Bit, which is not limited herein. According to the scheme, the last-order preset gray scale voltage with the minimum voltage value and the 0 th-order preset gray scale voltage with the maximum voltage value in the N paths of preset gray scale voltages are selected to serve as the first preset gray scale voltage and the second preset gray scale voltage respectively, and the accuracy of detecting the direct current offset degree at two ends of the liquid crystal layer is improved.
Example three:
the present application further provides a display device, which includes a common electrode line 40, a gray scale voltage generating circuit 50, and a common voltage correcting circuit, and the specific structure of the common voltage correcting circuit refers to the above embodiments.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the subject matter of the present application, which are made by the following claims and their equivalents, or which are directly or indirectly applicable to other related arts, are intended to be included within the scope of the present application.
Claims (8)
1. A common voltage correction circuit is applied to a display panel, and the display panel comprises: the device comprises a common electrode wire, a gray scale voltage generating circuit and a common voltage generating circuit, wherein the gray scale voltage generating circuit is used for outputting a first preset gray scale voltage and a second preset gray scale voltage, the common voltage generating circuit is used for outputting a common voltage to the common electrode wire, the gray scale voltage generating circuit is used for outputting N paths of preset gray scale voltages, and N is a positive integer; the minimum voltage value of the N preset gray scale voltages is the first preset gray scale voltage, the maximum voltage value of the N preset gray scale voltages is the second preset gray scale voltage, and the public voltage correction circuit comprises:
the offset detection circuit is used for determining the DC offset degree of two ends of the liquid crystal layer, which is influenced by the ambient temperature, according to the first preset gray scale voltage and the second preset gray scale voltage and outputting an offset detection signal; and (c) a second step of,
the input end of the correction voltage generating circuit is connected with the output end of the offset detection circuit, the output end of the correction voltage generating circuit is connected with the common electrode wire, and the correction voltage generating circuit is used for generating corresponding correction voltage according to the offset detection signal and outputting the corresponding correction voltage to the common electrode wire so as to correct the common voltage received by the common electrode wire until the degree of direct current offset of two ends of the liquid crystal layer, which is influenced by the ambient temperature, is eliminated;
the offset detection circuit includes:
the input end of the first offset detection circuit is used for accessing the first preset gray scale voltage, and the first offset detection circuit is used for determining the DC offset degree of the first preset gray scale voltage according to the first preset gray scale voltage and a corresponding gray scale voltage threshold or a preset reference voltage and outputting a first offset degree detection signal;
the input end of the first offset detection circuit is used for accessing the second preset gray scale voltage, and the second offset detection circuit is used for determining the DC offset degree of the second preset gray scale voltage according to the second preset gray scale voltage and a corresponding gray scale voltage threshold or a preset reference voltage and outputting a second offset degree detection signal;
and the first input end and the second input end of the direct current bias determining circuit are respectively connected with the output end of the first deviation detecting circuit and the output end of the second deviation detecting circuit, and the direct current bias determining circuit is used for determining the direct current deviation degree influenced by the environmental temperature at the two ends of the liquid crystal layer according to the first deviation degree detecting signal and the second deviation degree detecting signal and outputting the deviation detecting signal.
2. The common voltage correction circuit as claimed in claim 1, wherein the input terminal of the first offset detection circuit includes a positive input terminal and a negative input terminal, the first offset detection circuit comprising: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier;
the first end of the first resistor is the positive input end of the first offset detection circuit, the second end of the first resistor, the inverting input end of the first operational amplifier and the first end of the second resistor are interconnected, the second end of the second resistor is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is the output end of the first offset detection circuit, the first end of the third resistor is the negative input end of the first offset detection circuit, the second end of the third resistor, the non-inverting input end of the first operational amplifier and the first end of the fourth resistor are interconnected, and the second end of the fourth resistor is grounded.
3. The common voltage correction circuit as claimed in claim 1, wherein the input terminals of the second offset detection circuit include a positive input terminal and a negative input terminal, the second offset detection circuit comprising: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second operational amplifier;
the first end of the fifth resistor is the positive input end of the second offset detection circuit, the second end of the fifth resistor, the inverting input end of the second operational amplifier and the first end of the sixth resistor are interconnected, the second end of the sixth resistor is connected with the output end of the second operational amplifier, the output end of the second operational amplifier is the output end of the second offset detection circuit, the first end of the seventh resistor is the negative input end of the second offset detection circuit, the second end of the seventh resistor, the non-inverting input end of the second operational amplifier and the first end of the eighth resistor are interconnected, and the second end of the eighth resistor is grounded.
4. The common voltage correction circuit as claimed in claim 1, wherein said dc offset determination circuit comprises:
and a positive phase input end, a negative phase input end and an output end of the third operational amplifier are respectively a first input end, a second input end and an output end of the direct current bias determination circuit.
5. The common voltage correction circuit as claimed in claim 1, wherein the correction voltage generation circuit comprises:
the memory stores a mapping table of the preset DC offset degree-the preset correction voltage value;
the input end of the correction voltage generation circuit is connected with the output end of the offset detection circuit, the data end of the correction voltage generation circuit is in communication connection with the memory, and the correction voltage generation circuit is used for calling the preset direct current offset degree-preset correction voltage value mapping table according to the offset detection signal so as to search and obtain a preset correction voltage value corresponding to the offset detection signal and generate and output a corresponding correction voltage;
the input end of the digital-to-analog conversion circuit is connected with the output end of the correction voltage generation circuit, the output end of the digital-to-analog conversion circuit is the output end of the correction voltage generation circuit, and the digital-to-analog conversion circuit is used for performing digital-to-analog conversion on the accessed correction voltage and then outputting the correction voltage.
6. The common voltage correction circuit according to any one of claims 1 to 5, further comprising:
the first input end and the second input end of the buffer circuit are respectively connected with the output end of the correction voltage generating circuit and the output end of the public voltage generating circuit, the output end of the buffer circuit is connected with the public electrode wire, and the buffer circuit is used for correcting the public voltage according to the correction voltage, buffering the corrected public voltage signals and outputting the public voltage signals to the public electrode wire.
7. A display panel, comprising:
a common electrode line;
the gray scale voltage generating circuit is used for outputting a first preset gray scale voltage and a second preset gray scale voltage;
a common voltage generating circuit connected to the common electrode line for outputting a common voltage to the common electrode line: and the number of the first and second groups,
the common voltage correction circuit as claimed in any one of claims 1 to 6, connected to the common electrode line, the gray scale voltage generation circuit and the common voltage generation circuit, respectively;
the gray scale voltage generation circuit is used for outputting N paths of preset gray scale voltages, and N is a positive integer;
the preset gray scale voltage with the minimum voltage value in the N paths of preset gray scale voltages is the first preset gray scale voltage, and the preset gray scale voltage with the maximum voltage value in the N paths of preset gray scale voltages is the second preset gray scale voltage.
8. A display device characterized in that the display device comprises the display panel according to claim 7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210532067.4A CN114664271B (en) | 2022-05-17 | 2022-05-17 | Common voltage correction circuit, display panel and display device |
| PCT/CN2022/141162 WO2023221506A1 (en) | 2022-05-17 | 2022-12-22 | Common voltage correction circuit, display panel, and display apparatus |
Applications Claiming Priority (1)
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| CN202210532067.4A CN114664271B (en) | 2022-05-17 | 2022-05-17 | Common voltage correction circuit, display panel and display device |
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| WO2023221506A1 (en) | 2023-11-23 |
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