CN114629493A - PHYSICAL LAYER CIRCUIT FOR MULTI-LINE INTERFACE - Google Patents

Abstract

The invention discloses a physical layer circuit, which specifically includes: N signal pads, including at least four or six signal pads; a four-signal or six-signal physical medium additional sublayer; and M shielding pads. The M shielding pads include a first shielding pad coupled to the four-signal physical medium additional sublayer, or first to third shielding pads coupled to the six-signal physical medium additional sublayer. Wherein, the first shielding pad is located between a second signal pad and a third signal pad among the signal pads; the second shielding pad is located at the one of the signal pads between a third signal pad and a fourth signal pad; the third shielding pad is located between the fourth signal pad and a fifth signal pad among the signal pads and M and N is a positive integer.

Description

PHYSICAL LAYER CIRCUIT FOR MULTI-LINE INTERFACE

The present invention is a divisional application with an application date of July 19, 2018, an application number of 201810799479.8, and the title of the invention is "physical layer circuit for multi-wire interface".

technical field

The present invention relates to a multi-line data interface, and particularly refers to a physical layer circuit and a physical medium additional sublayer suitable for different physical layer modes of the multi-line data interface.

Background technique

Mobile devices such as smart phones contain various components for different purposes, such as application processors, displays, and CMOS image sensors. These elements need to be interconnected through a physical interface, for example, an interface through which an application processor can provide frame data to a display to render visual content. Alternatively, the CMOS image sensor can provide sensed image data to the application processor through an interface to output a photo or video.

The MIPI specification formulated by the Mobile Industry Processor Interface (MIPI) consortium is widely used in signal communication and data transmission between components of the above-mentioned mobile devices. MIPI D-PHY is one of the MIPI specifications. In the MIPI D-PHY interface, communication is achieved through one clock channel and one to four data channels. Each data channel contains differential signal pairs. The clock channels are used to transmit differential clock signals, and each data channel is used to transmit differential data signals.

In order to meet the high-speed transmission requirements of certain data (eg, image data), the MIPI Alliance newly developed and defined the MIPI C-PHY specification. In the MIPI C-PHY interface, communication takes place through three signal lines. The signal lines transmit three-valued signals respectively, and the three-valued signals can be converted into binary logic signals. A feature of MIPI C-PHY is that the clock is embedded in the data signal, and the receiver performs clock and data recovery when receiving the data signal.

Although the MIPI C-PHY interface can efficiently implement high-speed signal communication and can provide high throughput, this interface is not necessary for all components and requirements in a mobile device. So if the supplier can provide functional blocks and/or integrated circuits that are suitable for both specifications, it is quite welcome for the manufacturer. Therefore, it is necessary to provide integrated circuits or semiconductor devices that support MIPI D-PHY and MIPI C-PHY specifications.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a physical layer circuit and a multi-signal physical medium additional sublayer suitable for different physical layer modes of a multi-wire interface. The physical layer circuit and the physical medium additional sublayer proposed by the present invention have been designed with consideration of the difference in signal characteristics between different physical layer modes, such as MIPI D-PHY and MIPI C-PHY. Thereby, a two-in-one physical layer (combo PHY) device is realized, which can be seamlessly connected with MIPI D-PHY based devices or MIPI C-PHY based devices.

An embodiment of the present invention provides a physical layer circuit, the physical layer circuit includes: N signal pads, including at least four signal pads; a four-signal physical medium additional sub-layer coupled to the four signal pads pads; and M shielding pads, including at least one first shielding pad coupled to the four-signal physical medium additional sublayer. The first shielding pad is located between a second signal pad and a third signal pad among the four signal pads, and M and N are positive integers.

An embodiment of the present invention provides a physical layer circuit, the physical layer circuit includes: N signal pads, including at least six signal pads; a six-signal physical medium additional sub-layer coupled to the six signal pads pads; and M shielding pads, including at least a first shielding pad, a second shielding pad and a third shielding pad, respectively coupled to the six signal physical medium additional sublayers. Wherein, the first shielding pad is located between a second signal pad and a third signal pad among the six signal pads; the second shielding pad is located between the six signal pads between the third signal pad and a fourth signal pad in the , where M and N are positive integers.

An embodiment of the present invention provides a physical layer circuit, the physical layer circuit includes: N signal pads, including at least four signal pads; and a four-signal physical medium additional sublayer coupled to the four signals pad. The four-signal physical medium additional sublayer also includes a four-signal termination circuit. The four-signal terminal circuit includes: four adjustable resistive elements, each of which is respectively coupled to one of the four signal pads; a wire coupled to one end of a first adjustable resistive element and one end of a second adjustable resistive element; a first switch selectively coupled to one end of the second adjustable resistive element and one end of a third adjustable resistive element and a second switch selectively coupled between the terminal of the third adjustable resistive element and one terminal of a fourth adjustable resistive element. wherein the first switch is controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

An embodiment of the present invention provides a physical layer circuit, the physical layer circuit includes: N signal pads, including at least six signal pads; a six-signal physical medium additional sublayer, coupled to the six signals pad. The six-signal physical medium additional sublayer includes: a six-signal termination circuit coupled to the six-signal pads. The six-signal terminal circuit includes: six adjustable resistive elements, each of which is respectively coupled to one of the six signal pads; a first wire coupled to a first adjustable resistive element between one terminal and one terminal of a second adjustable resistive element; a second wire is coupled between one terminal of a fifth adjustable resistive element and one terminal of a sixth adjustable resistive element ; a first switch selectively coupled between the terminal of the second adjustable resistive element and a terminal of a third adjustable resistive element; and a second switch selectively coupled connected between the terminal of the third adjustable resistive element and one terminal of a fourth adjustable resistive element; a third switch selectively coupled to the fourth adjustable resistive element between the terminal of and a fifth adjustable resistive element. Wherein, the first switch and the third switch are controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

Description of drawings

FIG. 1 is a PHY circuit including a four-signal PMA supporting a two-lane PHY mode and a three-lane PHY mode according to an embodiment of the present invention.

FIG. 2 shows how to reduce the number of deserializers in the PMA according to an embodiment of the present invention.

FIG. 3 is a PHY circuit including a six-signal PMA supporting a two-lane PHY mode and a three-lane PHY mode according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating how a clock signal is used to process data signals at different stages according to an embodiment of the present invention.

FIG. 5 is an arrangement of signal pads for a PHY circuit including a four-signal PMA according to an embodiment of the present invention.

FIG. 6 is an arrangement of signal pads for a PHY circuit including a six-signal PMA according to an embodiment of the present invention.

7 and 8 illustrate the layout of signal pads including electrostatic discharge protection and pad shielding.

9A-9C are terminal circuits suitable for two-wire channel PHY mode and three-wire channel PHY mode in the prior art.

10A-10D are terminal circuits suitable for four-signal PMA in an embodiment of the present invention.

11A-11D are terminal circuits suitable for a six-signal PMA in an embodiment of the present invention.

FIG. 12 is a CDR circuit in a receiver for a three-wire communication link according to an embodiment of the present invention.

FIG. 13 is a signal timing diagram for a CDR circuit having a duty cycle correction circuit.

14 is a detailed circuit diagram of one embodiment of a duty cycle correction circuit.

15 and 16 are signal timing diagrams explaining the operation of the duty cycle correction circuit of FIG. 14 .

FIG. 17 is a detailed circuit diagram of another embodiment of the duty cycle correction circuit.

FIG. 18 is a signal timing diagram illustrating the operation of the duty cycle correction circuit of FIG. 17 .

FIG. 19 is a CDR circuit in a receiver for a three-wire communication link in another embodiment of the present invention.

FIG. 20 is a signal timing diagram illustrating the operation of the delay correction circuit of FIG. 19 .

reference number

800, 900, 110, 210, 411, 412 Physical Media Additional Sublayer

600 Termination Circuit

811-813, 911-916 Difference Amplifier

821, 822, 1110, 1112, 921, 923, 925 S/H circuit

823, 1111, 922, 924, 1010, 1200 CDR circuits

831, 832, 833, 1120, 931-935, 1020 Deserializers

840, 1130, 941, 942, 1030 buffers

845, 1035, 943, 944 symbol decoders

850, 1040, 951, 952 Data Processing Unit

100, 200, 300, 400 physical layer circuits

320, 322, 420, 422 ESD protection circuit

330, 430 entity coding sublayer

500, 600, 700 Termination Circuits

1210-1223, 2011-2013 Delay Unit

1221-1223, 2021-2023, 2091-2092 XOR gate

1231-1233, 2031-2033 Latch

1240, 2040 OR gate

1250, 1500, 1800 duty cycle correction circuit

1260, 2060 aligned delay units

1281-1282, 2081-2082 Sampling Unit

1271-1272, 2071-2072 Frequency divider

1511-1512 selector

1520 TDC

1530, 1820 Digital Control Logic

1540, 1830 NAND gate

1550, 1840 Programmable Delay Lines

1810 Comparator

2000 Delay Adjustment Unit

Detailed ways

In the following text, numerous specific details are described in order to provide the reader with a thorough understanding of the embodiments of the present invention. However, one skilled in the art will understand how to practice the invention in the absence of one or more of the specific details, or with other methods or elements or materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in the embodiment may be included in at least one embodiment of the present invention. Thus, the appearances of "in an embodiment" in various places in this specification do not necessarily mean the same embodiment. Furthermore, the particular features, structures or characteristics described above may be combined in any suitable form in one or more embodiments.

The present invention mainly provides a four-signal (four-signal) physical medium attachment sublayer (PMA) and/or a six-signal (six-signal) PMA in a physical layer circuit (PHY) of a receiver for interfacing with Compliant with the MIPI C-PHY specification or other types of PHY specifications that use three signal lines to form a lane (hereafter referred to as three-wire lane PHY), and with MIPI C-PHY specification or other types that use two signal lines A PHY specification for forming a lane (hereinafter referred to as a two-wire lane PHY) is used for communication wiring. In embodiments of the present invention, four-signal PMA and six-signal PMA may be implemented in the form of intellectual property (IP) cores, IP blocks or functional blocks to increase design productivity and make highly complex integrated circuit development manageable .

Both the four-signal PMA and the six-signal PMA of the present invention can be configured to operate in either MIPI D-PHY mode (or other type of two-wire channel PHY mode) and MIPI C-PHY mode (or other type of three-wire channel PHY mode) one. For each of them, a four-signal PMA can provide two "two-wire" channels or one "three-wire" channel for one communication link, while a six-signal PMA can provide three "two-wire" channels for one communication link or two "three-wire" channels.

Due to the signal characteristics of these different PHY modes, different signal processing procedures/hardware resources are required to process signals conforming to different PHY specifications. As described in the text below, the present invention provides pad arrangements, termination circuits, de-sequencing structures, and clock and data recovery circuits for four- and six-signal PMAs.

Invention as a whole

Please refer to FIG. 1 , which is a schematic diagram of a portion of a PHY circuit according to an embodiment of the present invention. As shown, the PHY circuit includes a four-signal PMA 800 and four signal pads D0P_T0A, D0N_T0B, D1P_TOC, and D1N, and a four-signal termination circuit 600 . The signal pads D0P_T0A, D0N_T0B, D1P_TOC and D1N are respectively coupled to the differential amplifiers 811 - 813 in the four-signal PMA 800 . The four-signal termination circuit 600 is also coupled to the signal pads D0P_T0A, D0N_T0B, D1P_T0C and D1N, respectively. Therefore, the differential amplifiers 811-813 are coupled to the termination circuit 600, respectively.

Generally, the four-signal PMA 800 in this embodiment supports a PHY mode of a two-wire channel (eg, MIPI D-PHY) and a PHY mode of a three-wire channel (eg, MIPI C-PHY). When the four-signal PMA 800 is configured in MIPI D-PHY mode and operating in MIPI D-PHY mode for MIPI D-PHY communication, it can support 2 two-wire lanes, signal pads D0P_T0A and D0N_T0B Connect to the first two-wire channel, while signal pads D1P_T0C and D1N connect to the second two-wire channel. Alternatively, when the four-signal PMA 800 is set to MIPI C-PHY mode and operating in MIPI C-PHY mode for MIPI C-PHY communications, the signal pads D0P_T0A, D0N_T0B and D1P_T0C are connected to a three-wire channel .

In the case of MIPI D-PHY mode/signal wiring, the signal pads D0P_T0A and D0N_T0B are coupled to the differential amplifier 811, and the differential amplifier 811 outputs a differential based on the difference between the signals on the signal pads D0P_T0A and D0N_T0B signal D0. The signal pads D1P_TOC and D1N are coupled to the differential amplifier 813 through switches, and the differential amplifier 813 outputs a differential signal D1 based on the difference between the signals on the signal pads D1P_TOC and D1N. In addition, a first signal processing block is coupled to the differential amplifier 811 . And, when the four-signal PMA 800 operates in MIPI D-PHY mode, the first signal processing block is used to process the differential signal D0. A third signal processing block is coupled to the differential amplifier 811 . Also, when the four-signal PMA 800 operates in MIPI D-PHY mode, the third signal processing block is used to process the differential signal D1.

In one embodiment, the first signal processing block includes at least a sample and hold (S/H) circuit 821 . The S/H circuit 821 generates the sequence data signal D0[1:0] and the clock signal D0_CK according to the differential signal D0. The third signal processing block includes at least an S/H circuit 823, and the S/H circuit 823 generates a sequence data signal D1[1:0] and a clock signal D1_CK according to the differential signal D1.

In one embodiment, the first signal processing block may further include a 2-to-8 deserializer 831 coupled to the S/H circuit 821 . The S/H circuit 821 outputs the data signal D0[1:0] and the clock signal D0_CK to the 2-to-8 deserializer 831. The 2-to-8 deserializer 831 performs a deserialization operation on them to generate a plurality of parallel data signals D0 [7:0] and clock signal D0_BCK. The third signal processing block may also include a 2 to 8 deserializer 833 coupled to the S/H circuit 823 . The S/H circuit 823 outputs the data signal D1[1:0] and the clock signal D1_CK to the 2-to-8 deserializer 833. The 2-to-8 deserializer 833 performs a deserialization operation on them to generate a plurality of parallel data signals D1[7:0] and the clock signal D1_BCK.

In the case of MIPI C-PHY mode/signal wiring, the signal pads D0P_T0A, D0N_T0B and D1P_TOC are coupled to differential amplifiers 811-813. The differential amplifier 811 outputs a differential signal TOAB based on the difference between the signals on the signal pads D0P_TOA and D0N_TOB. The differential amplifier 812 outputs a differential signal TOCA based on the difference between the signals on the signal pads D1P_TOC and D0P_TOA. The differential amplifier 813 outputs a differential signal TOBC based on the difference between the signals on the signal pads D0P_TOB and D1P_TOC. The differential amplifiers 811-813 are coupled to a second signal processing block. When the four-signal PMA 800 operates in MIPI C-PHY mode, the second signal processing block is used to process the differential signals TOAB, TOBC and TOCA.

In one embodiment, the second signal processing block at least includes a C-PHY clock and data recovery (Clock and data recovery, CDR) circuit 822, and the C-PHY CDR circuit 822 generates according to the differential signals TOAB, TOBC, and TOCA A set of sequence data signals TOAB[1:0], TOBC[1:0] and TOCA[1:0] and corresponding clock signal TO_CK.

In one embodiment, the second signal processing block includes at least a 2-to-8 deserializer 832 coupled to the C-PHY CDR circuit 822 . C-PHY CDR circuit 822 output signals TOAB[1:0], TOBC[1:0] and TOCA[1:0] and T0_CK to 2 to 8 deserializer 832. 2 to 8 deserializer 832 according to the clock signal TOCK, de-sequence the signals TOAB[1:0], TOBC[1:0] and TOCA[1:0] to generate a set of parallel data signals TOAB[7:0], TOBC[7:0], T0CA[7:0] and the corresponding clock signal T0_BCK.

The 2-to-8 deserializer 832 is further coupled to an 8-to-7 first-in, first-outbuffer, FIFO 840, and the 8-to-7 FIFO 840 converts the 8-bit metadata signal TOAB[7:0] , TOBC[7:0] and TOCA[7:0] are converted to 7-bit length. The 8-to-7 FIFO 840 is coupled to a 7-symbol decoding unit 845. The 7-symbol decoding unit 845 is used to decode the data signal read from the 8-to-7 FIFO 840 to generate data symbols. The 7-symbol decoding unit 845 is coupled to the data processing unit 850 . The data processing unit 850 is used for processing the data symbols output by the 7-symbol decoding unit 845 . Data processing unit 850 may include a 7-symbol to 16-bit demapper for demapping every 7-symbol received from 7-symbol decoding unit 845 into 16-bit data blocks.

In addition, the 8-to-7 FIFO 840 , the 7-symbol decoding unit 845 and the data processing unit 850 together function as the C-PHY decoding processor 860 in the four-signal PMA 800 . Furthermore, the order of the 8-to-7 FIFOs and 7-symbol decoding units in the four-signal PMA 800 are interchangeable. According to different embodiments of the present invention, the symbol decoding unit may be arranged before the FIFO (refer to the applicant's US Patent Application No. 15/956,709, which discloses the structure of the symbol decoding unit before the FIFO).

Since the quad-signal PMA 800 may not operate in MIPI D-PHY mode and MIPI C-PHY mode at the same time, the number of 2 to 8 deserializers configured in the quad-signal PMA 800 may be reduced. Please refer to Figure 2 for further understanding. When operating in MIPI D-PHY mode, the S/H circuits 1110 and 1112 may share the same 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 aligns the data signal D0 according to the clock signals D0_CK and D1_CK, respectively [1:0] and D1[1:0] for deserialization. On the other hand, when operating in MIPI C-PHY mode, the C-PHY CDR circuit 1111 only needs one 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 aligns the data signal TOAB according to the clock signal TO_CK [1:0], TOBC[1:0] and TOCA[1:0] for deserialization. Compared to the three separate de-sequencers 831-833 required by the four-signal PMA 800 of FIG. 1, this implementation significantly improves circuit area utilization efficiency.

FIG. 3 is another embodiment of the present invention that can support MIPI D-PHY communication lines and MIPI C-PHY communication lines. As shown, the PHY circuit in FIG. 3 includes six-signal PMA 900 , signals D0P_T0A, D0N_T0B, D1P_TOC, D1N_T1A, D2P_T1B, and D2N_T1C, and six-signal termination circuit 700 . Signal pads D0P_T0A, D0N_T0B, D1P_T0C, D1N_T1A, D2P_T1B, and D2N_T1C are coupled to differential amplifiers 911-916 of 6-signal PMA 900, respectively. The six signal termination circuits 700 are also coupled to the signal pads D0P_T0A, D0N_T0B, D1P_T0C, D1N_T1A, D2P_T1B and D2N_T1C, respectively. Thus, differential amplifiers 911-916 are coupled to the six-signal termination circuit 700, respectively.

When the six-signal PMA 900 is set to MIPI D-PHY mode and operating in MIPI D-PHY based communication lines in MIPI D-PHY mode, the signal pads D0P_T0A and D0N_T0B are connected to MIPI D-PHY communication The first 2-wire lane in the wire, the signal pads D1P_T0C and D1N_T1A are connected to the second 2-wire lane in the MIPI D-PHY communication wire, and the pads D2P_T1C and D2N_T1C are connected to the MIPI D-PHY communication The third two-wire channel in the wire. Alternatively, when the six-signal PMA 900 is set to MIPI C-PHY mode and operates in MIPI C-PHY based communication lines in MIPI C-PHY mode, the signal pads D0P_T0A, D0N_T0B and D1P_T0C are connected to MIPI The first 3-wire lane in the C-PHY communication wire, the signal pads D1N_T1A, D2P_T1B and D2N_T1C are connected to the second 3-wire lane in the MIPI C-PHY communication wire.

In the case of MIPI D-PHY mode/communication link, the signal pads D0P_T0A and D0N_T0B are coupled to the differential amplifier 911, and the differential amplifier 911 outputs a differential based on the difference between the signals on the signal pads D0P_T0A and D0N_T0B signal D0. The signal pads D1P_TOC and D1N_T1A are coupled to the differential amplifier 913 through switches, and the differential amplifier 913 outputs a differential signal D1 based on the difference between the signals on the signal pads D1P_TOC and D1N_T1A. Signal pads D2P_T1B and D2N_T1C are coupled to differential amplifier 916 through switches, and differential amplifier 916 outputs differential signal D2 based on the difference between the signals on signal pads D2P_T1B and D2N_T1C. Furthermore, the first signal processing block is coupled to the differential amplifier 911 and is used to process the differential signal D0 when the six-signal PMA 900 operates in MIPI D-PHY mode. The third signal processing block is coupled to the differential amplifier 913 and is used to process the differential signal D1 when the six-signal PMA 900 operates in MIPI D-PHY mode. The fifth signal processing block is coupled to the differential amplifier 916 and is used to process the differential signal D2 when the six-signal PMA 900 is operating in MIPI D-PHY mode.

In one embodiment, the first signal processing block includes at least the S/H circuit 921 . The S/H circuit 921 generates the sequence data signal D0[1:0] and the clock signal D0_CK according to the signal D0. The third signal processing block includes at least an S/H circuit 923, and the S/H circuit 923 generates a sequence data signal D1[1:0] and a clock signal D1_CK according to the signal D1. The fifth signal processing block includes at least an S/H circuit 925, and the S/H circuit 925 generates a sequence data signal D2[1:0] and a clock signal D2_CK according to the signal D2.

In one embodiment, the first signal processing block may further include a 2 to 8 deserializer 931 coupled to the S/H circuit 921 . The S/H circuit 921 outputs the data signal D0[1:0] and the clock signal D0_CK to the 2-to-8 deserializer 931. The 2-to-8 deserializer 931 performs a deserialization operation on these signals to generate a plurality of parallel data signals D0[7:0] and the clock signal D0_BCK. The third signal processing block may also include a 2-to-8 deserializer 933 coupled to the S/H circuit 923 . The S/H circuit 923 outputs the data signal D1[1:0] and the clock signal D1_CK to the 2-to-8 deserializer 933. The 2-to-8 deserializer 933 performs a deserialization operation on these signals to generate a plurality of parallel data signals D1[7:0] and the clock signal D1_BCK. The fifth signal processing block may also include a 2-to-8 deserializer 935 coupled to the S/H circuit 925 . The S/H circuit 925 outputs the data signal D2[1:0] and the clock signal D2_CK to the 2-to-8 deserializer 935. The 2-to-8 deserializer 935 performs a deserialization operation on these signals to generate a plurality of parallel data signals D2[7:0] and the clock signal D2_BCK.

In the case of MIPI C-PHY mode/communication link, the signal pads D0P_T0A and D0N_T0B are coupled to the differential amplifier 911, and the differential amplifier 911 outputs a difference based on the difference between the signals on the signal pads D0P_T0A and D0N_T0B Motion signal TOAB. The signal pads D0P_TOA and D1P_TOC are coupled to the differential amplifier 912, and the differential amplifier 912 outputs a differential signal TOCA based on the difference between the signals on the signal pads D0P_TOA and D1P_TOC. The signal pads D1P_TOC and D0N_TOB are coupled to the differential amplifier 913 through switches, and the differential amplifier 913 outputs a differential signal TOBC based on the difference between the signals on the signal pads D1P_TOC and D0N_TOB. The signal pads D1N_T1A and D2P_T1B are coupled to a differential amplifier 914, which outputs a differential signal T1AB based on the difference between the signals on the signal pads D1N_T1A and D2P_T1B. The signal pads D1N_T1A and D2N_T1C are coupled to the differential amplifier 915, and the differential amplifier 915 outputs a differential signal T1CA based on the difference between the signals on the signal pads D1N_T1A and D2N_T1C. Signal pads D2P_T1B and D2N_T1C are coupled to differential amplifier 916 through switches, and differential amplifier 916 outputs differential signal T1BC based on the difference between the signals on signal pads D2P_T1B and D2N_T1C.

The differential amplifiers 911-913 are also coupled to a second signal processing block. When the six-signal PMA 900 is set to MIPI C-PHY mode, the second signal processing block is used to process the differential signals TOAB, TOBC and TOCA. The differential amplifiers 914-916 are also coupled to a fourth signal processing block. When the six-signal PMA 900 is set to MIPI C-PHY mode, the fourth signal processing block is used to process the differential signals T1AB, T1BC and T1CA.

In one embodiment, the second signal processing block includes at least a C-PHY CDR circuit 922, and the C-PHY CDR circuit 922 generates a set of sequence data signals TOAB[1:0], TOBC according to the signals TOAB, TOBC and TOCA [1:0] and TOCA[1:0] and the corresponding clock signal T0_CK. The fourth signal processing block includes at least the C-PHY CDR circuit 924 and generates a set of sequence data signals T1AB[1:0], T1BC[1:0] and T1CA[1:0] according to the signals T1AB, T1BC and T1CA and the corresponding clock signal T1_CK.

In one embodiment, the second signal processing block may further include a 2-to-8 deserializer 932 coupled to the C-PHY CDR circuit 922 . C-PHY CDR circuit 922 output signals TOAB[1:0], TOBC[1:0], TOCA[1:0] and T0_CK to 2 to 8 deserializer 932. 2 to 8 deserializer 932 according to the clock signal TOCK, de-sequence the signals TOAB[1:0], TOBC[1:0] and TOCA[1:0] to generate a set of parallel data signals TOAB[7:0], TOBC[7:0], T0CA[7:0] and the corresponding clock signal T0_BCK. The fourth signal processing block may also include a 2-to-8 deserializer 934 coupled to the C-PHYCDR circuit 924 . C-PHY CDR circuit 924 output signals T1AB[1:0], T1BC[1:0], T1CA[1:0] and T1_CK to 2 to 8 deserializer 934. 2 to 8 deserializer 934 according to the clock signal T1CK, perform a de-sequencing operation on the signals T1AB[1:0], T1BC[1:0] and T1CA[1:0], thereby generating a set of parallel data signals T1AB[7:0], T1BC[7:0], T1CA[7:0] and the corresponding clock signal T1_BCK.

In one embodiment, the 2-to-8 deserializer 932 is further coupled to the 8-to-7 FIFO 941, and the 8-to-7 FIFO 941 converts the 8-bit metadata signals TOAB[7:0], TOBC[7:0], TOCA[7 :0] is converted to a 7-bit long. The 8-to-7 FIFO 941 is coupled to the 7-symbol decoding unit 943. The 7-symbol decoding unit 943 is used to decode the data signal read from the 8-to-7 FIFO 941, thereby generating data symbols. The 7-symbol decoding unit 943 is coupled to the data processing unit 951 . The data processing unit 951 is used to process the data symbols output by the 7-symbol decoding unit 943 . Data processing unit 951 may include a 7-symbol to 16-bit demapper for demapping every 7-symbol received from 7-symbol decoding unit 943 into 16-bit data blocks. In addition, the 8 to 7 FIFO 941 , the 7-symbol decoding unit 943 and the data processing unit 951 work together as the C-PHY decoding processor 960 in the six-signal PMA 900 . Furthermore, the order of the FIFOs and the symbol decoding units in the six-signal PMA of the present invention are interchangeable. According to various embodiments of the present invention, the symbol decoding unit can also be arranged before the FIFO (refer to the applicant's US patent application, Doc. No. 15/956,709, which discloses the structure of the symbol decoding unit before the FIFO) .

The 2-to-8 deserializer 934 is further coupled to the 8-to-7 FIFO 942. The 8-to-7 FIFO 942 converts the 8-bit data signals T1AB[7:0], T1BC[7:0] and T1CA[7:0] into 7 bits long. The 8-to-7 FIFO 942 is coupled to a 7-symbol decoding unit 944. The 7-symbol decoding unit 944 is used to decode the data signals read from the 8-to-7 FIFO 942, thereby generating data symbols. The 7-symbol decoding unit 944 is coupled to the data processing unit 952 . The data processing unit 952 is used to process the data symbols output by the 7-symbol decoding unit 944 . Data processing unit 952 may include a 7-symbol to 16-bit demapper for demapping every 7-symbol received from 7-symbol decoding unit 944 into 16-bit data blocks. Additionally, the 8-to-7 FIFO 942 , the 7-symbol decoding unit 944 and the data processing unit 952 collectively function as another C-PHY decoding processor 970 in the six-signal PMA 900 .

As mentioned above, in order to utilize the circuit area efficiently, as in the embodiment shown in FIG. 2 , the 2-to-8 deserializers 931-933 may be combined, or the 2-to-8 deserializers 934 and 935 may be combined.

Figure 4 shows how to use the clock signal to process data signals at different stages. As shown in the figure, the 2-to-8 deserializer 1020 performs deserialization operations on the data signals AB[1:0], BC[1:0] and CA[1:0] according to the clock signal TCK, wherein the clock signal TCK The frequency is half of the symbol rate of the communication link. The 8-to-7 FIFO 1030 converts the 8-bit metadata signals AB[7:0], BC[7:0] and CA[7:0] into 7-bit data blocks according to the clock signal BCK, wherein the clock signal The frequency of BCK is 1/8 of the symbol rate. The 7-symbol decoding unit 1035 is used to decode the data signal read from the 8-to-7 FIFO 1030 to generate symbols according to the clock signal SCK. Data processing unit 1040 is coupled to 7-symbol decoding unit 1035 and is used to process symbols output from 7-symbol decoding unit 1035 . The data processing unit 1040 may include a 7-symbol to 16-bit demapper configured to demap every 7 symbols received from the 7-symbol decoding unit 1035 into 16-bit data according to the clock signal SCK block, where the frequency of the clock signal SCK is 1/7 of the symbol rate.

Please note that the data widths of any particular number of bits mentioned in the embodiments of FIGS. 1 and 3 are intended for illustrative purposes and not limitations. Those skilled in the art should understand how to choose different data width bits to set up various elements in it according to different applications and design requirements, such as the deserializers in four-signal and six-signal PMA, FIFO, and symbol decoding unit .

Pad layout

Signals sent from the PHY circuits in FIGS. 1 and 3 may be subject to interference, such as cross-talk between signal transmission lines. Therefore, in various designs, shielding techniques are often applied to mitigate interference. In order to solve these problems, the present invention provides an innovative pad arrangement to use and distribute the pads more rationally and efficiently, thereby shielding the interference.

FIG. 5 is for a pad arrangement that may be used in a PHY circuit including a four-signal PMA in accordance with an embodiment of the present invention. As shown, the PHY circuit 100 includes a four-signal PMA 110, and signal pads DOP_TOA, DON_TOB, CKP_TOC, and CKN_XXX for interfacing with other integrated circuits/devices, which are coupled to the four-signal PMA 110 by any possible type of conductor. A shielding pad SH is coupled to ground or a power supply voltage, and is used to shield the signal pads D0P_T0A and D0N_T0B to prevent interference with the signal pads CKP_T0C and CKN_XXX.

The four-signal PMA 110 may be configured in a two-wire lane PHY mode (eg, MIPI D-PHY) or a three-wire lane PHY mode (eg, MIPI C-PHY). In the dual-lane PHY mode, the signal pads D0P_T0A and D0N_T0B can form a data channel, and the signal pads CKP_T0C and CKN_XXX can be used as a clock channel. The signal PMA 110 transmits/receives a pair of data signals through the signal pads D0P_T0A and D0N_T0B, and transmits/receives a pair of clock signals through the signal pads CKP_T0C and CKN_XXX. In three-wire channel mode, three signal pads form a channel. For example, the signal pads D0P_T0A, D0N_T0B and CKP_T0C form one channel, and the signal pads CKN_XXX may not be used.

Note that, in various embodiments of the present invention, the pad arrangement shown in FIG. 5 may be further adapted to a PHY circuit comprising N signal pads and M shield pads, where N and M are positive integers. In such an embodiment, the N signal pads include at least four signal pads, and the M shield pads include at least one shield pad. The at least four signal pads and the at least one shield pad may be arranged in a pad arrangement similar to that shown in FIG. 5 .

FIG. 6 is for a pad arrangement that may be used in a PHY circuit including a six-signal PMA in accordance with an embodiment of the present invention. As shown, PHY circuit 200 includes six signal PMA 210 and signal pads D0P_TOA, D0N_TOB, CKP_TOC, CKN_T1A, D1P_T1B and D1N_T1C for interfacing with another integrated circuit/device. Shield pads SH0, SH1 and SH2 are coupled to ground or supply voltage and are used to shield certain signal pads from interference by other signal pads.

The six-signal PMA 210 can be set to either a two-wire lane PHY mode or a three-wire lane PHY mode. In the 2-wire lane PHY mode, the signal pads D0P_T0A and D0N_T0B and D1P_T1B and D1N_T1C form the data lane, while the signal pads CKP_T0C and CKN_XXX form the clock lane. The six-signal PMA 210 transmits/receives a pair of data signals through signal pads D0P_T0A and D0N_T0B and D1P_T1B and D1N_T1C, and transmits/receives a pair of clock signals through signal pads CKP_TOC, CKN_T1A. In three-lane PHY mode, three pads form a lane. For example, the signal pads D0P_T0A, D0N_T0B, and CKP_T0C form one three-wire channel, while the signal pads CKN_T1A, D1P_T0B, and D1N_T1C form another three-wire channel.

Note that, in various embodiments of the present invention, the pad arrangement shown in FIG. 6 may be further applicable to a PHY circuit comprising N signal pads and M shield pads, where N and M are positive integers. In such an embodiment, the N signal pads include at least six signal pads, and the M shield pads include at least three shield pads. The at least six signal pads and the at least three shield pads may be arranged in a pad arrangement similar to that shown in FIG. 6 .

Please refer to FIGS. 7 and 8 , which illustrate pad arrangements for Electrostatic Discharge (ESD) protection and pad shielding. 7 illustrates a pad arrangement that may be used in a PHY circuit including a six-signal PMA, according to an embodiment of the present invention. As shown, the PHY circuit 300 includes a six-signal PMA 210, a physical encoding sublayer (PCS) 330, ESD protection circuits 320 and 322, and signal pads DOP_TOA, D0N_TOB, CKP_T0C, CKN_T1A, D1P_T1B, and D1N_T1C. Shield pads SH0 and SH4 are used to couple ESD protection circuits 320 and 322 to ground to provide electromagnetic shielding. In addition, the shielding pads SH1, SH2 and SH3 are coupled to ground or a power supply voltage and are used to shield some signal pads from interference by other signal pads.

8 is a pad arrangement that may be used in a PHY circuit that includes a combination of six-signal PMA and four-signal PMA, according to an embodiment of the present invention. As shown, the PHY circuit 400 includes a six-signal PMA 411 , a four-signal PMA 412 , a PCS 430 , and ESD protection circuits 420 and 422 . Six-signal PMA 411 interfaces with another integrated circuit/device through signal pads D0P_T0A, D0N_T0B, CKP_T0C, CKN_T1A, D1P_T1B, and D1N_T1C. Four-signal PMA 412 interfaces with another integrated circuit/device through signal pads D0P_T0A, D0N_T0B, CKP_T0C, and CKN_XXX. Shield pads SH0 and SH6 are used to couple ESD protection circuits 420 and 422 to ground to provide electromagnetic shielding. In addition, the shielding pads SH1, SH2, SH3, SH4 and SH5 are coupled to ground or a supply voltage and serve to shield some signal pads from interference from other signal pads.

terminal circuit

As mentioned above, both the four-signal PMA and the six-signal PMA of the present invention can be set to operate in either a two-wire lane PHY mode or a three-wire lane PHY mode. Therefore, there is a need to provide a termination circuit suitable for signal characteristics of different PHY modes.

FIG. 9A shows a prior art termination circuit suitable for a two-wire channel PHY mode and a three-wire channel PHY mode. By controlling the switches in the termination circuit 500 of FIG. 9A. As shown in FIG. 9A, the termination circuit 500 can be switched to the first configuration to accommodate the two-wire channel shown in FIG. 9B. Alternatively, switch to the second configuration to accommodate the three-wire channel shown in Figure 9C. In the MIPI standard, the equivalent decoupling capacitor in the three-wire channel is required to be larger than the equivalent decoupling capacitor in the two-wire channel. Thus, the capacitance value of each of the decoupling capacitive elements C1 , C2 and C3 will be 1X (where "X" represents the unit capacitance value). However, this implementation would result in capacitive redundancy (ie, capacitive element C2) in the three-wire channel configuration shown in Figure 9C. To overcome the capacitive redundancy of the termination circuit 500 in a three-wire channel configuration, the present invention provides an innovative architecture for improving the termination circuit.

FIG. 10A shows a four-signal termination circuit 600 according to an embodiment of the present invention, which may be used in a PHY circuit including a four-signal PMA. Termination circuit 600 includes adjustable resistive elements R1-R4, switches S61-S62, and decoupling capacitive elements C1-C3 (each capacitive element C1-C2 has a capacitance value of 0.5X, while capacitive element C3 has a 1X capacitance value). capacitor value). In this embodiment, each adjustable resistive element R1-R4 may be coupled to a signal pad of a PHY circuit that includes a four-signal PMA (eg, four-signal PMA 800). Note that the adjustable resistive elements R1-R4 may be replaced with other types of electrical impedances according to various embodiments of the present invention.

Please refer to FIG. 1 and FIG. 10A at the same time. When the four-signal PMA 800 is set to operate in two-wire lane PHY mode, every two signal pads will form a lane, and a pair of differential signals can be sent/received through the signal pads D0P_T0A and D0N_T0B, respectively, while the D1P_T0C and D1N respectively transmit/receive another pair of clock signals. At this time, the switch S62 is turned on and the switch S61 is not turned on (as shown in FIG. 10B ). Therefore, the equivalent decoupling capacitance value obtained at the signal pads D0P_T0A and D0N_T0B is (0.5+0.5)X, and the decoupling capacitance value of 1X is obtained at the pads D1P_T0C and D1N. Furthermore, when the four-signal PMA 800 is set to operate in the three-wire lane PHY mode, switch S61 is turned on and switch S62 is turned off (shown in FIG. 10C ). Therefore, an equivalent decoupling capacitance value of (0.5+0.5+1)X is obtained at the signal pads D0P_T0A, D0N_T0B and D1P_T0C. Furthermore, as shown in FIG. 10D , in another embodiment, the decoupling capacitive elements C1 and C2 may be combined into one larger decoupling capacitive element CN with a capacitance value of (0.5+0.5).

FIG. 11A shows a six-signal termination circuit 700 according to an embodiment of the present invention, which may be used in a PHY circuit including a six-signal PMA. Six-signal termination circuit 700 includes adjustable resistive elements R1-R6, switches S61-S63, and decoupling capacitive elements C1-C6 (each having a capacitance value of 0.5X). In this embodiment, each adjustable resistive element R1-R6 may be coupled to a signal pad of a PHY circuit that includes a six-signal PMA (eg, six-signal PMA 900). Note that the adjustable resistive elements R1-R6 may be replaced with other types of impedance elements according to various embodiments of the present invention.

Please refer to FIG. 3 and FIG. 11A at the same time. When the six-signal PMA 900 is set to operate in dual-lane PHY mode, a pair of data signals can be sent/received on the signal pads D0P_T0A and D0N_T0B, a pair of data signals can be sent/received on the signal pads D1P_T0C and D1N_T1A, and A pair of clock signals are sent/received on the signal pads D2P_T1B and D2N_T1C. Additionally, the six-signal PMA 900 can provide two three-wire lanes when the six-signal PMA 900 is set to operate in three-wire lane PHY mode. For example, one set of three-wire signals is sent on signal pads D0P_T0A, D0N_T0B, and signal pad D1P_T0A, respectively, and another set of three-wire signals is sent on signal pads D1N_T1A, D2P_T1B, and D2P_T1C.

When the six-signal PMA 900 is set to operate in the 2-wire lane PHY mode, switch S62 is turned on and switches S61 and S63 are not turned on (as shown in FIG. 11B ). Therefore, decoupling capacitors with capacitance values equivalent to (0.5+0.5)X are formed at the signal pads D0P_T0A and D0N_T0B, the signal pads D1P_T0C and D1N_T1A, and the signal pads D2P_T1B and D2N_T1C, respectively. Additionally, when the six-signal PMA 900 is set to operate in the three-wire lane PHY mode, switches S61 and 63 are turned on and switch S62 is not turned on (as shown in FIG. 11C ). Therefore, decoupling capacitors with capacitance values equivalent to (0.5+0.5+0.5)X are formed at the signal pads D0P_T0A, D0N_T0B and D1P_T0C and the signal pads D1N_T1A, D2P_T1B and D2N_T1C respectively. Furthermore, as shown in FIG. 11D , in one possible embodiment, decoupling capacitive elements C1 and C2 may be implemented with a larger decoupling capacitive element CN1 having a capacitance value of (0.5+0.5)×. Additionally, in one possible embodiment, decoupling capacitive elements C5 and C6 may also be implemented with a larger decoupling capacitive element CN2 having a capacitance value of (0.5+0.5)X.

Compared to termination circuit 500, there is no capacitive redundancy in four-signal termination circuit 600 and six-signal termination circuit 700 when switching to a three-wire channel configuration. Also, another advantage of the termination circuits 600 and 700 of the present invention is the number of switches. Since the termination circuits 600 and 700 require fewer switches than the termination circuit 500, signal loss can be reduced.

clock and data recovery

In the MIPI C-PHY specification, the clock signal is embedded in the data signal. Therefore, the PHY circuit in the receiver needs to recover the clock signal from the received data signal.

Figure 12 illustrates a CDR circuit in a receiver suitable for use in MIPI C-PHY (or other three-wire lane PHY standards) communication links, according to one embodiment of the present invention. As shown, the CDR circuit 1200 has three input terminals for receiving signals AB, BC and CA generated by the differential amplifier. The differential amplifiers described above may be differential amplifiers 811-813 shown in the embodiment of FIG. 1, or differential amplifiers 911-916 shown in the embodiment of FIG. 3 on three signal pads/wires Receive differential signals, namely signal pads D0P_T0A, D0N_T0B, D1P_T0C, and convert them into differential signals AB, BC, CA (ie, TOAB[1:0], TOBC[1:0] in Figure 1 or Figure 3 ] and TOCA[1:0]).

The three signals AB, BC and CA are input to delay units 1210, 1211 and 1212, resulting in delayed versions AB_D, BC_D and CA_D of the signals AB, BC and CA. After that, exclusive OR (XOR) gates 1221 , 1222 and 1223 perform an XOR operation on the signals AB and AB_D, BC and BC_D, and CA and CA_D, respectively. Accordingly, XOR gates 1221, 1222 and 1223 generate XOR output signals AB_X, BC_X and CA_X. Due to the XOR operation, signal transitions in signals AB, BC, and CA will cause the XOR to output pulses in signals AB_X, BC_X, and CA_X. Then, the XOR output signals AB_X, BC_X and CA_X are sent to latches 1231, 1232 and 1233, and provide clocks for the latches 1231, 1232 and 1233 to latch a high logic level signal. In addition, the latches 1231, 1232 and 1233 may be reset by the reset control signal RSTB. Therefore, the rising edges of the latch output signals AB_EDGE, BC_EDGE and CA_EDGE are respectively triggered by the XOR output signals AB_X, BC_X and CA_X, and the falling edges of the latch output signals AB_EDGE, BC_EDGE and CA_EDGE are respectively triggered by the reset control signal RSTB.

Then, the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE are sent to an OR gate 1240, which performs an OR operation on the latch output signals AB_EDGE, BC_EDGE, and CA_EDGE, thereby generating a clock signal RCK. The clock signal RCK may be processed by frequency dividers 1271 and 1272 with different divisors (ie, 2 and 7) to generate clock signals for different purposes. The clock signal TCK generated by the frequency divider 1271 will be supplied to the sampling units 1281 and 1282 for sampling the signals AB_S, BC_S and CA_S in order to perform a deserialization operation (wherein the signals AB_S, BC_S and CA_S can be The delay) unit 1260 delays the delay signals AB_D, BC_D and CA_D to output). In addition, the clock signal SCK generated by the frequency divider 1272 will be supplied to circuits such as the data processing units 850 (in FIG. 1 ), 951-952 (in FIG. 3 ) and 1040 (in FIG. 4 ) to perform data processing operate.

On the other hand, the generated clock signal RCK is further sent to the duty cycle correction circuit 1250, thereby generating the reset control signal RSTB. The duty cycle correction circuit 1250 is used to correct the clock signal RCK to achieve a 50% (or about 50%) duty cycle for the clock signal RCK. The duty cycle correction circuit 1250 corrects the clock signal RCK by generating the reset control signal RSTB, thereby realizing a duty cycle of 50%.

As described above, the clock signal RCK is generated by performing an OR operation on the latched output signals AB_EDGE, BC_EDGE and CA_EDGE. Therefore, adjusting the duty cycle of the latch output signals AB_EDGE, BC_EDGE and CA_EDGE (by resetting these signals) can substantially change the duty cycle of the clock signal RCK.

The timing diagram of the processing of the clock signal RCK by the duty cycle correction circuit 1250 is shown in FIG. 13 . When the pulses of signals AB_X, BC_X and CA_X follow the signal transitions of signals AB, BC and CA, the pulses of signals AB_X, BC_X and CA_X are indicated with dashed lines to reflect this. Pulses of signals AB_X, BC_X and CA_X will trigger latches 1231, 1232 and 1233 to transition the latch output signals AB_EDGE, BC_EDGE and CA_EDGE to a high logic level. Also, when the reset control signal RSTB is asserted, the latches 1231, 1232 and 1233 are reset, which causes the latch output signals AB_EDGE, BC_EDGE and CA_EDGE to transition to a low logic level. It should be understood that the timing of the pulse of the reset control signal RSTB may determine the duty cycle of the latch output signals AB_EDGE, BC_EDGE and CA_EDGE, thereby determining the duty cycle of the clock signal RCK.

According to various embodiments of the present invention, the duty cycle correction circuit may have different detailed circuits. Please refer to FIG. 14 , which shows a detailed circuit diagram of an embodiment of the duty cycle correction circuit 1250 . As shown, the duty cycle correction circuit 1500 has a time-to-digital converter (TDC) 1520 . TDC 1520 is used to measure the time difference between adjacent edges of the signals AB_EDGE, BC_EDGE and CA_EDGE, and to convert the measured time difference to a digital (TDC) result accordingly. Selectors 1511 and 1512 are used to select two signals from signals AB_EDGE, BC_EDGE and CA_EDGE to be measured by TDC 1520 . The TDC result is averaged by the digital control circuit logic 1530, and the digital control logic 1530 outputs a delay control signal to control the delay line 1550 according to half of the averaged TDC result. The delay line 1550 is used to delay the clock signal RCK, and the NAND gate 1540 is used to perform a NAND operation on the clock signal RCK and the delayed version of the clock signal RCK, thereby generating the reset control signal RSTB. When the time difference between the signals AB_EDGE, BC_EDGE and CA_EDGE is longer, the duty cycle of the clock signal RCK will be longer, and vice versa. Therefore, the TDC result will reflect this, causing the digital control logic 1530 to find the appropriate delay amount for the delay line to adjust the timing of the reset control signal RSTB so that the clock signal RCK has a duty cycle of about 50%. Note that the NAND gate 1540 can be replaced by another other type of logic gate or combination of logic gates, as long as they can provide the same result.

Please refer to FIGS. 15 and 16 to better understand how the duty cycle correction circuit 1500 actually handles the repeated input pattern "+x→-y→+z→-x→+y→-z→+ representing symbol element 3333333" x" and the repeated input pattern "+x→-z→+y→-x→+z→-y→+x" representing the symbol 1111111.

FIG. 17 shows a detailed circuit diagram of another embodiment of the duty cycle correction circuit 1250 of the present invention. The duty cycle correction circuit 1800 includes a low pass RC filter including a resistive element R and a capacitive element C for filtering the clock signal RCK. A low pass RC filter produces the filtered signal Vduty. The comparator 1810 compares the signal Vduty with a predetermined signal VDD/2 to generate a comparison result UP. The digital control logic 1820 controls the delay line 1840 according to the comparison result UP. Through the low pass RC filter, the duty cycle of the clock signal RCK will be reflected and represented as the voltage level of the signal Vduty. Please refer to Figure 18. As shown in the figure, if the comparator 1810 detects that the voltage level of the signal Vduty is lower than the predetermined signal VDD/2, it means that the duty cycle of the clock signal RCK is lower than 50%. Therefore, the output signal UP of the comparator 1810 remains at the high logic level "1". According to the output signal UP, the digital control logic 1820 generates a delay control signal to adjust the delay time of the delay line 1840 . Once the comparator 1810 detects that the voltage level of the signal Vduty is equal to the predetermined signal VDD/2, it indicates that the duty cycle of the clock signal RCK is 50%. Therefore, the output signal UP of the comparator 1810 becomes a low logic level "0". Therefore, according to the comparison result UP, the digital control logic 1820 controls the delay line 1840 to generate an appropriate delay (; causes the delay to increase or decrease until the comparison result UP shows no difference) to generate the reset control signal RSTB to correct the clock signal RCK , thus achieving a 50% duty cycle.

FIG. 19 is a schematic diagram of a CDR circuit in a receiver for MIPI C-PHY (or other three-wire lane PHY standard) communication connections according to another embodiment of the present invention. The CDR circuit in FIG. 19 shares features and elements with the CDR circuit shown in FIG. 12 . However, the main difference between them is that the embodiment of FIG. 19 utilizes the delay adjustment unit 2000 instead of the duty cycle correction circuit 1200 to generate the reset control signal. The delay adjustment unit 2000 generates the reset control signal RSTB according to the adjustable delay time and the clock signal RCK.

As described above, the clock signal RCK transitions to a high logic level on the rising edges of the signals AB_X, BC_X and CA_X and starts a new cycle. However, as indicated by the circle in Figure 20, if the period of signal BC_edge is too long, the rising edges of signals AB_X and CA_X will be masked. This is caused by wrong timing of reset control signal RSTB. The incorrect timing of reset control signal RSTB resets signal BC_edge too slowly, thus masking the rising edges of signals AB_X and CA_X. In order to prevent the rising edges of the signals AB_X, BC_X and CA_X from being masked, the delay adjustment unit 2000 according to the sampling results AB_O[0], BC_O[0] and CA_O[0] and the sampling results AB_O[1], BC_O[1] and CA_O[ 1], adjust the reset control signal RSTB. Specifically, the delay adjustment unit 2000 detects the XOR output signal XOR[0] of the XOR gate 2091 and the XOR output signal XOR[1] of the XOR gate 2092 . The XOR gate 2091 performs an XOR operation on the sampled results AB_O[0], BC_O[0], and CA_O[0]. The sampling results AB_O[0], BC_O[0] and CA_O[0] are generated by the sampling unit 2081 sampling the signals AB_S, BC_S and CA_S according to the clock signal TCK. The XOR gate 2092 performs an XOR operation on the sampled results AB_O[1], BC_O[1] and CA_O[1]. The sampling results AB_O[1], BC_O[1] and CA_O[1] are generated by the sampling unit 2082 sampling the signals AB_S, BC_S and CA_S according to the inverted version of the clock signal TCK.

The delay adjustment circuit 2000 will start with an initial delay that ensures that the entire CDR circuit in FIG. 19 can function properly. Then, the delay timing of the reset control signal RSTB is slowly increased by the circuit of the delay adjustment circuit 2000 . Once a wrong timing is created, it will be reflected as a signal transition in the XOR output signal XOR[0] and/or the XOR output signal XOR[1]. Once the delay adjustment unit 2000 detects a signal transition of the XOR output signal XOR[0] and/or the XOR output signal XOR[1], it sets the adjustable delay time to half the wrong timing. As a result, the reset control signal RSTB resets the latches 2031-2033 earlier than the wrong timing, which causes the falling edges of the signals AB_EDGE, BC_EDGE, and CA_EDGE to occur earlier without masking the next signal edge. Therefore, the clock signal RCK will reach nearly 50% duty cycle. For example, as shown in the circled portion of Figure 20, if reset control signal RSTB resets latches 2031-2033 earlier than before, the falling edge of latch output signal BC_edge will occur earlier. In this way, the XOR output signals AB_X and CA_X will not be masked by the latch output signal BC_edge, and the clock signal RCK can also appropriately follow the rising edges of the signals AB_X and CA_X.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A physical layer circuit, characterized in that the physical layer circuit comprises: N signal pads, including at least four signal pads; a four-signal physical medium additional sublayer coupled to the four signal pads; and M shielding pads, including at least one first shielding pad and the four-signal physical medium additional sublayer; The first shielding pad is located between a second signal pad and a third signal pad among the four signal pads, and M and N are positive integers. 2 . The physical layer circuit according to claim 1 , wherein when the four-signal physical medium additional sub-layer operates in a first physical layer mode, every two signal connections in the N signal pads are connected. 3 . The pads are set to the same channel, and when the four-signal physical medium additional sublayer operates in a second physical layer mode, every three signal pads of the N signal pads are set to the same channel. 3. A physical layer circuit, wherein the physical layer circuit comprises: N signal pads, including at least six signal pads; a six-signal physical medium additional sublayer, coupled to the six signal pads; and M shielding pads, including at least a first shielding pad, a second shielding pad and a third shielding pad, respectively coupled to the six signal physical medium additional sublayers; The first shielding pad is located between a second signal pad and a third signal pad among the six signal pads; the second shielding pad is located among the six signal pads between the third signal pad and a fourth signal pad; the third shield pad is located between the fourth signal pad and a fifth signal pad among the six signal pads , where M and N are positive integers. 4 . The physical layer circuit of claim 3 , wherein when the six-signal physical medium additional sub-layer operates in a first physical layer mode, every two signal connections in the N signal pads are connected. 5 . The pads are set to the same channel, and when the six-signal physical medium additional sublayer operates in a second physical layer mode, every three signal pads of the N signal pads are set to the same channel. 5. A physical layer circuit, wherein the physical layer circuit comprises: N signal pads, including at least four signal pads; A four-signal physical medium additional sublayer, coupled to the four signal pads, includes: A four-signal termination circuit, coupled to the four signal pads, includes: four adjustable resistive elements, each of which is respectively coupled to one of the four signal pads; a wire coupled between one end of a first adjustable resistive element and one end of a second adjustable resistive element; a first switch selectively coupled between the terminal of the second adjustable resistive element and a terminal of a third adjustable resistive element; and a second switch selectively coupled between the terminal of the third adjustable resistive element and a terminal of a fourth adjustable resistive element; Wherein the first switch is controlled by a switch control signal and the second switch is controlled by an inverted version of the switch control signal. 6. A physical layer circuit, wherein the physical layer circuit comprises: N signal pads, including at least six signal pads; A six-signal physical medium additional sublayer, coupled to the six signal pads, includes: A six-signal termination circuit, coupled to the six signal pads, includes: six adjustable resistive elements, each of which is respectively coupled to one of the six signal pads; a first wire coupled between one end of a first adjustable resistive element and one end of a second adjustable resistive element; a second wire coupled between one end of a fifth adjustable resistive element and one end of a sixth adjustable resistive element; a first switch selectively coupled between the terminal of the second adjustable resistive element and a terminal of a third adjustable resistive element; and a second switch selectively coupled between the terminal of the third adjustable resistive element and a terminal of a fourth adjustable resistive element; a third switch selectively coupled between the terminal of the fourth adjustable resistive element and the terminal of a fifth adjustable resistive element; Wherein the first switch and the third switch are controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

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