CN114510136A - Central processing unit system and power supply management device thereof - Google Patents
Central processing unit system and power supply management device thereof Download PDFInfo
- Publication number
- CN114510136A CN114510136A CN202011289252.2A CN202011289252A CN114510136A CN 114510136 A CN114510136 A CN 114510136A CN 202011289252 A CN202011289252 A CN 202011289252A CN 114510136 A CN114510136 A CN 114510136A
- Authority
- CN
- China
- Prior art keywords
- processing unit
- central processing
- power supply
- module
- voltage signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 title claims abstract description 116
- 238000004891 communication Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The invention provides a central manager system and a power management device thereof, comprising: the power supply module is used for providing working power supply for the device; the output module is connected with the power supply module and used for converting the working power supply into different types of power supply voltage signals and respectively supplying the different types of power supply voltage signals to various types of working modules of the central processing unit; and the communication module is connected with at least part of the sub-modules in the output module and is used for receiving the instruction of the central processing unit and controlling the output voltage signals of at least part of the sub-modules based on the instruction. According to the invention, based on the communication between the single power management device and the central processing unit, the power supply requirements of each working module in the central processing unit can be met, the power supply structure of the central processing unit is simplified, the power supply efficiency of the central processing unit is improved, the cost is greatly reduced, and the reliability and the safety of the whole system are ensured.
Description
Technical Field
The present invention relates to the field of power management, and more particularly to power management for a central processing unit.
Background
Currently, a central processing unit has become the most widely used hardware system architecture in the field of computers. Due to its absolute position in market share, a central processor developed based on it can adapt almost all hardware and software in the personal host and server domains. However, in the hardware system with strong versatility, due to the non-uniformity of the standards in each field, the development investment is insufficient, and in the current hardware system, the integration level of the power management system for supplying power to the central processing unit is very low, for example, for each specific design, the scattered combination of each power supply needs to be performed, even each voltage needs to be separately built with the front and rear stages to meet the time sequence, so that the system requirements are met, and many devices need to be stacked. This not only consumes cost, has reduced the power supply efficiency of power management system, has also caused very big risk to the integrality and the security of central processing unit entire system simultaneously.
Therefore, in the prior art, the integration level of a power management system for supplying power to the central processing unit is very low, so that the power supply structure is complex, the power supply efficiency is low, the cost is not reduced, and the reliability and the safety of the whole system are also reduced.
Disclosure of Invention
The embodiment of the invention provides a central processing unit-based system and a power management device thereof, which at least solve one of the problems of low power management and success rate and low power supply efficiency of the power supply of a central processing unit.
According to a first aspect of the present invention, there is provided a central processor-based power management apparatus, the apparatus comprising:
the power supply module is used for providing working power supply for the device;
the output module is connected with the power supply module and is used for converting the working power supply into different types of power supply voltage signals and respectively supplying the different types of power supply voltage signals to various types of working modules of the central processing unit;
and the communication module is connected with at least part of the sub-modules in the output module and is used for receiving the instruction of the central processing unit and controlling the output voltage signals of at least part of the sub-modules based on the instruction.
Optionally, the output module includes:
and the analog submodule is connected with the power supply module and used for converting the working power supply into at least one analog voltage signal and providing the analog voltage signal to the analog signal module of the central processing unit.
Optionally, the output module includes:
and the digital submodule is connected with the analog submodule and used for converting the at least one analog voltage signal into at least one digital voltage signal and providing the digital voltage signal to a digital signal module of the central processing unit.
Optionally, the at least part of the sub-module comprises:
and the non-service sub-module is connected with the digital sub-module and used for outputting at least one non-service voltage signal based on the first instruction of the central processing unit and providing the non-service voltage signal to the non-service module of the central processing unit.
Optionally, the at least part of the sub-module comprises:
and the core submodule is connected with the power supply module and used for converting the working power supply into a core voltage signal based on a second instruction of the central processing unit and providing the core voltage signal to the core module of the central processing unit.
Optionally, the at least part of the sub-module comprises:
and the memory submodule is connected with the power supply module and used for outputting at least one memory voltage signal based on a third instruction of the central processing unit and providing the memory voltage signal to the memory module of the central processing unit.
Optionally, the communication module comprises:
and the state submodule is used for sending the working state of the output module of the device to the central processing unit.
Optionally, the communication module comprises: the configuration submodule is in configuration communication with the central processing unit and receives a configuration communication signal;
the device further comprises: and the control module is connected with the configuration submodule and used for controlling the device and the central processing unit to be configured based on the configuration communication signal.
According to a second aspect of the present invention, there is provided a central processor system, the system comprising:
the central processing unit is used for processing data;
the power management device according to the first aspect is connected to the central processing unit, and configured to provide different types of power supply voltage signals to various types of operating modules of the central processing unit.
Optionally, the power management apparatus is further configured to:
providing a power supply voltage signal to at least part of the modules of the central processing unit without being based on the instruction of the central processing unit; and
and controlling at least part of the output power supply voltage signal based on the instruction of the central processing unit.
According to the central processing unit system and the power management device thereof, the power supply required by the central processing unit is integrated in the power management device, and the power supply requirements of each working module in the central processing unit can be met based on the communication between a single power management device and the central processing unit, so that the power supply structure of the central processing unit is simplified, the power supply efficiency of the central processing unit is improved, the cost is greatly reduced, and the reliability and the safety of the whole system are ensured.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention when taken in conjunction with the accompanying drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 is a schematic diagram of a central processor-based power management apparatus according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a power management device according to an embodiment of the invention;
fig. 3 is an example of a central processor system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of embodiments of the invention and not all embodiments of the invention, with the understanding that the invention is not limited to the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the invention described herein without inventive step, shall fall within the scope of protection of the invention.
Currently, a central processing unit has become the most widely used hardware system architecture in the field of computers. x86 generally refers to a family of Intel 8086-based, backward compatible central processor instruction set architectures. It is the most widely used hardware system architecture in the field of personal host and server. Due to its absolute position in market share, a central processor developed based on it can adapt almost all hardware and software in the personal host and server domains. However, such a highly versatile architecture is not perfect. Because of the non-uniformity of the standards in various fields and the shortage of development investment, in the current hardware system, the power management system for supplying power to the hardware system still does not achieve better integration level, scattered combination of the power supplies is carried out aiming at each specific design, even each voltage is independently established with a front-stage and a rear-stage to meet the time sequence, the requirement of the system is met, a plurality of devices are required to be stacked, the cost is consumed, the power supply efficiency is reduced, and meanwhile, great risks are caused to the integrity and the safety of the system.
In view of the above, a power management device based on a central processing unit according to an embodiment of the present invention is provided. Referring to fig. 1, fig. 1 shows a schematic diagram of a central processor-based power management apparatus according to an embodiment of the present invention. As shown in fig. 1, the central processor-based power management apparatus 100 may include:
a power module 110, configured to provide a working power supply for the apparatus 100;
an output module 120, connected to the power module 110, for converting the working power into different types of power voltage signals, and providing the different types of power voltage signals to the various types of working modules of the cpu;
a communication module 130 connected to at least some of the output modules 120, configured to receive an instruction of the central processing unit, and control an output voltage signal of the at least some of the sub-modules based on the instruction.
The power management device based on the central processing unit converts the working power supply into different types of power supply voltage signals, and the different types of power supply voltage signals are respectively provided for various types of working modules of the central processing unit, so that various types of power consumption requirements of the central processing unit can be met by a single power management device. The traditional power management technology of the central manager needs to build a power management function through a plurality of power chips/peripheral devices, and needs a CPU and a single embedded controller to carry out a large amount of control, so that the power supply efficiency is low. In contrast, according to the power management device of the embodiment of the invention, all power supply modules are integrated into one device, even packaged into one chip, and the power management device can immediately start to supply power to the central processing unit after being connected (i.e. powered on) with the working power supply, so that the power supply efficiency is greatly improved. The central manager only needs to communicate with a single power supply management device, namely, the power supply voltage signal output by the central manager can be controlled through an instruction, the power supply structure of the central processor is simplified, the cost is greatly reduced, and the reliability and the safety of the whole system are ensured. The power supply device is suitable for being widely applied to any power supply occasions of the central processing unit.
In some embodiments, the power management device 100 may include a chip.
In some embodiments, referring to fig. 1, the power module 110 may include:
optionally, referring to fig. 1, the output module 120 includes:
and the analog sub-module 121 is connected to the power module 110, and configured to convert the working power into at least one analog voltage signal and provide the analog voltage signal to the analog signal module of the central processing unit.
In some embodiments, the simulation submodule 121 may include: and outputting one or more analog voltage signals with different voltage levels.
In some embodiments, referring to fig. 1, the simulation submodule 121 may include:
pin 4, pin 5, pin 6, pin 7: the corresponding signals V1P0A, V1P8A, V1P2A, and V3P3A are the voltage output pins of 1.0V, 1.8V, 1.2V, and 3.3V of the power management device 100, respectively, and can be used as analog power supplies of different modules of the cpu.
Specifically, referring to fig. 1, pins 1, 27 and 28 are all connected to the input end of the voltage clamping and voltage dropping module 121-0, and the output end of the voltage clamping and voltage dropping module 121-0 is connected to the first voltage dropping circuit 121-1, the second voltage dropping circuit 121-2, the third voltage dropping circuit 121-3 and the fourth voltage dropping circuit 121-4, respectively; and the output terminal of the first voltage-dropping circuit 121-1 is connected to pin 4 and the input terminal of the second voltage-dropping circuit 121-2, the output terminal of the second voltage-dropping circuit 121-2 is connected to pin 5 and the input terminal of the third voltage-dropping circuit 121-3, the output terminal of the third voltage-dropping circuit 121-3 is connected to pin 6 and the input terminal of the fourth voltage-dropping circuit 121-4, and the output terminal of the fourth voltage-dropping circuit 121-4 is connected to pin 7.
Optionally, referring to fig. 1, the output module 120 includes:
and a digital sub-module 122, connected to the analog sub-module 121, for converting the at least one analog voltage signal into at least one digital voltage signal and providing the digital voltage signal to a digital signal module of the central processing unit.
In some embodiments, the digital sub-module 122 may include: and outputting one or more voltage level digital voltage signals.
In some embodiments, referring to fig. 1, the digital sub-module 122 may include:
pin 8, pin 9, pin 10, pin 11, pin 12: corresponding signals V1P0S, V1P05S, V1P35S, V1P8S, V3P 3S: the voltage output pins of the power management device 100, which are 1.0V, 1.05V, 1.35V, 1.8V, and 3.3V, can be used as digital power supplies of different modules of the cpu.
Specifically, referring to fig. 1, the output terminal of the first voltage-reducing circuit 122-1 is connected to the first switch 122-5, the first switch 122-5 also receives a signal from the pin 25, and the output terminal of the first switch 122-5 is connected to the pin 8; the output end of the first switch 122-5 and the output end of the second voltage reduction circuit 121-2 are both connected to the input end of the first low dropout regulator LDO1, and the output end of the first low dropout regulator LDO1 is connected to pin 9; the output end of the second voltage reduction circuit 121-2 and the output end of the first low dropout regulator LDO1 are both connected to the input end of the second low dropout regulator LDO2, and the output end of the second low dropout regulator LDO2 is connected to the pin 10; the output end of the second voltage reduction circuit 121-2 and the output end of the second low dropout regulator LDO2 are both connected to the input end of the second switch 122-6, and the output end of the second switch 122-2 is connected to the pin 11; the output terminal of the fourth voltage-decreasing circuit 121-5 and the output terminal of the second switch 122-6 are both connected to the input terminal of the third switch 122-7, and the output terminal of the third switch 122-7 is connected to pin 12.
Optionally, referring to fig. 1, the at least part of the sub-module comprises:
and a non-service sub-module 123, connected to the digital sub-module 122, configured to output at least one non-service voltage signal based on the first instruction of the central processing unit, and provide the non-service voltage signal to a non-service module of the central processing unit.
In some embodiments, the non-service modules may include multimedia modules and/or non-core modules.
In some embodiments, referring to fig. 1, the non-business sub-module 123 may include:
pin 16: the corresponding signal V1P0SX is a 1.0V voltage output pin of the power management device 100, which can be used as a power supply of a multimedia module of the central processing unit;
pin 17: the pin corresponding to the signal VSFR is a 1.35V voltage output pin of the power management apparatus 100, and can be used as a power supply for a non-core module of the cpu.
Specifically, referring to fig. 1, the output terminal of the first low dropout linear regulator LDO1 is connected to the input terminal of the fourth switch 122-8, the output terminal of the second low dropout linear regulator LDO2 is connected to the input terminal of the fifth switch 122-9, the input terminal of the fourth switch 122-8 and the input terminal of the fifth switch 122-9 both receive the first instruction from the central processor through the pin 24, the output terminal of the fourth switch 122-8 and the output terminal of the fifth switch 122-9 are connected to pins 16 and 17, respectively, and the fourth switch 122-8 and the fifth switch 122-9 determine whether to output the corresponding voltage signal based on the first instruction.
Optionally, referring to fig. 1, the at least part of the sub-module comprises:
the memory submodule 124 is connected to the power module 110, and configured to output at least one memory voltage signal based on a third instruction of the central processing unit, and provide the memory voltage signal to the memory module of the central processing unit.
In some embodiments, referring to fig. 1, the memory submodule 124 may include:
pin 18: the corresponding signal VDDQ _ VTT is a 0.75V voltage output pin of the power management device 100, and may provide a reference voltage power supply for a memory (i.e., DDR module) of the cpu;
pin 19: the corresponding signal VDDQ is a 1.5V voltage output pin of the power management device 100, which may be used as a voltage source for the memory (i.e., DDR module) of the cpu.
Specifically, referring to fig. 1, the output terminal of the voltage clamping and voltage dropping module 121-0 is connected to the input terminal of the fifth voltage dropping circuit 122-10, the input terminal of the fifth voltage dropping circuit 122-10 also receives the inverse instruction of the pin 24 (i.e., the instruction of the pin 24 takes logic "inverse" and then is input to the input terminal of the fifth voltage dropping circuit 122-10), the output terminal of the fifth voltage dropping circuit 122-10 is connected to the pin 19, the output terminal of the fifth voltage dropping circuit 122-10 is also grounded through two voltage dividing resistors R1 and R2, and the connection point of the voltage dividing resistors R1 and R2 is connected to the pin 18.
Optionally, referring to fig. 1, the at least part of the sub-module comprises:
and a core sub-module 125, connected to the power module 110, for converting the operating power into a core voltage signal based on a second instruction of the central processing unit, and providing the core voltage signal to the core module of the central processing unit.
In some embodiments, referring to fig. 1, core submodule 125 may include:
pin 20: corresponding to the signal VCC, VCORE core voltage can be provided for the central processing unit;
pin 21: the VGFX core voltage may be provided to the CPU in response to signal VNN.
Specifically, referring to FIG. 1, the output of the voltage clamping and buck module 121-0 is connected to the input of the sixth buck circuit 122-11, the input of the sixth buck circuit 122-11 also receiving the command at pin 25; a first output terminal of the sixth voltage-decreasing circuit 122-11 is connected to pin 20, and a second output terminal of the sixth voltage-decreasing circuit 122-11 is connected to pin 21.
Optionally, referring to fig. 1, the communication module 130 includes:
a status submodule 131, configured to send a working status of the output module of the apparatus to the central processing unit.
In some embodiments, referring to fig. 1, the status sub-module 131 may include:
pin 23: the corresponding signal CORE _ PWROK is used for communicating with the central processing unit and can be used for informing the central processing unit that all pins have output normal voltage signals.
Optionally, referring to fig. 1, the communication module 130 includes: a configuration submodule 132, configured to communicate with the central processing unit, and receive a configuration communication signal;
the apparatus 100 further comprises: a control module 140, connected to the configuration submodule 132, for controlling the apparatus to configure with the central processing unit based on the configuration communication signal.
In some embodiments, referring to fig. 1, the configuration submodule 132 may include:
pin 14, pin 15: is a communication interface of the power management device 100, and is configured to communicate with a central processing unit.
In some embodiments, the control module 140 may include: an embedded core processor.
In some embodiments, the configuration communication may be based on a serial communication protocol. For example I2And C, protocol.
Specifically, referring to fig. 1, the pin 14 receives the signal SDA based on the serial communication protocol, and the pin 15 receives the signal SCL based on the serial communication protocol, and then sends the signal SDA and the signal SCL to the control module 140, so as to complete the configuration of the power management device 100.
Optionally, referring to fig. 1, the communication module 130 may further include:
pin 24: the PMC _ SLP _ S0# signal may be used to notify the power management device 100 that the cpu enters the S0 state and adjust the voltage configuration to the S0 Mode.
In fact, the S0 state of the cpu is a normal operating state, and all devices are operating.
Optionally, referring to fig. 1, the communication module 130 may further include:
pin 25: the PMC _ SLP _ S3# signal may be used to notify the power management device 100 that the cpu enters the S3 state and adjust the voltage configuration to the S3 Mode.
Wherein, the state of S3 of the CPU is Suspend to RAM, that is, all the data in the CPU operation are kept still, and the false shutdown is entered. At this time, except that the memory needs the power supply, all other devices stop supplying power.
Optionally, referring to fig. 1, the communication module 130 may further include:
pin 26: the corresponding signal PMC _ SLP _ S4 may communicate with the cpu, and may notify the power management device 100 that the cpu enters the S4 state, and adjust the voltage configuration to enter the S4 Mode.
The state of the central processing unit S4 is Suspend to Disk, i.e. the data in the memory is completely stored in Disk, and when the central processing unit is restarted, the data is directly and completely read from Disk to RAM; using this mode, Disk requires a complete contiguous space to be left.
In some embodiments, referring to fig. 1, the power management device 100 may further include at least one of:
pin 2: corresponding to the signal REG3P3, which is an internal 3.3V voltage output pin, an external capacitor filters;
pin 3: the corresponding signal VRTC is supplied with power by an external battery and is the input voltage of the real-time clock;
pin 13: the GND pin of the chip is used for grounding;
pin 22: corresponding to PMC _ PLTRST #, a communication pin with the CPU may be used as a central processing unit to RESET (TOTAL RESET) power management device 100.
Referring to fig. 1, pins 1, 27, 28VIN12 and pin 3VRTC in the power management device 100 are powered on, then pin 4V1P0A, pin 5V1P8A, pin 6V1P2A, pin 7V3P3A and the like output analog voltage signals, and the central processing unit notifies the power management device 100 of entering the S4 mode through pin 26PMC _ SLP _ S4 (the actions of the power management device 100 before the pin 26PMC _ SLP _ S4 signal are all self-running, and do not need to be controlled by the central processing unit, so that partial voltage can be supplied to the central processing unit immediately after the pins 1, 27, 28VIN12 are powered on, and partial functions of the central processing unit are enabled to work in the following state); then, the pin 19VDDQ of the power management device 100 is output, and the central processing unit notifies the power management device 100 that the power management device 100 has entered S3 mode through the pin 25PMC _ SLP _ S3 #; the chip continues to output the voltages of pin 21VNN, pin 20VCC, pin 8V1P0S, pin 9V1P05S, pin 10V1P35S, pin 11V1P8S, pin 12V3P3S, etc., and the central processing unit notifies the power management device 100 that the power management device 100 has entered S0 mode through pin 24PMC _ SLP _ S0 #; the power management device 100 then provides the central processor with the VDDQ _ VTT at pin 18, V1P0SX at pin 16, VSFR voltage at pin 17, and informs the CPU that the voltage configuration is complete via pin 23CORE _ PWROK.
Therefore, according to the power management device provided by the embodiment of the invention, the power supply chips of the central processing unit which originally need a plurality of chips and peripheral devices are integrated into one chip, the output state of the power supply chips can be controlled through a plurality of control pins connected with the central processing unit, and the kernel setting of the power management device can be controlled through the I2C standard communication interface, so that the use effect of the power management device is improved. And the power management device according to the embodiment of the present invention can strictly meet the requirements of various central processing units (for example, X86 architecture) on voltage performance and timing, referring to fig. 2, fig. 2 shows a timing diagram of the power management device according to the embodiment of the present invention. The power management device provided by the embodiment of the invention has the advantages of simple structure and high safety and reliability, the power management chip can start partial work immediately after being electrified, the power supply requirement of the central processing unit can be met by controlling the central processing unit in advance, and the power supply efficiency is greatly improved.
According to an embodiment of the present invention, there is also provided a central processing unit system, including:
the central processing unit CPU is used for processing data;
the power supply management device is connected with the central processing unit CPU and used for providing different types of power supply voltage signals for various types of working modules of the central processing unit CPU.
Optionally, the power management apparatus is further configured to:
providing a power supply voltage signal to at least part of the modules of the central processing unit without being based on the instruction of the central processing unit; and
and controlling at least part of the output power supply voltage signal based on the instruction of the central processing unit.
In some embodiments, referring to fig. 3, fig. 3 illustrates an example of a central processor system in accordance with an embodiment of the present invention. As shown in fig. 3, the central processor system 300 includes: a central processing unit CPU; the POWER management device 310, wherein the pins 13 GND/pins 1, 27, 28VIN12 of the POWER management device 310 are respectively connected to the ground and the working POWER (e.g. 12V POWER) of the system;
pins 14, 15 pass through I2The protocol C is communicated with a central processing unit CPU, pins 22-26 are communicated with the central processing unit CPU, and the pins can be subjected to level configuration in a default state by using external pull-up or pull-down resistors;
pins 4-12 and 16-21 are output pins for providing corresponding voltage for the CPU, and are controlled by the power management device 310 in the time sequence of generation and output, so as to sequentially supply power to the CPU and enable corresponding modules to operate, and appropriate grounded parallel capacitors can be placed at the voltage output pins for filtering.
In summary, according to the central processing unit system and the power management device thereof in the embodiments of the present invention, the power required by the central processing unit is integrated in the power management device, and based on the communication between the single power management device and the central processing unit, the power requirements of each working module in the central processing unit can be met, the power supply structure of the central processing unit is simplified, the power supply efficiency of the central processing unit is improved, the cost is greatly reduced, and the reliability and the safety of the whole system are ensured.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A central processing unit-based power management apparatus, the apparatus comprising:
the power supply module is used for providing working power supply for the device;
the output module is connected with the power supply module and used for converting the working power supply into different types of power supply voltage signals and respectively supplying the different types of power supply voltage signals to various types of working modules of the central processing unit;
and the communication module is connected with at least part of the sub-modules in the output module and is used for receiving the instruction of the central processing unit and controlling the output voltage signals of at least part of the sub-modules based on the instruction.
2. The apparatus of claim 1, wherein the output module comprises:
and the analog submodule is connected with the power supply module and used for converting the working power supply into at least one analog voltage signal and providing the analog voltage signal to the analog signal module of the central processing unit.
3. The apparatus of claim 2, wherein the output module comprises:
and the digital submodule is connected with the analog submodule and used for converting the at least one analog voltage signal into at least one digital voltage signal and providing the digital voltage signal to a digital signal module of the central processing unit.
4. The apparatus of claim 3, wherein the at least partial sub-module comprises:
and the non-service sub-module is connected with the digital sub-module and used for outputting at least one non-service voltage signal based on the first instruction of the central processing unit and providing the non-service voltage signal to the non-service module of the central processing unit.
5. The apparatus of claim 1, wherein the at least partial sub-module comprises:
and the core submodule is connected with the power supply module and used for converting the working power supply into a core voltage signal based on a second instruction of the central processing unit and providing the core voltage signal to the core module of the central processing unit.
6. The apparatus of claim 1, wherein the at least partial sub-module comprises:
and the memory submodule is connected with the power supply module and used for outputting at least one memory voltage signal based on a third instruction of the central processing unit and providing the memory voltage signal to the memory module of the central processing unit.
7. The apparatus of claim 1, wherein the communication module comprises:
and the state submodule is used for sending the working state of the output module of the device to the central processing unit.
8. The apparatus of claim 1, wherein the communication module comprises: the configuration submodule is in configuration communication with the central processing unit and receives a configuration communication signal;
the device further comprises: and the control module is connected with the configuration submodule and used for controlling the device and the central processing unit to be configured based on the configuration communication signal.
9. A central processing unit system, the system comprising:
the central processing unit is used for processing data;
the power management device according to any one of claims 1 to 8, connected to the central processor, for providing different types of power supply voltage signals to various types of operating modules of the central processor.
10. The system of claim 9, wherein the power management device is further configured to:
providing a power supply voltage signal to at least part of the modules of the central processing unit without being based on the instruction of the central processing unit; and
and controlling at least part of the output power supply voltage signal based on the instruction of the central processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011289252.2A CN114510136A (en) | 2020-11-17 | 2020-11-17 | Central processing unit system and power supply management device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011289252.2A CN114510136A (en) | 2020-11-17 | 2020-11-17 | Central processing unit system and power supply management device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114510136A true CN114510136A (en) | 2022-05-17 |
Family
ID=81546015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011289252.2A Pending CN114510136A (en) | 2020-11-17 | 2020-11-17 | Central processing unit system and power supply management device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114510136A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714873A (en) * | 1995-12-20 | 1998-02-03 | Samsung Electronics Co., Ltd. | Power supply for automatically supplying a proper voltage to a central processing unit |
| TW200928706A (en) * | 2007-12-31 | 2009-07-01 | Gigabyte United Inc | Method and system for power management of a motherboard |
| CN102118516A (en) * | 2011-01-13 | 2011-07-06 | 中兴通讯股份有限公司 | Control method and system for output voltage of power management chip |
| CN201984307U (en) * | 2011-02-21 | 2011-09-21 | 山东力创科技有限公司 | ARM Cortex M 0 based digital time difference conversion MCU chip |
| US20140122833A1 (en) * | 2009-09-24 | 2014-05-01 | Mark Bradley Davis | Server on a chip and node cards comprising one or more of same |
| CN104578761A (en) * | 2014-12-31 | 2015-04-29 | 苏州普力恩企业管理咨询有限公司 | Central processor power module |
| CN105718014A (en) * | 2016-01-18 | 2016-06-29 | 合肥联宝信息技术有限公司 | Universal integrated computer power module |
| CN106227319A (en) * | 2016-09-20 | 2016-12-14 | 合肥联宝信息技术有限公司 | A kind of power management chip and notebook computer |
| CN111459875A (en) * | 2020-03-31 | 2020-07-28 | 西安微电子技术研究所 | MCU processor and packaging method thereof |
-
2020
- 2020-11-17 CN CN202011289252.2A patent/CN114510136A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714873A (en) * | 1995-12-20 | 1998-02-03 | Samsung Electronics Co., Ltd. | Power supply for automatically supplying a proper voltage to a central processing unit |
| TW200928706A (en) * | 2007-12-31 | 2009-07-01 | Gigabyte United Inc | Method and system for power management of a motherboard |
| US20140122833A1 (en) * | 2009-09-24 | 2014-05-01 | Mark Bradley Davis | Server on a chip and node cards comprising one or more of same |
| CN102118516A (en) * | 2011-01-13 | 2011-07-06 | 中兴通讯股份有限公司 | Control method and system for output voltage of power management chip |
| CN201984307U (en) * | 2011-02-21 | 2011-09-21 | 山东力创科技有限公司 | ARM Cortex M 0 based digital time difference conversion MCU chip |
| CN104578761A (en) * | 2014-12-31 | 2015-04-29 | 苏州普力恩企业管理咨询有限公司 | Central processor power module |
| CN105718014A (en) * | 2016-01-18 | 2016-06-29 | 合肥联宝信息技术有限公司 | Universal integrated computer power module |
| CN106227319A (en) * | 2016-09-20 | 2016-12-14 | 合肥联宝信息技术有限公司 | A kind of power management chip and notebook computer |
| CN111459875A (en) * | 2020-03-31 | 2020-07-28 | 西安微电子技术研究所 | MCU processor and packaging method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11221774B2 (en) | Power down mode for universal flash storage (UFS) | |
| CN107038138B (en) | Universal serial bus power delivery apparatus and system including the same | |
| TWI494863B (en) | Dual-interface card reader module | |
| US8514604B2 (en) | Monitoring system for monitoring serial advanced technology attachment dual in-line memory module | |
| US8607080B2 (en) | Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array | |
| JP2009015752A (en) | Storage device | |
| CN1941542A (en) | Power-supplying circuit | |
| US9195297B2 (en) | Bridging device for connecting to a host executes a power saving operation or a polling operation according to status detected by the connection detector | |
| CN102147652A (en) | Shut-down energy-saving system and shut-down energy-saving method | |
| CN103870429A (en) | High-speed-signal processing board based on embedded GPU | |
| CN101907914A (en) | Computer power starting signal control signal | |
| WO2024051254A1 (en) | Server power supplying method and system, device, and medium | |
| US20130166809A1 (en) | Drive circuit for peripheral component interconnect-express (pcie) slots | |
| CN113835517A (en) | Fast dynamic capacitance, frequency, and/or voltage throttling device and method | |
| US7694163B1 (en) | System for generating and monitoring voltages generated for a variety of different components on a common printed circuit board | |
| CN103853638A (en) | Method for refreshing firmware and electronic equipment | |
| US20190205042A1 (en) | Configurable flush of data from volatile memory to non-volatile memory | |
| CN114510136A (en) | Central processing unit system and power supply management device thereof | |
| US20130134947A1 (en) | Power consumption control method for an electronic system and electronic system thereof | |
| CN221239266U (en) | I.MX6ULL-based small-volume stamp hole core plate | |
| CN112017580B (en) | Display device driving system and electronic apparatus | |
| TWI755926B (en) | Uninterruptible power supply and operation method thereof | |
| CN220829839U (en) | Burning device of mainboard SPI Flash | |
| US8555092B2 (en) | Memory power supply control circuit | |
| CN112650384B (en) | Low-power consumption dormancy awakening control circuit and multi-power-domain control circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |