CN114420711A - Display substrate and preparation method thereof, and display device - Google Patents

Abstract

Display substrate and preparation method, display device thereof, display substrate includes: the substrate comprises a display area and a binding area at least positioned on one side of the display area; and the pixel definition layer is positioned on one side of the substrate and positioned in the display area and the binding area, wherein the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the binding area and the substrate is smaller than the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the display area and the substrate. The scheme provided by the embodiment reduces the thickness of the pixel definition layer positioned in the binding region, reduces the section difference between the pixel definition layer and the binding pad, and can improve the yield of subsequent IC binding.

Description

Display substrate and preparation method thereof, and display device

technical field

The embodiments of the present disclosure relate to, but are not limited to, display technology, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background technique

In the self-luminous display technology, whether it is an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED) display technology, regardless of the printing process or the evaporation process, it is necessary to make a pixel in the pixel. The hole design is convenient for OLED/QLED evaporation or printing related luminescent materials to enter the hole, commonly known as Pixel Definition Layer or Bank Layer (PDL) in the industry. Its Bank thickness is required in vapor deposition or printing design.

SUMMARY OF THE INVENTION

The following is an overview of the topics detailed in this article. This summary is not intended to limit the scope of protection of the claims.

Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, which improve the bonding yield.

In one aspect, an embodiment of the present disclosure provides a display substrate, including:

a substrate, including a display area and a binding area at least on one side of the display area;

The pixel definition layer is located on one side of the substrate, and is located in the display area and the binding area, wherein the surface of the pixel definition layer located in the binding area on the side away from the substrate and the surface of the substrate The shortest distance is smaller than the shortest distance between the surface of the pixel definition layer in the display area on the side away from the substrate and the substrate.

On the other hand, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including:

A pixel definition layer provided with pixel openings is formed on one side of a substrate, the substrate includes a display area and a binding area at least on one side of the display area, the pixel definition layer is disposed on the display area and the binding area a fixed area, the pixel openings are arranged in the display area;

Coat photoresist on the side of the pixel definition layer away from the substrate, and perform halftone mask exposure, development and ashing treatment, so that the bottom of the pixel opening is free of photoresist after development, and after the ashing treatment The sidewall of the pixel opening is at least partially covered with photoresist; and the exposure degree of the photoresist covering the pixel definition layer located in the display area is the same as the exposure degree of the photoresist covering the pixel definition layer located in the binding area. The degree is different, so that after the ashing process, the shortest distance between the surface of the pixel definition layer in the binding area on the side away from the substrate and the substrate is smaller than the distance between the pixel definition layer in the display area and the substrate. the shortest distance between the surface of the side and the substrate;

The photoresist is stripped.

In yet another aspect, an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

Embodiments of the present disclosure include a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a substrate including a display area and a binding area at least on one side of the display area; a pixel definition layer located on the substrate one side, and is located in the display area and the binding area, wherein the shortest distance between the surface of the pixel definition layer located on the side of the binding area away from the substrate and the substrate is smaller than that located in the display area The shortest distance between the surface of the pixel definition layer on the side away from the substrate and the substrate. The solution provided in this embodiment reduces the thickness of the pixel definition layer located in the binding area, reduces the step difference between the pixel definition layer and the binding pad, and can improve the yield of subsequent IC binding.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description and drawings.

Other aspects will become apparent upon reading and understanding of the drawings and detailed description.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present invention, and do not constitute limitations on the technical solutions.

FIG. 1 is a schematic plan view of a display substrate provided by an exemplary embodiment;

FIG. 2 is a cross-sectional view of the display substrate shown in FIG. 1 in the direction AA;

3 is a schematic diagram after forming a gate electrode and a first electrode provided by an exemplary embodiment;

FIG. 4 is a schematic diagram after forming an active layer provided by an exemplary embodiment;

5 is a schematic diagram after forming a source electrode, a drain electrode and a second electrode provided by an exemplary embodiment;

6 is a schematic diagram after forming a second insulating layer provided by an exemplary embodiment;

FIG. 7 is a schematic diagram after forming a flat layer provided by an exemplary embodiment;

8 is a schematic diagram after forming an anode and a third electrode provided by an exemplary embodiment;

9 is a schematic diagram after forming a pixel definition layer provided by an exemplary embodiment;

10 is a schematic diagram after ashing treatment provided by an exemplary embodiment;

FIG. 11 is a schematic diagram of a display substrate provided by another exemplary embodiment;

FIG. 12 is a schematic diagram of a display substrate provided by another exemplary embodiment;

FIG. 13 is a schematic diagram of a display substrate provided by yet another exemplary embodiment;

FIG. 14 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure.

Detailed ways

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

In the drawings, the size of each constituent element, the thickness of a layer, or a region are sometimes exaggerated for clarity. Therefore, embodiments of the present disclosure are not necessarily limited to this size, and the shapes and sizes of components in the drawings do not reflect true scale. Further, the drawings schematically show ideal examples, and embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.

In the present disclosure, ordinal numbers such as "first", "second" and "third" are set to avoid confusion of constituent elements, and do not indicate any order, quantity or importance.

In the present disclosure, "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside" are used for convenience , "outside" and other words indicating orientation or positional relationship are used to describe the positional relationship of constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation. , are constructed and operated in a particular orientation and are therefore not to be construed as limitations of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure, and can be appropriately replaced according to the situation.

In the present disclosure, the terms "installed", "connected" and "connected" should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode . In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. The functions of the "source electrode" and the "drain electrode" may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.

In the present disclosure, "electrically connected" includes the case where constituent elements are connected together by elements having some electrical function. The "element having a certain electrical effect" is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.

In this disclosure, "film" and "layer" are interchangeable. For example, "conductive layer" may be replaced by "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

At present, the mainstream of OLED light-emitting materials is carried out by evaporation process, and the printing technology of light-emitting layer is regarded as the development of OLED&QLED. There are still many difficulties in the current printing technology for the flow properties of ink, among which the roughness of the pixel definition layer is one of the difficulties. One direction of the roughness of the pixel definition layer is to ensure that there is no glue residue in the opening of the pixel definition layer.

In the OLED process, the organic material is ashed with oxygen plasma (O ₂ Plasma), and part of the film thickness of the PDL layer is lost. The evaporation process does not require high surface properties of the material in the PDL hole, but in the QLED luminescent material ink printing process Among them, the ink has high requirements on the hydrophobicity of the material surface. The traditional method of removing glue residue will ashing the hydrophobic layer on the surface of the PDL layer, reducing the hydrophobicity and affecting the subsequent inkjet effect. In an exemplary embodiment, before the ashing process, the pixel definition layer on the sidewall of the pixel opening is protected with a photoresist, so as to avoid destroying the hydrophobicity of the sidewall during the ashing process, and improve the inkjet printing performance. In addition, the ashing process can be used to remove the glue residue in the pixel opening and improve the roughness of the pixel opening.

In addition, since there is no flat layer in the bonding area outside the display area, when the target film thickness of the PDL layer is 2.0um, due to the fluidity of the glue, the thickness of the PDL layer in the Bonding area is about 2.9um, which is relatively high. The assembly leads to the failure of the Bonding IC in the rear section. In an exemplary embodiment, the yield of integrated circuit (Integrated Circuit, IC) bonding can be improved by reducing the thickness of the PDL layer of the bonding region.

FIG. 1 is a schematic plan view of a display substrate provided by an exemplary embodiment. As shown in FIG. 1 , the display substrate includes a substrate 1 , and the substrate 1 includes a display area 100 and a binding area 200 located at least on one side of the display area 100 . The display area 100 includes a plurality of sub-pixels 110 distributed in an array, and the bonding area 200 includes a plurality of bonding pads 210 . At least one of the plurality of sub-pixels 110 includes a thin film transistor, a flat layer and a light-emitting element that are sequentially arranged on the substrate 1 . The flat layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; the light-emitting element is located on the side of the flat layer away from the substrate, and the light-emitting element includes an anode. The sub-pixels 110 are connected to the bonding pads 210 through the data lines 300, and then connected to the external driving circuit through the bonding pads 210. In FIG. 1, only some sub-pixels are shown connected to the bonding pads 210 through the data lines 300. , the rest of the sub-pixels are similar.

FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1 . As shown in FIG. 2 , the display substrate provided in this embodiment includes: a substrate 1 , and the substrate 1 includes a display area 100 and a binding area 200 located at least on one side of the display area 100 . On a plane perpendicular to the substrate 1 of the display substrate, the display substrate includes: a substrate 1, a gate electrode 2 and a first electrode 3 arranged on the substrate 1, and arranged on the gate electrode 2 and the first electrode 3 The first insulating layer 4 on the side of the electrode 3 away from the substrate 1, the active layer 5 on the side of the first insulating layer 4 away from the substrate 1, and the active layer 5 on the side away from the substrate The source-drain electrode layer on one side of 1, the source-drain electrode layer may include a source electrode 6, a drain electrode 7 and a second electrode 8, and a second insulating layer provided on the side of the source-drain electrode layer away from the substrate 1 9. The flat layer 10 arranged on the side of the second insulating layer 9 away from the substrate 1, the anode 11 and the third electrode 12 arranged on the side of the flat layer 10 away from the substrate 1, arranged on the The anode 11 and the third electrode 12 are away from the pixel defining layer 13 on the side of the substrate. The flat layer 10 includes a first flat layer via P1, the anode 11 is electrically connected to the drain electrode 7 through the first flat layer via P1, and the second electrode 8 is electrically connected to the first via K1. The electrode 3, the third electrode 12 is electrically connected to the second electrode 8 through the second via K2.

The gate electrode 2 , the source electrode 6 , the drain electrode 7 , the flat layer 10 and the anode 11 can be arranged in the display area 100 , and the first electrode 3 , the second electrode 8 and the third electrode 12 can be arranged in the bonding area. In the region 200 , the first insulating layer 4 , the second insulating layer 9 and the pixel defining layer 13 may be disposed in the display region 100 and the binding region 200 . The gate electrode 2 , the active layer 5 , the source electrode 6 and the drain electrode 7 constitute the thin film transistor. In another exemplary embodiment, the anode 11 may be electrically connected to the source electrode 6 through the first flat layer via P1.

In an exemplary embodiment, the shortest distance d1 between the surface of the pixel definition layer 13 located in the binding area 200 away from the substrate 1 and the substrate 1 is smaller than that of the pixel definition layer 13 located in the display area 100 The shortest distance d2 between the surface on the side away from the substrate 1 and the substrate 1 . The solution provided in this embodiment reduces the thickness of the pixel definition layer 13 in the binding area, reduces the step difference between the pixel definition layer 13 and the third electrode 12, and can improve the yield of subsequent IC binding. In the present disclosure, the pixel definition layer 13 located in the display area 100 refers to an orthographic projection of the pixel definition layer 13 located in the display area 100 on a plane parallel to the substrate 1 . The pixel definition layer 13 located in the binding area 200 refers to an orthographic projection of the pixel definition layer 13 located in the binding area 200 on a plane parallel to the substrate 1 .

In an exemplary embodiment, 1.5≤d2/d1≤1.9. This is just an example, d2/d1 can be other values.

The technical solution of this embodiment is further described below through the preparation process of the display substrate of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., and is a mature preparation process in the related art. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure and development, and is a mature preparation process in the related art. The deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can use a known coating process, and the etching can use a known method, which is not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a layer of thin film produced by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or a photolithography process in the entire manufacturing process, the "thin film" may also be referred to as a "layer". If the "thin film" needs a patterning process or a photolithography process in the whole manufacturing process, it is called a "thin film" before the patterning process, and a "layer" after the patterning process. A "layer" after a patterning process or a photolithography process contains at least one "pattern". In the present disclosure, "A and B are arranged in the same layer" means that A and B are simultaneously formed through the same patterning process.

(1) Coating a flexible material on a glass carrier, curing it into a film, and forming a substrate 1 . The substrate 1 includes a display area 100 and a binding area 200 . In the embodiment of the present disclosure, the substrate 1 may be a flexible substrate. The flexible material can be made of polyimide PI, polyethylene terephthalate PET or surface-treated soft polymer film. In the exemplary embodiment, the substrate 1 may be a single-layer structure, or may be a multi-layer stack structure. The substrate of the laminated structure may include: flexible material/inorganic material/flexible material, flexible material/inorganic material/amorphous silicon/flexible material/inorganic material, etc. The inorganic material may be a barrier film, such as silicon nitride (SiNx) ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. Taking the PI/Barrier/PI/Barrier laminated structure as an example, the preparation process may include: first coating a layer of polyimide on a glass carrier, curing a film and then depositing a barrier film, and then depositing a barrier film on the barrier film A layer of polyimide is then coated, cured to form a film, and then a barrier film is deposited to form a flexible substrate with a laminated structure.

(2) depositing a first metal film on the substrate 1, patterning the first metal film through a patterning process, to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in the display area 100 , the first electrode 3 is formed in the bonding region 200 , as shown in FIG. 3 .

(3) depositing a first insulating film and an active layer film in sequence, patterning the first insulating film through a patterning process to form a pattern of the first insulating layer 4 provided with the first vias K1, and patterning the active layer film , forming a pattern of the active layer 5, the active layer 5 is formed in the display area 100, the first via K1 exposes the first electrode 3, and the first insulating layer 4 covers the display area 100 and the bonding The fixed area 200 is shown in FIG. 4 .

(4) depositing a second metal film, patterning the second metal film through a patterning process to form a source electrode 6 , a drain electrode 7 and a second electrode 8 , and the second electrode 8 is electrically connected through the first via K1 The first electrode 3 , the source electrode 6 and the drain electrode 7 are formed in the display area 100 , the second electrode 8 is formed in the binding area 200 , and the source electrode 6 and the drain electrode 7 are at least partially disposed in the display area 100 . The surface of the active layer 5 is electrically connected to the active layer 5 ; as shown in FIG. 5 .

(5) depositing a second insulating film, the second insulating film covering the display area 100 and the binding area 200 , as shown in FIG. 6 ;

(6) Coating a flat film, patterning to form a pattern of the flat layer (PLN) 10 and the second insulating layer 9 , the flat layer 10 is provided with a first flat layer via hole P1 , and the first flat layer via hole P1 is formed in the display area 100 , the flat film and the second insulating film in the via hole P1 of the first flat layer are etched away, exposing the surface of the drain electrode 7, the second insulating layer 9 is provided with a second via hole K2, the second via hole K2 The second electrode 8 is exposed; as shown in FIG. 7 , the flat layer 10 is formed in the display area 100 , and the bonding area 200 has no flat layer 10 . In an exemplary embodiment, the flat film can be made of organic materials, such as polyimide, etc.;

In an exemplary embodiment, on a plane parallel to the substrate 1 , the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9 . However, the embodiment of the present disclosure is not limited thereto. On a plane parallel to the substrate 1, the orthographic projection of the second electrode 8 may be partially located outside the orthographic projection of the second insulating layer 9, for example, the second via hole The orthographic projection of K2 may lie within the orthographic projection of the second electrode 8 .

(7) A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, the transparent conductive film is patterned by a patterning process, and the pattern of the anode 11 and the third electrode 12 is formed on the flat layer 10. The anode 11 is formed in the display area 100, and the third The electrode 12 is formed in the bonding area 200, the anode 11 is connected to the drain electrode 7 through the first flat layer via P1 opened on the flat layer 10, and the third electrode 12 is connected to the second electrode 8 through the second via K2, as shown in the figure 8 shown. Among them, the transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO or the like. In an exemplary embodiment, the anode 11 may be an ITO/Ag/ITO, IZO/Ag/IZO multilayer structure, and a transparent conductive film, an Ag film and a transparent conductive film may be deposited in sequence, and then patterned to form the anode 11 .

In an exemplary embodiment, the orthographic projection of the second via hole K2 on the substrate 1 overlaps with the orthographic projection of the first via hole K1 on the substrate 1 .

(8) A pixel definition film is coated on the substrate forming the aforementioned pattern, and a pixel definition layer (PDL) 13 pattern is formed by masking, exposing and developing processes. The pixel definition layer 13 is provided with a pixel opening and a binding opening. The opening is formed in the display area 100, the binding opening is formed in the binding area 200, the pixel definition film in the pixel opening is developed, and the surface of the anode 11 is exposed, and the binding opening exposes the third electrode 12, as shown in FIG. 9 . After this process, there are glue residues 14 in the pixel opening and the binding opening.

In an exemplary embodiment, on a plane parallel to the substrate 1 , the orthographic projection of the bottom of the binding opening may be located within the orthographic projection of the third electrode 12 . In the solution provided in this embodiment, the sidewall of the third electrode 12 is covered by the pixel definition layer 13, which can prevent the sidewall of the third electrode 12 from being damaged in subsequent processes. For example, when the third electrode 12 contains Ag, Ag can be avoided. Oxidized during subsequent ashing treatment with oxygen.

In addition, in the solution provided in this embodiment, the third electrode 12 can be used to protect the second electrode 8 to prevent the second electrode 8 from being oxidized in the subsequent ashing process.

Wherein, the pixel definition layer can be prepared by using polyimide, acrylic, polyethylene terephthalate, or the like.

(9) Coat photoresist on the substrate 1 on which the aforementioned pattern is formed, and perform half-tone mask (Half Tone Mask, HTM) exposure, development and ashing treatment, wherein, when performing half-tone mask exposure, there are Various exposure degrees, so that after development, the bottom of the pixel opening (the surface of the anode 11 away from the substrate 1 side) and the bottom of the binding opening (the surface of the third electrode 12 away from the substrate 1 side) have no Photoresist, the thickness of the photoresist covering the pixel definition layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel definition layer 13 of the binding area 200 (the thickness of the binding area 200 after development) The pixel definition layer 13 may be covered with photoresist, or may not be covered with photoresist); and after the ashing process, the sidewalls of the pixel openings are at least partially covered with photoresist, and the ashing is performed After processing, the thickness of the pixel definition layer in the binding area 200 is reduced after the ashing process (that is, after the ashing process, the thickness of the pixel definition layer in the binding area 200 is smaller than that before the ashing process) The thickness of the pixel definition layer 13 in the area 200), the shortest distance d1 between the surface of the pixel definition layer 13 in the binding area 200 away from the substrate 1 and the substrate 1 is smaller than the pixel definition layer in the display area 100 13 The shortest distance d2 between the surface on the side away from the substrate 1 and the substrate 1 . The glue residues in the pixel openings and the bonding openings are removed.

In the solution provided in this embodiment, since the sidewalls of the pixel openings are protected by photoresist, the hydrophobic layer on the surface of the pixel definition layer on the sidewalls will not be ashed during the ashing process, so that the subsequent inkjet effect will not be affected. In addition, glue residue can be removed to improve pixel roughness. In addition, the thickness of the pixel definition layer in the bonding region 200 can be reduced, thereby improving the yield of subsequent IC bonding.

In an exemplary embodiment, the pixel definition layer 13 of the display area 100 before the ashing process may include: an opening part 131 constituting the sidewall of the pixel opening and a flat part 132 other than the opening part 131 , The method further includes, after the ashing treatment, the thickness of the flat portion 132 along a direction perpendicular to the substrate at least partially is the same as the thickness before the ashing treatment. That is, after the ashing process, in addition to the sidewall (opening portion 131 ) of the pixel opening being covered with photoresist, the flat portion 132 is covered with photoresist to protect the flat portion 132 , so that the pixels of the display area 100 are defined. The layers are not etched away in the ashing process. As shown in FIG. 10 , after the ashing process, the surface of the pixel definition layer of the display area 100 is covered with photoresist 15 to prevent the pixel definition layer of the display area 100 from being etched away during the ashing process. In an exemplary embodiment, after the ashing process, in the display area 100, only the sidewalls of the pixel openings are covered with photoresist, and the flat portion 132 is not covered with photoresist. In this case, the flat portion is The thickness of 132 in a direction perpendicular to the substrate may decrease during ashing. In the solution provided in this embodiment, the sidewall of the pixel opening area is protected by photoresist, and the hydrophobic layer on the surface of the sidewall will not be ashed, so that the subsequent inkjet effect will not be affected.

In an exemplary embodiment, when performing halftone mask exposure, the area 101 where the bottom of the pixel opening is located and the area 201 where the bottom of the binding opening is located are completely exposed, and the display area 100 is excluding the area where the bottom of the pixel opening is located. The area 101 is not exposed, and the binding area 200 is partially exposed except for the area 201 where the bottom of the binding opening is located, so that after development, the areas 101 and 102 are free of photoresist, and the area of the display area 100 except the area 101 is covered. The thickness of the photoresist is greater than the thickness of the photoresist covered by the regions other than the region 201 in the binding region 200 , so that in the subsequent ashing process, the thickness of the pixel definition layer in the binding region 200 is reduced, and at least some pixels in the display region 100 are The thickness of the definition layer does not change.

In an exemplary embodiment, as shown in FIG. 10 , the thickness d3 of the pixel definition layer 13 located in the binding region 200 along the direction perpendicular to the substrate 1 may be 0.8 um to 1 um. When d3 is within this value range, the step difference between the pixel definition layer 13 and the third electrode 12 is small, which can improve the yield of subsequent integrated circuit (Integrated Circuit, IC) bonding. However, the embodiment of the present disclosure is not limited thereto, and the thickness d3 may be other values.

In an exemplary embodiment, as shown in FIG. 10 , the thickness d4 of the pixel definition layer 13 in the display area 100 along the direction perpendicular to the substrate 1 is, for example, 2 um to 3 um.

In an exemplary embodiment, the ashing process may be performed using oxygen plasma, but the embodiments of the present disclosure are not limited thereto, and other gases may be used for the ashing process.

(10) The photoresist 15 is stripped.

The photoresist 15 can be removed by using an organic or inorganic solvent by wet stripping, as shown in FIG. 1 .

In an exemplary embodiment, the first insulating film and the second insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and may be a single-layer structure or a Multilayer composite structure. The first metal film and the second metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (MTD), etc., or the above Metal alloy materials, such as aluminum neodymium alloy (AlNd), molybdenum niobium alloy (MoNb), etc., can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo and the like. The active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials.

In the subsequent process, an organic light-emitting layer, a cathode, an encapsulation layer, etc. may be sequentially formed in the display area 100 to complete the preparation of the display substrate of this embodiment.

Wherein, the organic light-emitting layer may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, and the cathode may be magnesium (Mg), silver (Ag), aluminum (Al), copper One of metal materials such as (Cu), lithium (Li), or an alloy of the above metals, and the encapsulation layer may adopt a laminated structure of inorganic material/organic material/inorganic material.

The structure shown in this embodiment and the preparation process thereof are merely illustrative. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the active layer may be disposed on the side of the gate electrode close to the substrate, that is, the display area 100 may include an active layer, a gate electrode, a source electrode, a drain electrode, and the like disposed in sequence.

FIG. 11 is a schematic diagram of a display substrate provided by another exemplary embodiment. As shown in FIG. 11 , the display substrate provided in this embodiment includes a substrate 1 , and the substrate 1 includes a display area 100 and a binding area 200 located at least on one side of the display area 100 , along a plane perpendicular to the substrate 1 , The display substrate includes: a substrate 1, a gate electrode 2 and a first electrode 3 arranged on the side of the substrate 1 away from the substrate, and arranged on the side of the gate electrode 2 and the first electrode 3 away from the substrate 1 The first insulating layer 4 is arranged on the active layer 5 on the side of the first insulating layer 4 away from the substrate 1, and the source-drain electrode layer is arranged on the side of the active layer 5 away from the substrate 1, The source-drain electrode layer includes a source electrode 6, a drain electrode 7 and a second electrode 8, and a second insulating layer 9 provided on the side of the source-drain electrode layer away from the substrate 1 is provided on the second insulating layer 9. The flat layer 10 on the side away from the substrate 1, the anode 11 and the third electrode 12 are arranged on the side of the flat layer 10 away from the substrate 1, and the anode 11 and the third electrode 12 are arranged on the side away from the The pixel definition layer 13 on the side of the substrate 1 . The anode 11 is electrically connected to the drain electrode 7 through the first flat layer via P1, the second electrode 8 is electrically connected to the first electrode 3 through the first via K1, and the third electrode 12 is electrically connected through the second via K2 is electrically connected to the second electrode 8 . The shortest distance d1 between the surface of the pixel definition layer 13 located in the binding area 200 on the side away from the substrate 1 and the substrate 1 is smaller than that of the pixel definition layer 13 located in the display area 100 on the side away from the substrate 1 . The shortest distance d2 between the surface and the substrate 1 .

Wherein, on a plane parallel to the substrate 1, the orthographic projection of the second electrode 8 overlaps with the orthographic projection of the second insulating layer 9, that is, the second electrode 8 is partially covered by the second via hole K2 exposed. In the previous embodiment, on a plane parallel to the substrate 1, the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9, and all the second electrodes 8 are covered by the second overcoat layer. Hole K2 is exposed.

FIG. 12 is a schematic diagram of a display substrate provided by another exemplary embodiment. As shown in FIG. 12 , the display substrate provided in this embodiment includes a substrate 1 , and the substrate 1 includes a display area 100 and a binding area 200 located at least on one side of the display area 100 , along a plane perpendicular to the substrate 1 , The display substrate includes: a substrate 1, a gate electrode 2 and a first electrode 3 arranged on the substrate 1, and a first insulating layer arranged on the side of the gate electrode 2 and the first electrode 3 away from the substrate 1 4. The active layer 5 arranged on the side of the first insulating layer 4 away from the substrate 1, the source-drain electrode layer arranged on the side of the active layer 5 away from the substrate 1, the source-drain electrodes The layer may include a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 provided on the side of the source-drain electrode layer away from the substrate 1, and a second insulating layer 9 provided on the side of the source-drain electrode layer away from the substrate 1. The flat layer 10 on the side of the substrate 1, the anode 11 and the third electrode 12 on the side of the flat layer 10 away from the substrate 1, and the anode 11 and the third electrode 12 on the side away from the substrate Pixel definition layer 13 . The anode 11 is electrically connected to the drain electrode 7 through the first flat layer via P1, the third electrode 12 is electrically connected to the second electrode 8 through the third via K3, and the third electrode 12 is electrically connected through the fourth The via hole K4 is electrically connected to the first electrode 3 . The first electrode 3 is disposed in the binding area 200 , the second electrode 8 and the third electrode 12 are at least partially disposed in the binding area 200 , the second electrode 8 and the third electrode Parts of the electrodes 12 may be provided in the display area 100 . The shortest distance d1 between the surface of the pixel definition layer 13 located in the binding area 200 on the side away from the substrate 1 and the substrate 1 is smaller than that of the pixel definition layer 13 located in the display area 100 on the side away from the substrate 1 . The shortest distance d2 between the surface and the substrate 1 .

In the solution provided by this embodiment, the third via hole K3 and the fourth via hole K4 can be formed by one patterning process. Compared with the previous embodiment, the first via K1 and the second via hole need to be formed by two patterning processes respectively. K2, can reduce the one-time patterning process, simplify the process, and reduce the cost.

The manufacturing process of the display substrate shown in FIG. 12 is briefly described below, and some details can be referred to the foregoing embodiments, which will not be repeated.

The preparation process of the display substrate provided in this embodiment includes:

(1) Coating a flexible material on a glass carrier, curing to form a film, and forming a substrate 1 , the substrate 1 includes a display area 100 and a binding area 200 .

(2) depositing a first metal film on the substrate 1, patterning the first metal film through a patterning process, to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in the display area 100 , the first electrode 3 is formed in the bonding region 200 .

(3) depositing a first insulating film and an active layer film in turn, patterning the active layer film through a patterning process, forming a pattern of the first insulating layer 4 and the active layer 5, and the active layer 5 is formed in the display area 100, so The first insulating layer 4 covers the display area 100 and the binding area 200 .

(4) depositing a second metal film, patterning the second metal film through a patterning process to form a source electrode 6 , a drain electrode 7 and a second electrode 8 , and the source electrode 6 and the drain electrode 7 are formed in the display area 100 , the second electrode 8 is at least partially formed in the binding region 200 , and the source electrode 6 and the drain electrode 7 are at least partially disposed on the surface of the active layer 5 to achieve electrical connection with the active layer 5 .

In an exemplary embodiment, the second electrode 8 is located on the side of the first electrode 3 close to the display area 100 .

(5) depositing a second insulating film, the second insulating film covering the display area 100 and the binding area 200, as shown in FIG. 5;

(6) Coating a flat film, patterning to form a pattern of the flat layer (PLN) 10 and the second insulating layer 9 , the flat layer 10 is provided with a first flat layer via hole P1 , and the first flat layer via hole P1 is formed in the display area 100 , the flat film and the second insulating film in the via hole P1 of the first flat layer are etched away, exposing the surface of the drain electrode 7, and the second insulating layer 9 is provided with a third via hole K3 and a fourth via hole K4, so The third via hole K3 exposes the second electrode 8 , the fourth via hole K4 exposes the first electrode 3 , the flat layer 10 is formed in the display area 100 , and the bonding area 200 has no flat layer 10 .

(7) A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, the transparent conductive film is patterned by a patterning process, and the pattern of the anode 11 and the third electrode 12 is formed on the flat layer 10. The anode 11 is formed in the display area 100, and the third The electrode 12 is at least partially formed in the bonding region 200 , the anode 11 is electrically connected to the drain electrode 7 through the first planar layer via P1 opened on the planar layer 10 , and the third electrode 12 is electrically connected to the second electrode 8 through the third via K3 . connected, and electrically connected to the first electrode 3 through the fourth via hole K4.

(8) A pixel definition film is coated on the substrate forming the aforementioned pattern, and a pixel definition layer (PDL) 13 pattern is formed by masking, exposing and developing processes. The pixel definition layer 13 is provided with a pixel opening and a binding opening. The opening is formed in the display area 100, the binding opening is formed in the binding area 200, the pixel definition film in the pixel opening is developed, and the surface of the anode 11 is exposed, and the binding opening exposes the third electrode 12, as shown in FIG. 8 shown. After this process, there are glue residues 14 in the pixel opening and the binding opening.

(9) Coating photoresist on the substrate 1 forming the aforementioned pattern, and performing halftone mask exposure, development and ashing treatment, wherein, when performing halftone mask exposure, there are various exposure degrees, so that the development After that, the bottom of the pixel opening (the surface of the anode 11 away from the substrate 1 side) and the bottom of the binding opening (the surface of the third electrode 12 away from the substrate 1 side) are free of photoresist, covering the The thickness of the photoresist of the pixel definition layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel definition layer 13 of the binding area 200 (the pixel definition layer 13 of the binding area 200 may be covered after development) photoresist, or may not be covered with photoresist); and after the ashing process, the sidewalls of the pixel openings are at least partially covered with photoresist, and after the ashing process, the binding The thickness of the pixel definition layer in the region 200 is reduced after the ashing process (that is, after the ashing process, the thickness of the pixel definition layer in the binding region 200 is smaller than the thickness of the pixel definition layer 13 in the binding region 200 before the ashing process. thickness), the shortest distance d1 between the surface of the pixel definition layer 13 located on the side of the binding area 200 away from the substrate 1 and the substrate 1 is smaller than the distance d1 of the pixel definition layer 13 located in the display area 100 away from the substrate The shortest distance d2 between the surface on one side of 1 and the substrate 1 . The glue residues in the pixel openings and the bonding openings are removed.

In the solution provided in this embodiment, since the sidewalls of the pixel openings are protected by photoresist, the hydrophobic layer on the surface of the pixel definition layer on the sidewalls will not be ashed during the ashing process, so that the subsequent inkjet effect will not be affected. In addition, glue residue can be removed to improve pixel roughness. In addition, the thickness of the pixel definition layer in the bonding region 200 can be reduced, thereby improving the yield of subsequent IC bonding.

(10) The photoresist 15 is stripped.

FIG. 13 is a schematic diagram of a display substrate provided by another exemplary embodiment. The display substrate provided in this embodiment may include a substrate 1, the substrate 1 includes a display area 100 and a binding area 200 at least on one side of the display area 100, the display area 100 may include a plurality of sub-pixels, and at least one sub-pixel is included in the substrate The thin film transistor, the flat layer and the light emitting element are arranged in sequence on the top. The flat layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; the light-emitting element is located on the side of the flat layer away from the substrate, and the light-emitting element includes an anode. The thin film transistor includes an active layer located on the substrate, a gate electrode located on a side of the active layer away from the substrate, and a source electrode and a drain electrode located on the side of the gate electrode away from the substrate, And one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first flat layer via hole. As shown in FIG. 13 , the display substrate provided in this embodiment may include: a substrate 1 , an active layer 5 disposed on the substrate 1 , a fourth layer disposed on the side of the active layer 5 away from the substrate 1 The insulating layer 16 is arranged on the gate electrode 2 and the first electrode 3 on the side of the fourth insulating layer 16 away from the substrate 1 , and is arranged on the side of the gate electrode 2 and the first electrode 3 away from the substrate 1 . The first insulating layer 4 is a source-drain electrode layer disposed on the side of the first insulating layer 4 away from the substrate 1 . The source-drain electrode layer may include a source electrode 6 , a drain electrode 7 and a second electrode 8 . The second insulating layer 9 on the side of the source-drain electrode layer away from the substrate 1, the flat layer 10 on the side of the second insulating layer 9 away from the substrate 1, and the flat layer 10 on the side away from the substrate 1 The anode 11 and the third electrode 12 on the side of the substrate 1 are disposed on the pixel definition layer 13 on the side of the anode 11 and the third electrode 12 away from the substrate. The flat layer 10 includes a first flat layer via hole P1, the anode 11 is electrically connected to the drain electrode 7 through the first flat layer via hole P1, and the second electrode 8 is electrically connected to the first via hole K1. The electrode 3 and the third electrode 12 are electrically connected to the second electrode 8 through the second via K2 , and the source electrode 6 and the drain electrode 7 are electrically connected to the active layer 5 . The shortest distance d1 between the surface of the pixel definition layer 13 located in the binding area 200 on the side away from the substrate 1 and the substrate 1 is smaller than that of the pixel definition layer 13 located in the display area 100 on the side away from the substrate 1 . The shortest distance d2 between the surface and the substrate 1 . In this embodiment, the thin film transistor includes an active layer 5 , a gate electrode 2 , a source electrode 6 and a drain electrode 7 which are sequentially arranged on the substrate 1 . For the preparation of the display substrate described in this embodiment, after the active layer 5 and the fourth insulating layer 16 are formed, the subsequent preparation may refer to the foregoing embodiments, which will not be repeated.

FIG. 14 is a flowchart of a method for fabricating a display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 14 , the preparation method of the display substrate provided by the embodiment of the present disclosure may include:

Step 1401, forming a pixel definition layer provided with pixel openings on a substrate;

Step 1402: Coat photoresist on the side of the pixel definition layer away from the substrate, and perform mask exposure, development and ashing treatment, so that the bottom of the pixel opening is free of photoresist after development, and after the ashing treatment The sidewall of the pixel opening is at least partially covered with photoresist;

Step 1403, stripping the photoresist.

In the preparation method of the display substrate provided in this embodiment, photoresist is used to protect the sidewall of the pixel opening, so as to prevent the surface of the sidewall of the pixel opening from being damaged in hydrophobicity during the ashing process, thereby improving the effect of subsequent inkjet printing. In addition, Residual glue in pixel openings can be removed to improve pixel roughness.

In an exemplary embodiment, the substrate includes a display area and a binding area at least on one side of the display area, the pixel definition layer is disposed on the display area and the binding area, and the pixel openings set in the display area;

The mask exposure is a halftone mask exposure, wherein the exposure degree of the photoresist covering the pixel definition layer located in the display area is the same as the exposure degree of the photoresist covering the pixel definition layer located in the binding area. different, so that after the ashing process, the shortest distance between the surface of the pixel definition layer located in the binding area on the side away from the substrate and the substrate is smaller than that of the pixel definition layer located in the display area away from the substrate. The shortest distance between the surface and the substrate.

In an exemplary embodiment, the pixel definition layer located in the display area before the ashing process includes: an opening part forming a sidewall of the pixel opening and a flat part other than the opening part, and the method further includes: , the thickness of the flat portion at least partially along the direction perpendicular to the substrate after the ashing treatment is the same as the thickness before the ashing treatment.

In an exemplary embodiment, the forming a pixel definition layer provided with pixel openings on the substrate includes:

forming a pixel definition layer provided with the pixel opening and the binding opening on the substrate, and the binding opening is arranged in the binding area;

The method further includes, after developing, making the bottom of the binding opening free of photoresist.

In an exemplary embodiment, before forming the pixel definition layer provided with the pixel opening on the substrate, the method further includes:

forming a first electrode on the substrate, the first electrode being formed in the binding region;

A first insulating layer provided with a first via hole is formed on the side of the first electrode away from the substrate, and the first via hole exposes the first electrode;

A second electrode is formed on the side of the first insulating layer away from the substrate, the second electrode is electrically connected to the first electrode through the first via hole, and the second electrode is formed in the bonding area ;

forming a second insulating layer on the side of the second electrode away from the substrate;

forming a flat layer on the side of the second insulating layer away from the substrate, and forming a second via hole exposing the second electrode;

A third electrode is formed on the side of the flat layer away from the substrate, the third electrode is formed in the binding region, and the third electrode and the second electrode are electrically connected through the second via hole, The binding opening exposes the third electrode.

In an exemplary embodiment, before forming the pixel definition layer provided with the pixel opening on the substrate, the method further includes:

forming a first electrode on the substrate, the first electrode being formed in the binding region;

forming a first insulating layer on the side of the first electrode away from the substrate;

A second electrode is formed on the side of the first insulating layer away from the substrate; the second electrode is formed at least partially in the binding region;

forming a second insulating layer on the side of the second electrode away from the substrate;

forming a flat layer on the side of the second insulating layer away from the substrate, and forming a third via hole exposing the second electrode and a fourth via hole exposing the first electrode;

A third electrode is formed on the side of the flat layer away from the substrate, the third electrode is formed at least partially in the bonding region, and the third electrode and the second electrode are electrically connected to each other through the third via hole connection, the third electrode and the first electrode are electrically connected through the fourth via hole, and the binding opening exposes the third electrode.

In an exemplary embodiment, before forming the pixel definition layer provided with the pixel opening on the substrate, the method further includes:

A gate electrode is formed between the substrate and the first insulating layer, the gate electrode is formed in the display region, and the gate electrode and the first electrode are formed through the same patterning process;

A source electrode and a drain electrode are formed between the first insulating layer and the second insulating layer; the source electrode and the drain electrode are formed in the display area, and the source electrode, the drain electrode and the second electrode Formed by the same patterning process;

An anode is formed on the side of the flat layer away from the substrate, the anode is formed in the display area, the pixel opening exposes the anode, and the anode and the third electrode are formed through the same patterning process.

An embodiment of the present disclosure provides a display substrate, and the display substrate is prepared by using the method for preparing a display substrate described in any one of the above embodiments. In the display substrate provided in this embodiment, by protecting the pixel definition layer on the sidewall of the pixel opening, the hydrophobicity of the surface of the pixel definition layer on the sidewall of the pixel opening is prevented from being damaged during ashing treatment, the inkjet printing effect is improved, and the Remove glue residue and improve pixel roughness.

In an exemplary embodiment, the display substrate includes a display area and a binding area located at least on one side of the display area, and the pixel definition layer is disposed on the display area and the binding area, and is located in the display area and the binding area. The shortest distance between the surface of the pixel definition layer in the binding area on the side away from the substrate and the substrate is smaller than the shortest distance between the surface of the pixel definition layer in the display area on the side away from the substrate and the substrate. In the display substrate provided in this embodiment, the thickness of the pixel definition layer in the binding area is smaller than the thickness of the pixel definition layer in the display area, which can reduce the level difference between the pixel definition layer and the electrodes in the binding opening and improve the binding yield.

In an exemplary embodiment, the thickness of the pixel definition layer located in the binding region along a direction perpendicular to the substrate is 0.8 micrometers to 1 micrometer.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode and a third electrode sequentially arranged on the substrate, and the first electrode, the second electrode and the third electrode are arranged on the substrate. In the binding area, the second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode and a third electrode sequentially arranged on the substrate, the first electrode is arranged in the binding area, and the first electrode is arranged in the binding area. The second electrode and the third electrode are at least partially disposed in the binding area, the third electrode is electrically connected to the second electrode through a third via hole, and the third electrode is electrically connected to the second electrode through a fourth via hole first electrode.

In an exemplary embodiment, the pixel definition layer further includes a binding opening exposing the third electrode, and on a plane parallel to the substrate, an orthographic projection of the bottom of the binding opening may be located on the third electrode. The electrodes are in the orthographic projection of .

Embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments. The display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (15)

1. A display substrate, characterized in that, comprising: a substrate, including a display area and a binding area at least on one side of the display area; The pixel definition layer is located on one side of the substrate, and is located in the display area and the binding area, wherein the surface of the pixel definition layer located in the binding area on the side away from the substrate and the surface of the substrate The shortest distance is smaller than the shortest distance between the surface of the pixel definition layer in the display area on the side away from the substrate and the substrate. 2 . The display substrate according to claim 1 , wherein the shortest distance between the surface of the pixel definition layer located on the side of the binding area away from the substrate and the substrate is d1 . The shortest distance between the surface of the pixel definition layer on the side away from the substrate and the substrate is d2, and 1.5≤d2/d1≤1.9. 3 . The display substrate of claim 1 , wherein a thickness of the pixel definition layer located in the binding region along a direction perpendicular to the substrate is 0.8 μm to 1 μm. 4 . 4 . The display substrate according to claim 1 , wherein the display substrate further comprises a first electrode, a second electrode and a third electrode arranged on the substrate in sequence, the first electrode, the second electrode An electrode and a third electrode are arranged in the binding area, the second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole. 5 . The display substrate according to claim 1 , wherein the display substrate further comprises a first electrode, a second electrode and a third electrode arranged on the substrate in sequence, and the first electrode is arranged on the base. 6 . the binding area, the second electrode and the third electrode are at least partially disposed in the binding area, the third electrode is electrically connected to the second electrode through a third via hole, and the third electrode is electrically connected to the second electrode through a third via hole. The fourth via hole is electrically connected to the first electrode. 6. The display substrate according to claim 4 or 5, wherein the pixel definition layer further comprises a binding opening exposing the third electrode, and on a plane parallel to the substrate, the binding opening is The orthographic projection of the bottom is within the orthographic projection of the third electrode. 7. The display substrate according to claim 4 or 5, wherein the display substrate further comprises a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels comprises a thin film transistor, a flat layer and a light-emitting element; the flat layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; The light-emitting element is located on the side of the flat layer away from the substrate, and the light-emitting element includes an anode; the planarization layer includes a first planarization layer via hole; The thin film transistor includes a gate electrode located on the substrate, an active layer located on a side of the gate electrode away from the substrate, and a source electrode and a drain electrode located on the side of the active layer away from the substrate, and one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first flat layer via hole; The third electrode and the anode are arranged in the same layer. 8. The display substrate according to claim 7, wherein the first electrode and the gate electrode are disposed in the same layer; The second electrode is disposed in the same layer as the source electrode or the drain electrode. 9 . The display substrate according to claim 4 , wherein the display substrate further comprises a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels comprises a thin film transistor, a flat layer and light-emitting element; the flat layer is located on the side of the thin film transistor away from the substrate to cover the thin film transistor; The light-emitting element is located on the side of the flat layer away from the substrate, and the light-emitting element includes an anode; the planarization layer includes a first planarization layer via hole; The thin film transistor includes an active layer located on the substrate, a gate electrode located on a side of the active layer away from the substrate, and a source electrode and a drain electrode located on the side of the gate electrode away from the substrate, and one of the source electrode and the drain electrode is electrically connected to the anode of the light-emitting element through the first flat layer via hole; The third electrode is arranged in the same layer as the anode, the first electrode is arranged in the same layer as the gate electrode, and the second electrode is arranged in the same layer as the source electrode or the drain electrode. 10. A display device, comprising the display substrate according to any one of claims 1 to 9. 11. A method for preparing a display substrate, comprising: A pixel definition layer provided with pixel openings is formed on one side of a substrate, the substrate includes a display area and a binding area at least on one side of the display area, the pixel definition layer is disposed on the display area and the binding area a fixed area, the pixel openings are arranged in the display area; Coat photoresist on the side of the pixel definition layer away from the substrate, and perform halftone mask exposure, development and ashing treatment, so that the bottom of the pixel opening is free of photoresist after development, and after the ashing treatment The sidewall of the pixel opening is at least partially covered with photoresist; and the exposure degree of the photoresist covering the pixel definition layer located in the display area is the same as the exposure degree of the photoresist covering the pixel definition layer located in the binding area. The degree is different, so that after the ashing process, the shortest distance between the surface of the pixel definition layer in the binding area on the side away from the substrate and the substrate is smaller than the distance between the pixel definition layer in the display area and the substrate. the shortest distance between the surface of the side and the substrate; The photoresist is stripped. 12 . The method for manufacturing a display substrate according to claim 11 , wherein the pixel definition layer located in the display area before the ashing process comprises: an opening part forming a sidewall of the pixel opening and an opening except for the opening. 13 . and the method further includes, after the ashing treatment, the thickness of the flat portion along a direction perpendicular to the substrate at least in part is the same as the thickness before the ashing treatment. 13 . The method for manufacturing a display substrate according to claim 11 , wherein the forming a pixel definition layer provided with pixel openings on the substrate comprises: 13 . forming a pixel definition layer provided with the pixel opening and the binding opening on the substrate, and the binding opening is arranged in the binding area; The method further includes, after developing, making the bottom of the binding opening free of photoresist. 14 . The method for manufacturing a display substrate according to claim 13 , wherein before forming the pixel definition layer provided with the pixel openings on the substrate, the method further comprises: 14 . forming a first electrode on the substrate, the first electrode being formed in the binding region; A first insulating layer provided with a first via hole is formed on the side of the first electrode away from the substrate, and the first via hole exposes the first electrode; A second electrode is formed on the side of the first insulating layer away from the substrate, the second electrode is electrically connected to the first electrode through the first via hole, and the second electrode is formed in the bonding area ; forming a second insulating layer on the side of the second electrode away from the substrate; forming a flat layer on the side of the second insulating layer away from the substrate, and forming a second via hole exposing the second electrode; A third electrode is formed on the side of the flat layer away from the substrate, the third electrode is formed in the binding region, and the third electrode and the second electrode are electrically connected through the second via hole, The binding opening exposes the third electrode. 15. The method for manufacturing a display substrate according to claim 13, wherein before forming the pixel definition layer provided with the pixel opening on the substrate, further comprising: forming a first electrode on the substrate, the first electrode being formed in the binding region; forming a first insulating layer on the side of the first electrode away from the substrate; A second electrode is formed on the side of the first insulating layer away from the substrate, and the second electrode is at least partially formed in the binding region; forming a second insulating layer on the side of the second electrode away from the substrate; forming a flat layer on the side of the second insulating layer away from the substrate, and forming a third via hole exposing the second electrode and a fourth via hole exposing the first electrode; A third electrode is formed on the side of the flat layer away from the substrate, the third electrode is formed at least partially in the bonding region, and the third electrode and the second electrode are electrically connected to each other through the third via hole connection, the third electrode and the first electrode are electrically connected through the fourth via hole, and the binding opening exposes the third electrode.

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