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CN114400918B - Carrier PWM modulation method of three-phase T-type three-level double-output inverter - Google Patents

Carrier PWM modulation method of three-phase T-type three-level double-output inverter Download PDF

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CN114400918B
CN114400918B CN202210113255.3A CN202210113255A CN114400918B CN 114400918 B CN114400918 B CN 114400918B CN 202210113255 A CN202210113255 A CN 202210113255A CN 114400918 B CN114400918 B CN 114400918B
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bipolar transistor
insulated gate
gate bipolar
phase
diode
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CN114400918A (en
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王秀云
吴雪东
薛彪
袁帅
王汝田
刘闯
蔡国伟
陈继开
郭东波
张嘉伟
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Northeast Electric Power University
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Northeast Dianli University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention relates to a carrier PWM modulation method of a three-phase T-type three-level double-output inverter, which is characterized in that for the three-phase T-type three-level double-output inverter, the method of modulating upper and lower groups of modulating waves respectively compared with in-phase laminated carriers is utilized, and logic operation for generating driving signals of each power switch is deduced according to the switch state and the modulation comparison result, so that the single direct current input voltage of the three-phase T-type three-level double-output inverter is converted into two groups of three-phase alternating current voltages with adjustable frequency and amplitude, and the method has the advantages of good output waveform quality, easiness in implementation and the like.

Description

Carrier PWM modulation method of three-phase T-type three-level double-output inverter
Technical Field
The invention relates to the field of power electronics, in particular to a carrier PWM modulation method of a three-phase T-shaped three-level double-output inverter.
Background
In recent years, the double-alternating-current output system has been applied to the fields of electric automobiles, rail traction, wind power generation and the like. The core of the double alternating current output system is a double output inverter. At present, the research on the two-level double-output inverter is mature, but the research on the two-level double-output inverter cannot meet the requirement of the high-voltage high-capacity double-output inverter in the current power industry. Three-level versus two-level inverters have many advantages, such as: lower harmonic distortion rate, higher efficiency, etc. Therefore, three-level double-output inverters are proposed, but the research on the three-level double-output inverters is less at the present stage, and the modulation method of the three-phase T-type three-level double-output inverter is not reported in the prior literature.
Disclosure of Invention
The invention aims at providing a carrier PWM modulation method of a three-phase T-type three-level double-output inverter, which can compare upper and lower groups of modulation waves with in-phase laminated carriers respectively, deduce logic operation for generating driving signals of each power switch according to a switch state and a modulation comparison result, and has the advantages of scientific and reasonable design, strong applicability, simple modulation and good effect.
The invention aims at realizing the following technical scheme: a carrier PWM modulation method of a three-phase T-shaped three-level double-output inverter comprises the following steps: the three-phase T-type three-level double-output inverter consists of a direct-current side capacitor C 1, a capacitor C 2, 18 power switching devices and 18 diodes, wherein the three-phase T-type three-level double-output inverter is provided with a phase A, a phase B and a phase C bridge arm, each phase bridge arm of the phase A, the phase B and the phase C bridge arm consists of 6 power switches S x1～Sx6 and 6 diodes D x1～Dx6, wherein x is { A, B, C }; the capacitance values of the direct current side capacitor C 1 and the capacitor C 2 of the three-phase T-type three-level double-output inverter are equal, the direct current side input voltage is U d, the three-phase T-type three-level double-output inverter is provided with two groups of output ends, the upper group of output ends are defined as x1, the upper group of output phase voltages are defined as U x1O, the lower group of output ends are defined as x2, and the lower group of output phase voltages are defined as U x2O, wherein x epsilon { A, B, C }; two groups of output ends of the three-phase T-shaped three-level double-output inverter are respectively connected with two groups of three-phase loads, the upper groups of output ends are respectively connected with a three-phase load Z A1、ZB1、ZC1, and the lower groups of output ends are respectively connected with a three-phase load Z A2、ZB2、ZC2, so that the output of two groups of three-phase alternating currents can be realized; the method is characterized by also comprising the following steps:
(1) The upper group output phase voltage and the lower group output phase voltage of the three-phase T-shaped three-level double-output inverter have a constraint relation, namely, the upper group output phase voltage is more than or equal to the lower group output phase voltage, so 6 power switches of each phase bridge arm of the three-phase T-shaped three-level double-output inverter have 6 reasonable switch states in total:
Switch state 1: the power switches S x1、Sx2、Sx3 and S x5 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both U d/2;
switch state 2: the power switches S x1、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltage U x1O is U d/2,ux2O and is 0;
Switch state 3: the power switches S x1、Sx4、Sx5 and S x6 are turned on, and at the moment, the output phase voltage U x1O is U d/2,ux2O and is-U d/2;
Switch state 4: the power switches S x2、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltages u x1O and u x2O are both 0;
Switch state 5: the power switches S x2、Sx4、Sx5 and S x6 are turned on, at this time, the output phase voltage U x1O is 0, and U x2O is-U d/2;
Switch state 6: the power switches S x2、Sx3、Sx4 and S x6 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both-U d/2;
(2) The three-phase T-shaped three-level double-output inverter adopts a carrier PWM modulation method, uses two triangular carriers v c1 and v c2, adopts an in-phase lamination mode, namely the phases and the frequencies of the two triangular carriers v c1、vc2 are the same, the variation range of v c1 is 0-1, and the variation range of v c2 is-1-0;
The upper group output phase voltage u x1O and the lower group output phase voltage u x2O are controlled by using two groups of modulation waves v x1 and v x2 respectively, wherein x is { A, B, C }, and the formula of the upper group modulation wave v x1 is as follows:
Wherein omega 1、φ1、m1 and V offset1 are respectively the angular frequency, the initial phase angle, the modulation degree and the direct current offset of the upper group modulation wave V x1, the value range of m 1 is 0 to 1, and the value of V offset1 is 1-m 1;
The following set of modulated wave v x2 formula is:
Wherein omega 2、φ2、m2 and V offset2 are the angular frequency, the initial phase angle, the modulation degree and the DC offset of the modulated wave V x2 of the following group, the value range of m 2 is 0 to 1, and the value of V offset2 is 1-m 2;
Because the three-phase T-shaped three-level double-output inverter has a constraint relation that the voltage of an upper group output phase is more than or equal to that of a lower group output phase, the voltage of an upper group modulation wave v x1 is more than or equal to that of a lower group modulation wave v x2;
(3) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have the same frequency and phase, namely the frequencies and phases of u x1O and u x2O are the same, and the angular frequencies and the initial phase angles of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are respectively equal, namely omega 1＝ω2＝ω,φ1＝φ2 =phi; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; The upper set output phase voltage u x1O in the other case is 0; ② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; If the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
under the condition that u x1O、ux2O is in the same frequency and phase, the peak time of the upper group modulation wave v x1、vx2 and the peak time of the lower group modulation wave v x1、vx2 are the same, and direct current offset exists, the modulation degrees m 1、m2 of the upper group modulation wave and the lower group modulation wave are not affected, so that the value range of m 1、m2 is expressed as follows:
(4) The same frequency and different phases of the upper group output phase voltage u x1O and the lower group output phase voltage u x2O, namely the frequencies of u x1O and u x2O are the same, the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are equal, and the initial phase angles are different, namely omega 1＝ω2＝ω,φ1≠φ2; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; The upper set output phase voltage u x1O in the other case is 0; ② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; If the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
under the condition of u x1O、ux2O being in the same frequency and out of phase, setting a displacement angle delta phi 1-φ2 phi between the modulated waves v x1 and v x2, wherein delta phi is more than or equal to 0 and pi is more than or equal to pi; from the constraint relationship of v x1≥vx2, it is derived that m 1 and m 2 should satisfy the constraint relationship:
m1 sin(ωt+Δφ)+1-m1≥m2 sinωt-(1-m2)
(5) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have different frequencies, namely u x1O and u x2O have different frequencies, so that the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are not equal, namely omega 1≠ω2; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; the upper set output phase voltage u x1O in the other case is 0;
② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; if the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
in the u x1O、ux2O inter-frequency situation, according to the constraint relation of v x1≥vx2, m 1 and m 2 should satisfy the constraint relation:
0＜m1+m2≤1
(6) Deriving logic operation of driving signals of each power switch of each phase bridge arm of the three-phase T-shaped three-level double-output inverter by combining the switch states and the modulation comparison results;
the driving signal of the 6 power switches S x1～Sx6 of each phase bridge arm is S x1～sx6; the value of the driving signal is 1, which indicates that the power switch is turned on; the value of the driving signal is 0, which indicates that the power switch is turned off;
The upper group of modulated waves v x1 are compared with the carrier wave v c1, and a driving signal S x1 of the power switch S x1 is generated according to the comparison result, wherein the specific expression is as follows:
The following group of modulated waves v x2 and carrier waves v c2 are compared, and a driving signal S x4 of a power switch S x4 is generated according to the comparison result, wherein the specific expression is as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 1, expressed as:
Comparing the upper group modulation wave v x1 with the carrier wave v c1 to generate a signal e 2, wherein the expression is as follows:
Comparing the upper group modulation wave v x1 with the carrier wave v c2 to generate a signal e 3, wherein the expression is as follows:
Signal e 4 is generated from signal e 2 and signal e 3 as follows:
e4＝e2 AND e3
wherein the symbol "AND" represents a logical AND operation;
Comparing the upper group modulation wave v x1 with the carrier wave v c2 to generate a signal e 5, wherein the expression is as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 6, expressed as:
The following set of modulated waves v x2 and carrier v c2 are compared to generate a signal e 7, expressed as:
Signal e 8 is generated from signal e 6 and signal e 7 as follows:
e8＝e6 AND e7
The driving signal S x2 of the power switch S x2 is generated by the signal e 1, the signal e 4 and the signal e 5, and expressed as:
sx2＝e1 OR e4 OR e5
wherein the symbol "OR" represents a logical OR operation;
the driving signal S x3 of the power switch S x3 is generated by the signal e 1, the signal e 8 and the signal e 5, and expressed as:
sx3＝e1 OR e8 OR e5
The driving signal S x5 of the power switch S x5 is generated by the driving signal S x4 and the signal e 5, and the expression is:
sx5＝NOT(sx4 AND e5)
Wherein the symbol "NOT" represents a logical "NOT" operation;
The driving signal S x6 of the power switch S x6 is generated by the driving signal S x1 and the signal e 1, and the expression is:
sx6＝NOT(sx1 AND e1)
(7) According to the steps (1) - (6), driving signals of 18 power switches of the three-phase T-type three-level double-output inverter can be obtained, carrier PWM modulation is completed, and the inverter outputs two groups of three-phase symmetrical alternating-current voltages.
The carrier PWM modulation method of the three-phase T-shaped three-level double-output inverter provided by the invention has the advantages that the upper and lower groups of modulation waves are respectively compared with the in-phase laminated carrier waves, and each power switch driving signal is obtained through logic operation, so that a single direct current input voltage can be converted into two groups of three-phase alternating current output voltages with adjustable frequency and amplitude, and the method is scientific and reasonable, strong in applicability, simple in modulation, good in output waveform quality and good in effect.
Drawings
Fig. 1 is a topological schematic diagram of a three-phase T-type three-level dual-output inverter;
FIG. 2 is a schematic diagram showing a comparison of a modulated wave and a carrier wave under the same frequency and phase conditions;
FIG. 3 is a diagram showing a comparison of a modulated wave and a carrier wave in the same frequency and different phases;
FIG. 4 is a diagram showing a comparison of a modulated wave and a carrier wave in case of different frequencies;
FIG. 5 is a logic diagram of generating an x-phase bridge arm power switch drive signal;
FIG. 6 is a graph of waveforms of the upper set of output three-phase currents under a first set of simulation parameters;
FIG. 7 is a plot of the waveform of the lower set of output three-phase currents under the first set of simulation parameters;
FIG. 8 is a graph of waveforms of the upper set of output phase voltages under a first set of simulation parameters;
FIG. 9 is a waveform diagram of the lower set of output phase voltages under the first set of simulation parameters;
FIG. 10 is a graph of waveforms of the upper set of output three-phase currents under a second set of simulation parameters;
FIG. 11 is a plot of the waveform of the lower set of output three-phase currents under the second set of simulation parameters;
FIG. 12 is a graph of waveforms of the upper set of output phase voltages under a second set of simulation parameters;
FIG. 13 is a waveform diagram of the lower set of output phase voltages under the second set of simulation parameters;
FIG. 14 is a graph of waveforms of the upper set of output three-phase currents under a third set of simulation parameters;
FIG. 15 is a plot of a lower set of output three-phase current waveforms for a third set of simulation parameters;
FIG. 16 is a graph of waveforms of the upper set of output phase voltages under a third set of simulation parameters;
fig. 17 is a waveform diagram of the lower set of output phase voltages under the third set of simulation parameters.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The carrier PWM modulation method of the three-phase T-type three-level double-output inverter can effectively control the frequency and the amplitude of two groups of output voltages. The topology of a three-phase T-type three-level dual output inverter is shown in fig. 1. As can be seen from the figure, the three-phase T-type three-level dual-output inverter is composed of a dc side capacitor C 1 and a capacitor C 2, 18 power switching devices and 18 diodes. The three-phase T-shaped three-level double-output inverter is provided with three-phase bridge arms which are respectively defined as an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm, wherein each phase bridge arm consists of 6 power switches S x1～Sx6 and 6 diodes D x1～Dx6, and x is { A, B and C }. The capacitance values of the direct current side capacitor C 1 and the capacitor C 2 of the three-phase T-type three-level double-output inverter are equal, the direct current side input voltage is U d, the three-phase T-type three-level double-output inverter is provided with two groups of output ends, the upper group of output ends are defined as x1, the upper group of output phase voltages are defined as U x1O, the lower group of output ends are defined as x2, the lower group of output phase voltages are defined as U x2O, and x epsilon { A, B, C }. Two groups of output ends of the three-phase T-shaped three-level double-output inverter are respectively connected with two groups of three-phase loads, the upper groups of output ends are respectively connected with a three-phase load Z A1、ZB1、ZC1, and the lower groups of output ends are respectively connected with a three-phase load Z A2、ZB2、ZC2, so that the output of two groups of three-phase alternating currents can be realized.
In order to avoid the unavailable switching state, the upper group output phase voltage and the lower group output phase voltage of the three-phase T-shaped three-level double-output inverter have a constraint relation, namely, the upper group output phase voltage is more than or equal to the lower group output phase voltage, so 6 power switches of each phase bridge arm of the three-phase T-shaped three-level double-output inverter have 6 reasonable switching states, and the 6 reasonable switching states are as follows:
Switch state 1: the power switches S x1、Sx2、Sx3 and S x5 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both U d/2;
switch state 2: the power switches S x1、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltage U x1O is U d/2,ux2O and is 0;
Switch state 3: the power switches S x1、Sx4、Sx5 and S x6 are turned on, and at the moment, the output phase voltage U x1O is U d/2,ux2O and is-U d/2;
Switch state 4: the power switches S x2、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltages u x1O and u x2O are both 0;
Switch state 5: the power switches S x2、Sx4、Sx5 and S x6 are turned on, at this time, the output phase voltage U x1O is 0, and U x2O is-U d/2;
Switch state 6: the power switches S x2、Sx3、Sx4 and S x6 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both-U d/2;
The three-phase T-shaped three-level double-output inverter adopts a carrier PWM modulation method, uses two triangular carriers v c1 and v c2, adopts an in-phase lamination mode, namely the phases and the frequencies of the two triangular carriers v c1、vc2 are the same, the variation range of v c1 is 0-1, and the variation range of v c2 is-1-0.
The upper group output phase voltage of each phase bridge arm of the three-phase T-shaped three-level double-output inverter is more than or equal to the lower group output phase voltage, and can be realized by adding direct current offset into two groups of modulation waves. The upper group output phase voltage u x1O and the lower group output phase voltage u x2O are controlled by using two groups of modulation waves v x1 and v x2 respectively, wherein x is { A, B, C }, and the formula of the upper group modulation wave v x1 is as follows:
wherein omega 1、φ1、m1 and V offset1 are the angular frequency, the initial phase angle, the modulation degree and the direct current offset of the upper group modulation wave V x1 respectively, the value range of m 1 is 0 to 1, and the value of V offset1 is 1-m 1.
The following set of modulated wave v x2 formula is:
Wherein omega 2、φ2、m2 and V offset2 are the angular frequency, the initial phase angle, the modulation degree and the DC offset of the modulated wave V x2 respectively, the value range of m 2 is 0 to 1, and the value of V offset2 is 1-m 2.
Because the three-phase T-shaped three-level double-output inverter has a constraint relation of the output phase voltages of the upper group under the output phase voltages, the upper group modulation wave v x1 is more than or equal to the lower group modulation wave v x2. There are three possible cases according to the relative relationship between the angular frequency and the initial phase angle of the two modulated waves, and each case is described in detail below.
(1) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have the same frequency and phase, i.e. the frequencies and phases of u x1O and u x2O are the same, and the angular frequencies and the initial phase angles of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are respectively equal, i.e. ω 1＝ω2＝ω,φ1＝φ2 =phi. As shown in fig. 2, the upper and lower groups of modulated waves v x1、vx2 and carrier v c1、vc2 are compared with two triangular carrier v c1、vc2 by modulated waves v x1、vx2, and the upper and lower groups of output phase voltages u x1O、ux2O are determined by the following specific comparison method:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; The upper set output phase voltage u x1O in the other cases is 0. ② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; If the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; The lower set of output phase voltages u x2O in the other cases is 0. The upper and lower sets of output phase voltages u x1O、ux2O are shown in fig. 2.
Under the condition that u x1O、ux2O is in the same frequency and phase, the peak time of the upper group modulation wave v x1、vx2 and the peak time of the lower group modulation wave v x1、vx2 are the same, and direct current offset exists, the modulation degrees m 1、m2 of the upper group modulation wave and the lower group modulation wave are not affected, so that the value range of m 1、m2 is expressed as follows:
(2) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have the same frequency and different phases, namely u x1O and u x2O have the same frequency and different phases, and the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are equal, and the initial phase angles are different, namely omega 1＝ω2＝ω,φ1≠φ2. As shown in fig. 3, the upper and lower groups of modulated waves v x1、vx2 and carrier v c1、vc2 are compared with two triangular carrier v c1、vc2 by modulated waves v x1、vx2, and the upper and lower groups of output phase voltages u x1O、ux2O are determined by the following specific comparison method:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; the upper set output phase voltage u x1O in the other cases is 0.
② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; if the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in the other cases is 0. The upper and lower sets of output phase voltages u x1O、ux2O are shown in fig. 3.
Under the condition of u x1O、ux2O being in the same frequency and out of phase, setting a displacement angle delta phi 1-φ2 phi between the modulated waves v x1 and v x2, wherein delta phi is more than or equal to 0 and pi is more than or equal to pi; from the constraint relationship of v x1≥vx2, it is derived that m 1 and m 2 should satisfy the following constraint relationship:
m1 sin(ωt+Δφ)+1-m1≥m2 sinωt-(1-m2) (4)
The relationship according to m 1、m2 and Δφ is divided into the following two cases:
① Given m 1 and Δφ, the range of values for m 2 can be determined as follows:
Given m 1 and Δφ, the maximum value of m 2 is also related to ωt. Therefore, to ensure that the output voltage is not distorted, the maximum value achieved by m 2 should take into account the variation of ωt from-pi to pi.
② In some applications, it is required that m 1＝m2 =m, substituted into formula (5) and sorted into the following expression:
When considering the variation of ωt from-pi to pi, the relationship of m and Δφ inequality described by equation (6) is further reduced to:
The formula (5) and the formula (7) provide a constraint relation between the modulation degree m 1、m2 and the displacement angle delta phi, and provide guiding measures for fully utilizing the direct-current side voltage U d.
(3) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have different frequencies, i.e. u x1O and u x2O have different frequencies, so that the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are not equal, i.e. ω 1≠ω2. The upper and lower sets of modulated waves v x1、vx2 and carrier v c1、vc2 are shown in fig. 4. The modulated wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; the upper set output phase voltage u x1O in the other cases is 0.
② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; if the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in the other cases is 0. The upper and lower sets of output phase voltages u x1O、ux2O are shown in fig. 4.
In the u x1O、ux2O inter-frequency case, according to the constraint relation of v x1≥vx2, m 1 and m 2 should satisfy the following constraint relation:
0＜m1+m2≤1 (8)
Equation (8) shows that the sum of modulation degrees of the two sets of outputs is 1 at the maximum in the case of different frequencies. The possible, typical value ranges according to formulae (8) and m 1、m2 can be divided into the following three cases:
① The modulation degree m 1 is more than 0.5, modulation m 2 is less than or equal to 0.5: the upper set of output phase voltages U x1O will have three levels U d/2, 0 and-U d/2; the lower set of modulated waves v x2 < carrier v c1 results in a lower set of output phase voltages U x2O having only two levels of 0 and-U d/2, the number of phase voltage levels decreasing at low modulation levels.
② The modulation degree m 2 is more than 0.5, modulation m 1 is less than or equal to 0.5: the lower set of output phase voltages U x2O will have three levels U d/2, 0 and-U d/2; the upper group modulation wave v x1 > carrier v c2, resulting in an upper group output phase voltage U x1O having only two levels of U d/2 and 0, the number of phase voltage levels decreasing at low modulation levels.
③ The modulation degree m 2 is less than or equal to 0.5, modulation m 1 is less than or equal to 0.5: the upper group modulation wave v x1 > carrier v c2, resulting in an upper group output phase voltage U x1O having only two levels U d/2 and 0; the lower set of modulated waves v x2 < carrier v c1 results in a lower set of output phase voltages U x2O having only two levels of 0 and-U d/2, the number of phase voltage levels decreasing at low modulation levels.
The carrier PWM modulation method of the three-phase T-type three-level dual output inverter described above in three cases, i.e., the level of the output phase voltage is determined by the comparison result of the modulated wave and the carrier wave. And combining the analyzed conclusion and 6 reasonable switch states, and further analyzing and generating logic operation of each power switch driving signal.
The driving signal of 6 power switches S x1～Sx6 of each phase bridge arm of the three-phase T-type three-level double-output inverter is S x1～sx6; the value of the driving signal is 1, which indicates that the power switch is turned on; the value of the driving signal is 0, which indicates that the power switch is turned off;
The upper group of modulated waves v x1 are compared with the carrier wave v c1, and a driving signal S x1 of the power switch S x1 is generated according to the comparison result, wherein the specific expression is as follows:
The following group of modulated waves v x2 and carrier waves v c2 are compared, and a driving signal S x4 of a power switch S x4 is generated according to the comparison result, wherein the specific expression is as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 1, expressed as follows:
comparing the upper group modulated wave v x1 with the carrier wave v c1 to generate a signal e 2, expressed as follows:
Comparing the upper group modulated wave v x1 with the carrier wave v c2 to generate a signal e 3, expressed as follows:
Signal e 4 is generated from signal e 2 and signal e 3 as follows:
e4＝e2 AND e3 (14)
wherein the symbol "AND" represents a logical AND operation.
Comparing the upper group modulated wave v x1 with the carrier wave v c2 to generate a signal e 5, expressed as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 6, expressed as follows:
The following set of modulated waves v x2 and carrier v c2 are compared to generate a signal e 7, expressed as follows:
Signal e 8 is generated from signal e 6 and signal e 7 as follows:
e8＝e6 AND e7 (18)
From the 6 reasonable switching states, the power switch S x2 is turned on when the lower output phase voltage U x2O is U d/2, or the upper output phase voltage U x1O is 0, or the upper output phase voltage U x1O is-U d/2. The driving signal S x2 of the power switch S x2 is generated from the signal e 1, the signal e 4 and the signal e 5 as follows:
sx2＝e1 OR e4 OR e5 (19)
Wherein the symbol "OR" represents a logical OR operation.
From the 6 reasonable switching states, the power switch S x3 is turned on when the lower output phase voltage U x2O is U d/2, or the lower output phase voltage U x2O is 0, or the upper output phase voltage U x1O is-U d/2. The driving signal S x3 of the power switch S x3 is generated from the signal e 1, the signal e 8 and the signal e 5 as follows:
sx3＝e1 OR e8 OR e5 (20)
from the 6 reasonable switching states, the power switch S x5 is turned off when the upper set of output phase voltages U x1O is-U d/2 and the lower set of output phase voltages U x2O is-U d/2. The driving signal S x5 of the power switch S x5 is generated from the driving signal S x4 and the signal e 5 as follows:
sx5＝NOT(sx4 AND e5) (21)
Wherein the symbol "NOT" represents a logical "NOT" operation.
From the 6 reasonable switching states, the power switch S x6 is turned off when the upper output phase voltage U x1O is U d/2 and the lower output phase voltage U x2O is U d/2. The driving signal S x6 of the power switch S x6 is generated from the driving signal S x1 and the signal e 1 as follows:
sx6＝NOT(sx1 AND e1) (22)
from the above analysis, a logic circuit for generating a power switch driving signal can be obtained, as shown in FIG. 5, where symbols are shown The comparison operation is represented, when the positive electrode "+" input signal is more than or equal to the negative electrode "-" input signal, the output is high level "1", otherwise, the output is low level "0".
The method can obtain the driving signals of 18 power switches of the three-phase T-shaped three-level double-output inverter, so that carrier PWM modulation is completed, and the inverter outputs two groups of three-phase symmetrical alternating-current voltages.
In order to verify the effectiveness of the carrier PWM modulation method, a simulation circuit is built through MATLAB/Simulink. The first set of simulation parameters (same frequency and phase conditions) is as follows: the switching frequency is 5kHz, the direct current voltage is 200V, the upper and lower groups of three-phase load resistors are 10Ω, the inductance is 10mH, the modulation degree m 1 of the upper group of modulation waves is 0.9, the angular frequency omega 1 is 100 pi, the modulation degree m 2 of the lower group of modulation waves is 0.9, The angular frequency omega 2 is 100 pi, and the phase angle difference delta phi of two groups of modulation waves is 0; The second set of simulation parameters (same frequency out of phase case) is as follows: the switching frequency is 5kHz, the direct current voltage is 200V, the upper group three-phase load resistance is 10Ω, the inductance is 10mH, the modulation degree m 1 of the upper group modulation wave is 0.65, the angular frequency omega 1 is 100 pi, the lower group three-phase load resistance is 10Ω, the inductance is 10mH, the modulation degree m 2 of the lower group modulation wave is 0.65, The angular frequency omega 2 is 100 pi, and the phase angle difference delta phi of two groups of modulation waves is 60 degrees; The third set of simulation parameters (inter-frequency case) is as follows: the switching frequency is 5kHz, the direct current voltage is 200V, the upper group three-phase load resistance is 10Ω, the inductance is 10mH, the modulation degree m 1 of the upper group modulation wave is 0.5, the angular frequency omega 1 is 100 pi, the lower group three-phase load resistance is 10Ω, the inductance is 10mH, the modulation degree m 2 of the lower group modulation wave is 0.5, the angular frequency omega 2 is 200 pi. The simulation results are shown in fig. 6 to 17, wherein the three-phase output current and the output phase voltage under the first group of simulation parameters are shown in fig. 6 to 9, the three-phase output current and the output phase voltage under the second group of simulation parameters are shown in fig. 10 to 13, and the three-phase output current and the output phase voltage under the third group of simulation parameters are shown in fig. 14 to 17. As can be seen from the simulation results, the carrier PWM modulation method can ensure that the three-phase T-shaped three-level double-output inverter can output two groups of three-phase alternating-current voltages with adjustable amplitude and frequency.
Although the present invention has been described above with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are illustrative and not restrictive, and other forms may be made by those skilled in the art without departing from the spirit of the present invention, which are all within the protection of the present invention.

Claims (1)

1. A carrier PWM modulation method of a three-phase T-shaped three-level double-output inverter comprises the following steps: the three-phase T-type three-level double-output inverter consists of a direct-current side capacitor C 1, a capacitor C 2, 18 power switching devices and 18 diodes, wherein the three-phase T-type three-level double-output inverter is provided with a phase A, a phase B and a phase C bridge arm, each phase bridge arm of the phase A, the phase B and the phase C bridge arm consists of 6 power switches S x1～Sx6 and 6 diodes D x1～Dx6, wherein x is { A, B, C }; the capacitance values of the direct current side capacitor C 1 and the capacitor C 2 of the three-phase T-type three-level double-output inverter are equal, the direct current side input voltage is U d, the three-phase T-type three-level double-output inverter is provided with two groups of output ends, the upper group of output ends are defined as x1, the upper group of output phase voltages are defined as U x1O, the lower group of output ends are defined as x2, and the lower group of output phase voltages are defined as U x2O, wherein x epsilon { A, B, C };
The positive electrode of the capacitor C 1 is connected with the positive electrode P of the direct current bus, and the negative electrode of the capacitor C 1 is connected with the midpoint O; the positive electrode of the capacitor C 2 is connected with the midpoint O, and the negative electrode of the capacitor C 2 is connected with the negative electrode end N of the direct current bus;
The A-phase bridge arm comprises an insulated gate bipolar transistor S A1, an insulated gate bipolar transistor S A2, an insulated gate bipolar transistor S A3, an insulated gate bipolar transistor S A4, an insulated gate bipolar transistor S A5 and an insulated gate bipolar transistor S A6; diode D A1, diode D A2, diode D A3, diode D A4, diode D A5, diode D A6;
A collector of the insulated gate bipolar transistor S A1 is connected to the cathode of the diode D A1 and to the positive terminal P of the dc bus, and an emitter of the insulated gate bipolar transistor S A1 is connected to the anode of the diode D A1 and to the collector of the insulated gate bipolar transistor S A2 and to the upper output terminal A1; the collector of insulated gate bipolar transistor S A2 is connected to the cathode of diode D A2, An emitter of insulated gate bipolar transistor S A2 is connected to an anode of diode D A2 and to a collector of insulated gate bipolar transistor S A6 and a collector of insulated gate bipolar transistor S A3; The collector of insulated gate bipolar transistor S A6 is connected to the cathode of diode D A6, and the emitter of insulated gate bipolar transistor S A6 is connected to the anode of diode D A6 and to the emitter of insulated gate bipolar transistor S A5; An emitter of the insulated gate bipolar transistor S A5 is connected to an anode of the diode D A5, and a collector of the insulated gate bipolar transistor S A5 is connected to a cathode of the diode D A5 and to the midpoint O; The collector of the insulated gate bipolar transistor S A3 is connected with the cathode of the diode D A3, and the emitter of the insulated gate bipolar transistor S A3 is connected with the anode of the diode D A3 and is connected to the collector of the insulated gate bipolar transistor S A4 and the lower output end A2 of an external three-phase load; The collector of the insulated gate bipolar transistor S A4 is connected with the cathode of the diode D A4, and the emitter of the insulated gate bipolar transistor S A4 is connected with the anode of the diode D A4 and connected to the negative terminal N of the direct current bus;
The B-phase bridge arm comprises an insulated gate bipolar transistor S B1, an insulated gate bipolar transistor S B2, an insulated gate bipolar transistor S B3, an insulated gate bipolar transistor S B4, an insulated gate bipolar transistor S B5 and an insulated gate bipolar transistor S B6; diode D B1, diode D B2, diode D B3, diode D B4, diode D B5, diode D B6;
A collector of the insulated gate bipolar transistor S B1 is connected to the cathode of the diode D B1 and to the positive terminal P of the dc bus, and an emitter of the insulated gate bipolar transistor S B1 is connected to the anode of the diode D B1 and to the collector of the insulated gate bipolar transistor S B2 and to the upper output terminal B1; the collector of insulated gate bipolar transistor S B2 is connected to the cathode of diode D B2, An emitter of insulated gate bipolar transistor S B2 is connected to an anode of diode D B2 and to a collector of insulated gate bipolar transistor S B6 and a collector of insulated gate bipolar transistor S B3; the collector of insulated gate bipolar transistor S B6 is connected to the cathode of diode D B6, and the emitter of insulated gate bipolar transistor S B6 is connected to the anode of diode D B6 and to the emitter of insulated gate bipolar transistor S B5; An emitter of the insulated gate bipolar transistor S B5 is connected to an anode of the diode D B5, and a collector of the insulated gate bipolar transistor S B5 is connected to a cathode of the diode D B5 and to the midpoint O; the collector of the insulated gate bipolar transistor S B3 is connected to the cathode of the diode D B3, the emitter of the insulated gate bipolar transistor S B3 is connected to the anode of the diode D B3 and to the collector of the insulated gate bipolar transistor S B4 and the lower output terminal B2 of the external three-phase load; the collector of the insulated gate bipolar transistor S B4 is connected with the cathode of the diode D B4, and the emitter of the insulated gate bipolar transistor S B4 is connected with the anode of the diode D B4 and connected to the negative terminal N of the direct current bus;
The C-phase bridge arm comprises an insulated gate bipolar transistor S C1, an insulated gate bipolar transistor S C2, an insulated gate bipolar transistor S C3, an insulated gate bipolar transistor S C4, an insulated gate bipolar transistor S C5 and an insulated gate bipolar transistor S C6; diode D C1, diode D C2, diode D C3, diode D C4, diode D C5, diode D C6;
A collector of the insulated gate bipolar transistor S C1 is connected to the cathode of the diode D C1 and to the positive terminal P of the dc bus, and an emitter of the insulated gate bipolar transistor S C1 is connected to the anode of the diode D C1 and to the collector of the insulated gate bipolar transistor S C2 and to the upper output terminal C1; The collector of insulated gate bipolar transistor S C2 is connected to the cathode of diode D C2, an emitter of insulated gate bipolar transistor S C2 is connected to an anode of diode D C2 and to a collector of insulated gate bipolar transistor S C6 and a collector of insulated gate bipolar transistor S C3; The collector of insulated gate bipolar transistor S C6 is connected to the cathode of diode D C6, and the emitter of insulated gate bipolar transistor S C6 is connected to the anode of diode D C6 and to the emitter of insulated gate bipolar transistor S C5; An emitter of the insulated gate bipolar transistor S C5 is connected to an anode of the diode D C5, and a collector of the insulated gate bipolar transistor S C5 is connected to a cathode of the diode D C5 and to the midpoint O; The collector of the insulated gate bipolar transistor S C3 is connected to the cathode of the diode D C3, the emitter of the insulated gate bipolar transistor S C3 is connected to the anode of the diode D C3 and to the collector of the insulated gate bipolar transistor S C4 and the lower output terminal C2 of the external three-phase load; The collector of the insulated gate bipolar transistor S C4 is connected with the cathode of the diode D C4, and the emitter of the insulated gate bipolar transistor S C4 is connected with the anode of the diode D C4 and connected to the negative terminal N of the direct current bus;
Two groups of output ends of the three-phase T-shaped three-level double-output inverter are respectively connected with two groups of three-phase loads, the upper groups of output ends are respectively connected with a three-phase load Z A1、ZB1、ZC1, and the lower groups of output ends are respectively connected with a three-phase load Z A2、ZB2、ZC2, so that the output of two groups of three-phase alternating currents can be realized; the method is characterized by also comprising the following steps: (1) The upper group output phase voltage and the lower group output phase voltage of the three-phase T-shaped three-level double-output inverter have a constraint relation, namely, the upper group output phase voltage is more than or equal to the lower group output phase voltage, so 6 power switches of each phase bridge arm of the three-phase T-shaped three-level double-output inverter have 6 reasonable switch states in total:
Switch state 1: the power switches S x1、Sx2、Sx3 and S x5 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both U d/2;
switch state 2: the power switches S x1、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltage U x1O is U d/2,ux2O and is 0;
Switch state 3: the power switches S x1、Sx4、Sx5 and S x6 are turned on, and at the moment, the output phase voltage U x1O is U d/2,ux2O and is-U d/2;
Switch state 4: the power switches S x2、Sx3、Sx5 and S x6 are turned on, and at this time, the output phase voltages u x1O and u x2O are both 0;
Switch state 5: the power switches S x2、Sx4、Sx5 and S x6 are turned on, at this time, the output phase voltage U x1O is 0, and U x2O is-U d/2;
Switch state 6: the power switches S x2、Sx3、Sx4 and S x6 are turned on, and at the moment, the output phase voltages U x1O and U x2O are both-U d/2;
(2) The three-phase T-shaped three-level double-output inverter adopts a carrier PWM modulation method, uses two triangular carriers v c1 and v c2, adopts an in-phase lamination mode, namely the phases and the frequencies of the two triangular carriers v c1、vc2 are the same, the variation range of v c1 is 0-1, and the variation range of v c2 is-1-0;
The upper group output phase voltage u x1O and the lower group output phase voltage u x2O are controlled by using two groups of modulation waves v x1 and v x2 respectively, wherein x is { A, B, C }, and the formula of the upper group modulation wave v x1 is as follows:
Wherein omega 1、φ1、m1 and V offset1 are respectively the angular frequency, the initial phase angle, the modulation degree and the direct current offset of the upper group modulation wave V x1, the value range of m 1 is 0 to 1, and the value of V offset1 is 1-m 1;
The following set of modulated wave v x2 formula is:
Wherein omega 2、φ2、m2 and V offset2 are the angular frequency, the initial phase angle, the modulation degree and the DC offset of the modulated wave V x2 of the following group, the value range of m 2 is 0 to 1, and the value of V offset2 is 1-m 2;
Because the three-phase T-shaped three-level double-output inverter has a constraint relation that the voltage of an upper group output phase is more than or equal to that of a lower group output phase, the voltage of an upper group modulation wave v x1 is more than or equal to that of a lower group modulation wave v x2;
(3) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have the same frequency and phase, namely the frequencies and phases of u x1O and u x2O are the same, and the angular frequencies and the initial phase angles of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are respectively equal, namely omega 1＝ω2＝ω,φ1＝φ2 =phi; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; The upper set output phase voltage u x1O in the other case is 0; ② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; If the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
under the condition that u x1O、ux2O is in the same frequency and phase, the peak time of the upper group modulation wave v x1、vx2 and the peak time of the lower group modulation wave v x1、vx2 are the same, and direct current offset exists, the modulation degrees m 1、m2 of the upper group modulation wave and the lower group modulation wave are not affected, so that the value range of m 1、m2 is expressed as follows:
(4) The same frequency and different phases of the upper group output phase voltage u x1O and the lower group output phase voltage u x2O, namely the frequencies of u x1O and u x2O are the same, the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are equal, and the initial phase angles are different, namely omega 1＝ω2＝ω,φ1≠φ2; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; The upper set output phase voltage u x1O in the other case is 0; ② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; If the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
under the condition of u x1O、ux2O being in the same frequency and out of phase, setting a displacement angle delta phi 1-φ2 phi between the modulated waves v x1 and v x2, wherein delta phi is more than or equal to 0 and pi is more than or equal to pi; from the constraint relationship of v x1≥vx2, it is derived that m 1 and m 2 should satisfy the constraint relationship:
m1 sin(ωt+Δφ)+1-m1≥m2 sinωt-(1-m2)
(5) The upper group output phase voltage u x1O and the lower group output phase voltage u x2O have different frequencies, namely u x1O and u x2O have different frequencies, so that the angular frequencies of the upper group modulation wave v x1、vx2 and the lower group modulation wave v x1、vx2 are not equal, namely omega 1≠ω2; the modulation wave v x1、vx2 is compared with two triangular carrier waves v c1、vc2 respectively to determine the output phase voltages u x1O、ux2O of the upper group and the lower group, and the specific comparison method is as follows:
① If the upper group modulation wave v x1 is greater than the carrier wave v c1, the upper group output phase voltage U x1O is U d/2; if the upper group modulation wave v x1 is smaller than the carrier wave v c2, the upper group output phase voltage U x1O is-U d/2; the upper set output phase voltage u x1O in the other case is 0;
② If the lower group modulation wave v x2 is greater than the carrier wave v c1, the lower group output phase voltage U x2O is U d/2; if the lower group modulation wave v x2 is smaller than the carrier wave v c2, the lower group output phase voltage U x2O is-U d/2; the lower set of output phase voltages u x2O in other cases is 0;
in the u x1O、ux2O inter-frequency situation, according to the constraint relation of v x1≥vx2, m 1 and m 2 should satisfy the constraint relation:
0＜m1+m2≤1
(6) Deriving logic operation of driving signals of each power switch of each phase bridge arm of the three-phase T-shaped three-level double-output inverter by combining the switch states and the modulation comparison results;
the driving signal of the 6 power switches S x1～Sx6 of each phase bridge arm is S x1～sx6; the value of the driving signal is 1, which indicates that the power switch is turned on; the value of the driving signal is 0, which indicates that the power switch is turned off;
The upper group of modulated waves v x1 are compared with the carrier wave v c1, and a driving signal S x1 of the power switch S x1 is generated according to the comparison result, wherein the specific expression is as follows:
The following group of modulated waves v x2 and carrier waves v c2 are compared, and a driving signal S x4 of a power switch S x4 is generated according to the comparison result, wherein the specific expression is as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 1, expressed as:
Comparing the upper group modulation wave v x1 with the carrier wave v c1 to generate a signal e 2, wherein the expression is as follows:
Comparing the upper group modulation wave v x1 with the carrier wave v c2 to generate a signal e 3, wherein the expression is as follows:
Signal e 4 is generated from signal e 2 and signal e 3 as follows:
wherein the symbol "AND" represents a logical AND operation;
Comparing the upper group modulation wave v x1 with the carrier wave v c2 to generate a signal e 5, wherein the expression is as follows:
The following set of modulated waves v x2 and carrier v c1 are compared to generate a signal e 6, expressed as:
The following set of modulated waves v x2 and carrier v c2 are compared to generate a signal e 7, expressed as:
Signal e 8 is generated from signal e 6 and signal e 7 as follows:
e8＝e6 AND e7
The driving signal S x2 of the power switch S x2 is generated by the signal e 1, the signal e 4 and the signal e 5, and expressed as:
sx2＝e1 ORe4 ORe5
wherein the symbol "OR" represents a logical OR operation;
the driving signal S x3 of the power switch S x3 is generated by the signal e 1, the signal e 8 and the signal e 5, and expressed as:
sx3＝e1 ORe8 ORe5
The driving signal S x5 of the power switch S x5 is generated by the driving signal S x4 and the signal e 5, and the expression is:
sx5＝NOT(sx4 AND e5)
Wherein the symbol "NOT" represents a logical "NOT" operation;
The driving signal S x6 of the power switch S x6 is generated by the driving signal S x1 and the signal e 1, and the expression is:
sx6＝NOT(sx1 AND e1)
(7) According to the steps (1) - (6), driving signals of 18 power switches of the three-phase T-type three-level double-output inverter can be obtained, carrier PWM modulation is completed, and the inverter outputs two groups of three-phase symmetrical alternating-current voltages.
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CN110247568A (en) * 2019-06-29 2019-09-17 东北电力大学 A kind of three level dual output inverter topology of three-phase diode clamper type
CN112511029A (en) * 2020-11-30 2021-03-16 东北电力大学 Three-phase three-level double-output inverter

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CN112564526A (en) * 2020-12-01 2021-03-26 东北电力大学 Three-phase T-shaped three-level double-output inverter

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CN110247568A (en) * 2019-06-29 2019-09-17 东北电力大学 A kind of three level dual output inverter topology of three-phase diode clamper type
CN112511029A (en) * 2020-11-30 2021-03-16 东北电力大学 Three-phase three-level double-output inverter

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