CN114389598A - Conversion device, interface circuit and chip - Google Patents
Conversion device, interface circuit and chip Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention discloses a conversion device, an interface circuit and a chip, wherein the conversion device comprises: at least two inverting modules and a current limiting module, wherein; the input end and the output end of each of the at least two inverting modules are electrically connected in sequence; the input end of a first inverting module of the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of a second anti-phase module of the at least two anti-phase modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply; the current-limiting module is connected in series between the positive end of the power supply and the first inverting module and used for reducing leakage current on the first inverting module when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a conversion device, an interface circuit, and a chip.
Background
In an integrated circuit, a Schmitt Trigger (Schmitt Trigger) is usually included between an input square-wave signal and an output square-wave signal to filter glitches in the input square-wave signal, however, the switch element in the Schmitt Trigger has a large leakage due to the mismatch between the positive potential of the power source in the integrated circuit and the high level of the input square-wave signal. In view of the above problems, it is common to add a current comparator or a Low-voltage drop out Regulator (LDO) to an integrated circuit, but the two methods require a large area, a large static power consumption, and a poor duty ratio of the output square wave signal.
Disclosure of Invention
The present invention provides a conversion device, an interface circuit and a chip, which at least partially solve the above technical problems.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a conversion apparatus, including: at least two inverting modules and a current limiting module, wherein;
the input end and the output end of each of the at least two inverting modules are electrically connected in sequence; the input end of a first inverting module of the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of a second anti-phase module of the at least two anti-phase modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply;
the current-limiting module is connected in series between the positive end of the power supply and the first inverting module and used for reducing leakage current on the first inverting module when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply.
Optionally, the first inverting module includes a first P-type switch element and a first N-type switch element, wherein a gate terminal of the first P-type switch element is electrically connected to a gate terminal of the first N-type switch element and is an input terminal of the first inverting module; the drain terminal of the first P-type switch component is electrically connected with the drain terminal of the first N-type switch component and is the output terminal of the first inverting module; the source terminal of the first P-type switch component is electrically connected with the current limiting module; the source terminal of the first N-type switch component is electrically connected with the negative terminal of the power supply.
Optionally, the second inverting module includes a second P-type switch element and a second N-type switch element, wherein a gate terminal of the second P-type switch element is electrically connected to a gate terminal of the second N-type switch element and is an input terminal of the second inverting module; the drain terminal of the second P-type switch component is electrically connected with the drain terminal of the second N-type switch component and is the output terminal of the second inverting module; the source terminal of the second P-type switch component is electrically connected with the positive end of the power supply; the source terminal of the second N-type switch component is electrically connected with the negative terminal of the power supply.
Optionally, the current limiting module includes at least one of: a resistance component, a third P-type switch component and a diode component.
Optionally, when the current limiting module includes a third P-type switch element, the source terminal of the third P-type switch element is electrically connected to the positive terminal of the power supply; the drain terminal of the third P-type switch component is electrically connected with the gate terminal and then electrically connected with the source terminal of the first P-type switch component.
Optionally, when the current-limiting module includes the diode assembly, the positive terminal of the diode assembly is electrically connected to the positive terminal of the power supply, and the negative terminal of the diode assembly is electrically connected to the source terminal of the first P-type switch assembly.
Optionally, the resistor assembly includes at least one resistor connected in series.
Optionally, the third P-type switch component includes at least one Metal Oxide Semiconductor (MOS) transistor having a gate terminal and a drain terminal electrically connected in series.
Optionally, the diode assembly comprises at least one diode in series.
Optionally, the first P-type switch component and the second P-type switch component are P-type MOS transistors; the first N-type switch component and the second N-type switch component are N-type MOS transistors.
Optionally, the conversion device further includes a feedback module, the feedback module is connected in parallel to two ends of the current limiting module, and an input end of the feedback module is electrically connected to an output end of the second inverting module, and is configured to improve a duty ratio of the second square wave signal.
Optionally, the feedback module is a fourth P-type switch module, wherein a gate terminal of the fourth P-type switch module is an input terminal of the feedback module, and the input terminal is electrically connected to the output terminal of the second inverting module; the fourth P-type switch component is connected with the current limiting module in parallel through a source end and a drain end, and the source end is connected to the high potential side of the current limiting module; the drain terminal is connected to the low potential side of the current limiting module.
Optionally, the fourth P-type switch component is a P-type MOS transistor.
In a second aspect, an embodiment of the present invention provides an interface circuit, including any one of the conversion devices described above.
Optionally, the interface circuit further includes: a Schmitt trigger device and an inverting device, wherein;
the Schmitt trigger device is electrically connected with the conversion device and is used for accessing a second square wave signal and filtering the second square wave signal;
the phase inversion device is electrically connected with the Schmitt trigger device and is used for accessing the filtered second square wave signal and inverting the filtered second square wave signal so as to output a third square wave signal with the same phase as the first square wave signal.
Optionally, the inverting apparatus includes: at least N inversion modules connected in series, wherein N is an integer not less than 1.
In a third aspect, the present invention further provides a chip including any one of the interface circuits described above.
The embodiment of the invention provides a conversion device, an interface circuit and a chip, wherein the conversion device comprises: at least two inverting modules and a current limiting module, wherein; the input end and the output end of each of the at least two inverting modules are electrically connected in sequence; the input end of a first inverting module of the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of a second anti-phase module of the at least two anti-phase modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply; the current-limiting module is connected in series between the positive end of the power supply and the first inverting module and used for reducing leakage current on the first inverting module when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply. In the embodiment of the invention, the first square-wave signal (the input square-wave signal) is converted into the second square-wave signal through the first inverting module and the second inverting module in the conversion device, and the high level of the second square-wave signal is the potential of the positive terminal of the chip power supply, that is, the input square-wave signal is converted into the square-wave signal with the potential of the positive terminal of the power supply as the high level and the low level of the input square-wave signal as the low level. Meanwhile, the conversion device adopts the first inverting module and the current-limiting module to be connected in series to realize the control of the leakage current on the branch, so that the leakage current in the circuit with the conversion device is smaller, the aim of reducing the leakage current of the circuit is fulfilled, in addition, the conversion device adopts fewer components and parts, has smaller size and does not need to occupy larger area of a chip during realization.
Drawings
Fig. 1 is a schematic structural diagram of a conversion apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a first inverter module and a second inverter module according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a conversion apparatus when a current-limiting module according to an embodiment of the present invention includes a resistor and the first inverting module and the second inverting module respectively adopt the structure shown in FIG. 2;
fig. 4 is a schematic structural diagram of a conversion device when a current-limiting module according to an embodiment of the present invention includes a P-type MOS transistor having a gate terminal electrically connected to a drain terminal and the first inverting module and the second inverting module respectively adopt the structure shown in fig. 2;
fig. 5 is a schematic structural diagram of a conversion device when a current limiting module according to an embodiment of the present invention includes a diode and the first inverting module and the second inverting module respectively adopt the structure shown in fig. 2;
fig. 6 is a schematic structural diagram of a conversion apparatus when a current limiting module according to an embodiment of the present invention includes at least one diode connected in series and the first inverting module and the second inverting module respectively adopt the structure shown in fig. 2;
fig. 7 is a schematic structural diagram of a switching device in which a current limiting module includes a resistor and a feedback module is a P-type MOS transistor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a switching device in which the current limiting module according to the embodiment of the present invention includes a P-type MOS transistor having a gate terminal electrically connected to a drain terminal and a feedback module as the P-type MOS transistor;
fig. 9 is a schematic structural diagram of a conversion device in which a current limiting module includes a diode and a feedback module is a P-type MOS transistor according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a switching device in which a current limiting module includes at least one diode connected in series and a feedback module is a P-type MOS transistor according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a schmitt trigger device according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram of an inverter according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of an interface circuit including a Schmitt trigger device and an inverter;
FIG. 14 is a schematic diagram of a current comparator;
fig. 15 is a schematic structural diagram of an LDO.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, as shown in fig. 1, an embodiment of the present invention provides a conversion apparatus 100, which includes: at least two inverting modules and a current limiting module 103, wherein;
the input end and the output end of each of the at least two inverting modules are electrically connected in sequence; the input end of a first inverting module 101 in the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of the second inverting module 102 of the at least two inverting modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply;
the current-limiting module is connected in series between the positive end of the power supply and the first inverting module and used for reducing leakage current on the first inverting module when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply.
It should be noted that the conversion apparatus provided by the embodiment of the present invention can be applied to any circuit that requires level conversion, for example, an interface circuit in which a Serial Data Line (SDA) signal does not match a positive power supply potential; for another example, level conversion between devices whose levels communicated via an I2C (Inter-Integrated Circuit) bus do not match, and the like.
Here, the sequential electrical connection of the input end and the output end of each of the at least two inverting modules may mean that the input end and the output end of each inverting module are sequentially electrically connected to form an inverting module chain, wherein a first inverting module of the at least two inverting modules is located at a chain head of the inverting module chain, that is, a first inverting module; the second inversion module of the at least two inversion modules is located at the chain tail of the inversion module chain, i.e. the last inversion module. It should be understood that the inverting module, as the name implies, essentially performs the function of an inverter, that is, inverting the input square wave signal. In the embodiment of the present invention, to realize that the second square wave signal is in phase with the first square wave signal, the number of the at least two inverting modules is even.
It is understood that the operation principle of the conversion apparatus 100 provided by the embodiment of the present invention is as follows: the input end of a first inverting module of the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of the second inverse module of the at least two inverse modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply, wherein the high level of the first square wave signal can be greater than, less than or equal to the potential of the positive end of the power supply. The high level of the second square wave signal is equal to the potential of the positive end of the power supply and is in phase with the first square wave signal. The low level of the second square wave signal may be the same as or different from the low level of the first square wave signal, and is not limited herein and may be adjusted according to actual situations. The in-phase may mean that when the first square wave signal is at a high level, the second square wave signal is also at a high level; when the first square wave signal is at a low level, the second square wave signal is also at a low level. In this way, the high level of the square wave signal input to the interface circuit comprising the schmitt trigger device does not differ from, and is matched to, the potential of the positive terminal of the power supply. At this time, for example, there is no leakage current on the schmitt trigger device in the interface circuit including the schmitt trigger device, thereby solving the problem of large leakage current caused by mismatch between the potential of the positive terminal of the power supply inside the chip and the input square wave signal in the conventional interface circuit. The conversion device provided by the embodiment of the invention also provides a current limiting module which is connected between the first inverting module and the positive end of the power supply in series, so that when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply, the leakage current on the first inverting module is reduced.
When the conversion device is used in an interface circuit, the first square wave signal may be an SDA signal, which may be 1.2 volts (V), or may be set to another voltage value according to an actual application scenario. The potential of the positive power supply terminal can be the high potential of a power supply voltage signal inside the chip, and can be 1.8V, 3.3V and the like. The low level of the first square wave signal may be 0V. The potential of the negative terminal of the power supply may be 0V.
The first inverting module, the second inverting module and the current limiting module in the conversion device have various implementation modes.
In some embodiments, the first inverting module comprises a first P-type switch element and a first N-type switch element, wherein a gate terminal of the first P-type switch element and a gate terminal of the first N-type switch element are electrically connected and are input terminals of the first inverting module; the drain terminal of the first P-type switch component is electrically connected with the drain terminal of the first N-type switch component and is the output terminal of the first inverting module; the source terminal of the first P-type switch component is electrically connected with the current limiting module; the source terminal of the first N-type switch component is electrically connected with the negative terminal of the power supply.
In some embodiments, the second inverting module comprises a second P-type switch element and a second N-type switch element, wherein a gate terminal of the second P-type switch element and a gate terminal of the second N-type switch element are electrically connected and are input terminals of the second inverting module; the drain terminal of the second P-type switch component is electrically connected with the drain terminal of the second N-type switch component and is the output terminal of the second inverting module; the source terminal of the second P-type switch component is electrically connected with the positive end of the power supply; the source terminal of the second N-type switch component is electrically connected with the negative terminal of the power supply.
It should be noted that the components included in the first inverting module and the second inverting module may be the same or different, that is, the first P-type switch component and the second P-type switch component may be the same or different; the first N-type switch assembly and the second N-type switch assembly may be the same or different. It should be understood that, here, whether the first P-type switching element or the second P-type switching element is used in the embodiment of the present invention, the switching characteristics thereof are all used, and therefore, the first P-type switching element and the second P-type switching element may be three-terminal devices having any switching characteristics, for example, the first P-type switching element and the second P-type switching element may be P-type MOS transistors; for another example, the first P-type switch element and the second P-type switch element may be transistors. Similarly, the first N-type switch element and the second N-type switch element are not described herein again.
In an optional embodiment, the first P-type switch component and the second P-type switch component are the same and are both P-type MOS transistors; the first N-type switch component and the second N-type switch component are the same and are both N-type MOS transistors.
As an example, when the at least two inverse modules include two inverse modules, as shown in fig. 2, the two inverse modules are a first inverse module 101 and a second inverse module 102, an output end of the first inverse module 101 is electrically connected to an input end of the second inverse module 102 to form an inverse module chain, and the first inverse module 101 is configured to access the first square wave signal, perform inverse processing on the first square wave signal, and transmit the first square wave signal to the second inverse module 102; the second inverting module 102 is configured to receive the inverted first square wave signal and output a corresponding second square wave signal; the gate terminal of the P-type MOS transistor and the gate terminal of the N-type MOS transistor included in the first inverting module 101 are electrically connected, and are the input terminal of the first inverting module, and are used for receiving the first square wave signal; a source terminal of a P-type MOS transistor included in the first inverting module 101 is electrically connected to the current limiting module, a source terminal of an N-type MOS transistor included in the first inverting module 101 is electrically connected to a negative terminal of a power supply, and a drain terminal of the P-type MOS transistor included in the first inverting module 101 is electrically connected to a drain terminal of the N-type MOS transistor, and is an output terminal of the first inverting module and electrically connected to an input terminal of the second inverting module; the gate terminal of the P-type MOS transistor included in the second inverse module 102 is electrically connected to the gate terminal of the N-type MOS transistor, and is an input terminal of the second inverse module, the source terminal of the P-type MOS transistor included in the second inverse module 102 is electrically connected to the positive terminal of the power supply, the source terminal of the N-type MOS transistor included in the second inverse module 102 is electrically connected to the negative terminal of the power supply, and the drain terminal of the P-type MOS transistor included in the second inverse module 102 is electrically connected to the drain terminal of the N-type MOS transistor, and is configured to output a second square wave signal.
It should be understood that the foregoing occurrences of "first" and "second" are merely for convenience in describing the two inverter modules in FIG. 2 and are not intended to limit the present invention.
As can be seen from fig. 2, when the first square wave signal is at a high level (e.g., 1.2V), the N-type MOS transistor included in the first inverting module 101 is turned on, the output of the first inverting module 101 is at a low level, at this time, the P-type MOS transistor included in the second inverting module 102 is turned on, the N-type MOS transistor included in the second inverting module 102 is turned off, the second square wave signal output by the output of the second inverting module 102 is at a high level, and the potential of the high level is the potential of the positive terminal of the power supply; in this case, the P-type MOS transistor in the first inverter module 101 should be logically turned off, but due to the voltage difference between the positive power supply terminal and the high level of the first square wave signal, the P-type MOS transistor in the first inverter module 101 may be weakly turned on to generate a leakage current, and in order to reduce the leakage current on the P-type MOS transistor in the first inverter module 101, a current limiting module is connected in series to a branch where the P-type MOS transistor in the first inverter module 101 is located to divide the voltage, so as to reduce the leakage current on the P-type MOS transistor in the first inverter module.
When the first square wave signal is at a low level (e.g., 0V), the N-type MOS transistor in the first inverter module 101 is turned off, the P-type MOS transistor in the first inverter module 101 is turned on, the output of the first inverter module 101 is at a high level, and the potential of the output of the first inverter module 101 is the potential of the positive terminal of the power supply, at this time, the P-type MOS transistor in the second inverter module 102 is turned off, the N-type MOS transistor in the second inverter module 102 is turned on, and the second square wave signal output by the output of the second inverter module 102 is at a low level (e.g., 0V), at this time, there is no leakage current in the converter.
In some embodiments, the current limiting module comprises at least one of: a resistance component, a third P-type switch component and a diode component.
It is understood that the current limiting module may include one of a resistor element, a third P-type switch element and a diode element; any combination of the three aforementioned forms is also possible.
Wherein the resistive component may comprise at least one resistor in series. Fig. 3 is a schematic structural diagram illustrating the switching device when the current limiting module includes a resistor element and the first inverting module and the second inverting module respectively adopt the structure shown in fig. 2.
In fig. 3, the structure of the conversion device is as follows: the first inverting module 101 is connected in series with the resistor R1 and then connected between the positive power supply terminal and the negative power supply terminal, and the input end of the first inverting module 101 is used for receiving the first square wave signal; the output end of the first inverting module 101 is electrically connected to the input end of the second inverting module 102, the first inverting module 101 and the resistor are connected in parallel between the positive power terminal and the negative power terminal, and the output end of the second inverting module 102 outputs a corresponding second square wave signal.
The operation principle of the conversion device is as described above, and is not described herein again. When the switching device in fig. 3 is used, the leakage current of the P-type MOS transistor in the first inverting module can be calculated by the following formula (1):
wherein,
representing a first inverse modeLeakage current on the P-type MOS transistors in group 101;
represents the electron mobility;
a gate oxide capacitance representing a unit area;
represents the ratio of the width to the length of the P-type MOS transistor in the first inversion module 101;
a high level indicating a first square wave signal;
represents the potential of the positive terminal of the power supply;
representing the voltage drop across the resistor;
which represents the absolute value of the threshold voltage of the P-type MOS transistor in the first inverter module 101.
As can be appreciated from the analysis of the above equation (1),
it is shown that the larger the voltage difference Vgs between the source terminal and the gate terminal of the P-type MOS transistor in the first inversion module 101, the larger the leakage current in the P-type MOS transistor in the first inversion module 101, and therefore, in practical application, the leakage current can be reduced by reducing Vgs of the P-type MOS transistor in the first inversion module.
When the frequency of the first square wave signal is very high or the required leakage current is relatively small, by using the conversion device provided by the embodiment of the invention, compared with the existing solution (by adding a current comparator, refer to fig. 14 or an LDO, refer to fig. 15), the structure used in the traditional method is more complex, more devices are needed to limit the current, and meanwhile, the current comparator and the LDO both need some static power consumption to enable the current comparator and the LDO to work all the time, and the static power consumption is relatively large.
In some embodiments, when the current limiting module includes a third P-type switch element, the source terminal of the third P-type switch element is electrically connected to the positive power supply terminal; the drain terminal of the third P-type switch component is electrically connected with the gate terminal and then electrically connected with the source terminal of the first P-type switch component.
It should be noted that the third P-type switch element may be a three-terminal device with any switching characteristics, for example, the third P-type switch element may be a P-type MOS transistor; for another example, the third P-type switch element may be a transistor.
In some embodiments, the third P-type switch element may include at least one P-type MOS transistor having a gate terminal and a drain terminal electrically connected in series. Fig. 4 is a schematic structural diagram of the conversion device when the current limiting module according to the embodiment of the invention includes a P-type MOS transistor having a gate terminal electrically connected to a drain terminal and the first inverting module and the second inverting module respectively adopt the structure shown in fig. 2.
In fig. 4, the structure of the conversion device is as follows: in approximate agreement with the structure shown in fig. 3, the operation principle of the switching device is basically the same as that described above, except that the resistor R1 in fig. 3 is replaced by the P-type MOS transistor M1 having its gate terminal and drain terminal electrically connected.
At this time, when the first square wave signal is at a high level, the leakage current of the P-type MOS transistor in the first inverting module can be calculated by the following formula (2):
wherein,
gate representing M1The voltage difference between the source terminal and the terminal, i.e. the voltage difference between the source terminal and the gate terminal of the P-type MOS transistor electrically connected between the drain terminal and the gate terminal.
The structure in fig. 4 is the same as that in fig. 4 except that the resistor R1 in fig. 3 is replaced by a P-type MOS transistor M1 having a gate terminal electrically connected to a drain terminal. Based on the fact that the P-type MOS transistor has a certain voltage drop, the area of the P-type MOS transistor electrically connected with the grid end and the drain end is smaller under the same leakage current requirement, and the chip area is saved.
In some embodiments, when the current limiting module includes the diode component, the positive terminal of the diode component is electrically connected to the positive terminal of the power supply, and the negative terminal of the diode component is electrically connected to the source terminal of the first P-type switch component.
Wherein the diode assembly may include at least one diode connected in series. An example is shown in fig. 5, which is a schematic structural diagram of a conversion apparatus when a current limiting module provided by an embodiment of the invention is a diode and a first inverting module and a second inverting module respectively adopt the structure in fig. 2.
In fig. 5, the structure of the conversion device is as follows: in fig. 5, the structure of the conversion device is as follows: in approximate agreement with the structure in fig. 3, only the resistor R1 in fig. 3 is replaced by the diode D1, and the operation principle of the conversion device is basically in agreement with the above structure, and will not be described again.
At this time, when the first square wave signal is at a high level, the leakage current of the P-type MOS transistor in the first inverting module can be calculated by the following formula (3):
wherein,
representing the voltage across the diode.
Another example is shown in fig. 6, which is a schematic structural diagram of a switching device when a current limiting module provided in an embodiment of the present invention includes at least one diode connected in series and the first inverting module and the second inverting module respectively adopt the structure in fig. 2.
In fig. 6, the structure of the conversion device is as follows: in approximate agreement with the structure in fig. 5, only a single diode in fig. 5 is replaced by a plurality of diodes connected in series, and in this structure, the operation principle of the conversion device is basically in agreement with the foregoing, and will not be described again.
At this time, when the first square wave signal is at a high level, the leakage current of the P-type MOS transistor in the first inverting module can be calculated by the following formula (4):
wherein,
representing the total voltage drop after N diodes are connected in series.
It should be noted that the number of the aforementioned series diodes is related to the voltage difference between the high level of the first square wave signal and the positive terminal of the power supply, and since the voltage difference of one diode is about 0.6V, we need to reduce Vgs of the P-type MOS transistor in the first inverting module to be smaller than VTHFor the input signal with high level of 1.2V and the power voltage of 1.8V, the voltage difference between the two is 1.8-1.2=0.6V, we can use one diode, when the input signal with high level of 1.2V and the power voltage of 2.5V, we need two diodes, when the power voltage is 3.3V, we need about three diodes to reduce the leakage current,
it is understood that the series resistance and the number of the P-type MOS transistors electrically connected between the drain terminal and the gate terminal of the series are also related to the high level of the first square wave signal and the voltage difference of the positive terminal of the power supply.
Based on the second square wave signal obtained by the conversion apparatus shown in fig. 3 to fig. 6, when the first square wave signal is inverted from a high level to a low level, a weak current is charged to the gate terminals of the N-type MOS transistor and the P-type MOS transistor in the second inversion module through the current limiting module and the P-type MOS transistor in the first inversion module due to the effect of the current limiting module, so that the rising edge of the square wave signal output by the output terminal of the first inversion module rises more slowly, and the duty ratio of the second square wave signal output by the output terminal of the second inversion module is poorer, therefore, in some embodiments, the conversion apparatus further includes a feedback module, the feedback module is connected in parallel to the two ends of the current limiting module, and the input terminal of the feedback module is electrically connected to the output terminal of the second inversion module, for improving the duty cycle of the second square wave signal.
Optionally, the feedback module is a fourth P-type switch module, wherein a gate terminal of the fourth P-type switch module is an input terminal of the feedback module, and the input terminal is electrically connected to the output terminal of the second inverting module; the fourth P-type switch component is connected with the current limiting module in parallel through a source end and a drain end, and the source end is connected to the high potential side of the current limiting module; and the drain end is connected to the low potential side of the current limiting module.
The fourth P-type switch element may be a three-terminal device with any switching characteristics, for example, the fourth P-type switch element may be a Metal Oxide Semiconductor (MOS) transistor; for another example, the fourth P-type switch element may be a transistor.
As an optional implementation manner, the fourth P-type switch component is a P-type MOS transistor, wherein the P-type MOS transistor is connected in parallel with the current limiting module through a source terminal and a drain terminal, and the source terminal of the P-type MOS transistor is connected to the high potential side of the current limiting module; the drain end of the P-type MOS transistor is connected to the low potential side of the current limiting module; the grid end of the P-type MOS transistor is the input end of the feedback module, and the input end is electrically connected with the output end of the second inverting module.
For example, in the structure of the first inverting module 101 and the second inverting module 102 as shown in fig. 2, the current limiting module is shown in fig. 3 to 6, and the feedback module is a P-type MOS transistor, and the specific connection thereof can be as shown in fig. 7 to 10.
It should be noted that, after the feedback module is introduced, when the first square wave signal is inverted from a high level to a low level, after the square wave signal output by the first inverting module rises to the turn-on voltage of the N-type MOS transistor of the second inverting module, the second square wave signal output by the output end of the second inverting module is at a low level, and the feedback module is turned on, at this time, the power supply positive terminal charges the gate terminals of the N-type MOS transistor and the P-type MOS transistor in the second inverting module through the feedback module, so that the rising edge of the square wave signal output by the first inverting module rises faster, and the duty ratio of the second square wave signal output by the output end of the second inverting module is improved.
Based on the foregoing conversion apparatus, in some embodiments, an embodiment of the present invention further provides an interface circuit, which includes the conversion apparatus according to any of the foregoing embodiments.
In some embodiments, the interface circuit further comprises: a Schmitt trigger device and an inverting device, wherein;
the Schmitt trigger device is electrically connected with the conversion device and is used for accessing the second square wave signal and filtering the second square wave signal;
the phase inversion device is electrically connected with the Schmitt trigger device and is used for accessing the filtered second square wave signal and inverting the filtered second square wave signal so as to output a third square wave signal with the same phase as the first square wave signal.
In some embodiments, the schmitt trigger device is configured to access the second square wave signal, and perform filtering processing on the second square wave signal to output a fourth wave signal delivered to the phase inverting device.
It can be understood that, as used herein, the filtering process on the second square wave signal may be to reduce glitches in the second square wave signal by using a hysteresis characteristic of a schmitt trigger device, so that an output fourth wave signal has a better duty ratio, where the fourth wave signal and the second square wave signal may be in opposite phases, and the fourth wave signal is a square wave signal that meets an electrical requirement of a chip and carries information to be transmitted.
In some embodiments, the schmitt trigger mechanism may include: a fifth P-type switch assembly, a sixth P-type switch assembly, a seventh P-type switch assembly, a third N-type switch assembly, a fourth N-type switch assembly, and a fifth N-type switch assembly, wherein;
the source terminal of the fifth P-type switch component is used for being connected to the positive end of the power supply, and the drain terminal of the fifth P-type switch component is electrically connected with the source terminal of the sixth P-type switch component;
the drain terminal of the sixth P-type switch component is electrically connected with the drain terminal of the third N-type switch component;
the grid terminal of the fifth P-type switch component and the grid terminal of the sixth P-type switch component are electrically connected with the output end of the second inverting module and used for accessing the second square wave signal;
a source terminal of the seventh P-type switch component is connected with a connecting line of a drain terminal of the fifth P-type switch component and a source terminal of the sixth P-type switch component; the drain end of the seventh P-type switch component is connected to the negative end of the power supply; the grid end of the seventh P-type switch component is connected with a connecting line of the drain end of the sixth P-type switch component transistor and the drain end of the third N-type switch component;
the source terminal of the third N-type switch component is electrically connected with the drain terminal of the fourth N-type switch component;
the source terminal of the fourth N-type switch component is connected with the negative terminal of the power supply;
the grid terminal of the third N-type switch assembly and the grid terminal of the fourth N-type switch assembly are electrically connected with the output end of the second inverting module and are used for accessing the second square wave signal;
a source terminal of the fifth N-type switch element is connected to a connection line between a source terminal of the third N-type switch element and a drain terminal of the fourth N-type switch element; the drain end of the fifth N-type switch assembly is connected to the positive power supply end; the grid end of the fifth N-type switch component is connected with a connecting line of the drain end of the third N-type switch component and the drain end of the sixth P-type switch component.
It should be noted that the fifth P-type switch element, the sixth P-type switch element, and the seventh P-type switch element may be three-terminal devices with any switching characteristics, such as P-type MOS transistors; as another example, a triode.
In an optional implementation manner, the fifth P-type switch element, the sixth P-type switch element, and the seventh P-type switch element are all P-type MOS transistors.
It should be noted that the third N-type switch element, the fourth N-type switch element, and the fifth N-type switch element may be three-terminal devices with any switching characteristics, such as N-type MOS transistors; as another example, a triode.
In an optional implementation manner, the third N-type switch element, the fourth N-type switch element, and the fifth N-type switch element are all N-type MOS transistors.
The schmitt trigger device described above can be shown in fig. 11, the schmitt trigger device can include three P-type MOS transistors, which correspond to the fifth P-type switch element, the sixth P-type switch element, and the seventh P-type switch element, respectively; the three N-type MOS transistors respectively correspond to the third N-type switch element, the fourth N-type switch element, and the fifth N-type switch element, wherein the electrical connection relationship between the three P-type MOS transistors is not described herein again for clarity of the foregoing description. The electrical connection relationship between the three N-type MOS transistors is not described herein for clarity.
In some embodiments, as shown in fig. 12, the inverting means comprises: at least N inversion modules connected in series, wherein N is an integer not less than 1.
The inverting unit may shape the fourth wave signal output from the schmitt trigger unit to shorten a time taken for potential inversion of the fourth wave signal. The fourth wave signal is in anti-phase with the third wave signal; the output end of each phase inverter of the at least N phase inverters connected in series is electrically connected with the input end of the next phase inverter in sequence. In other embodiments, the inverting means may also be formed by a combination of a phase inverter and a phase inverter. It should be understood that the smaller the number of inverters, the smaller the occupied space of the chip, and accordingly, the chip area can be reduced.
Illustratively, as shown in fig. 13, a schematic diagram of an interface circuit including a schmitt trigger device and an inverter is shown. As can be seen from fig. 13, if the interface circuit comprises only schmitt trigger means and inverting means, then, the first square wave signal is directly accessed from the input end of the Schmitt trigger device, and because the high level of the first square wave signal is less than the potential of the positive end of the power supply, on a branch including the fourth P-type switch component, the fifth P-type switch component, the second N-type switch component and the third N-type switch component between the positive power supply terminal and the negative power supply terminal, when the first square wave signal is at a high level, the four transistors are all turned on, so that a large leakage current exists in the branch including the four transistors, and at this time, the conversion device provided by the embodiment of the invention is adopted before the interface circuit only comprising the Schmitt trigger device and the inverting device so as to reduce leakage circuits and save a large chip area.
The interface circuit provided by the embodiment of the invention has the advantages that compared with the traditional design mode that the current comparator is added before the interface circuit (the current comparator is shown in fig. 14) or the LDO is added before the interface circuit (shown in fig. 15), the traditional mode that the comparator and the LDO are used, it requires static power consumption to operate, it is also considered to be leakage current, not in line with our expectations, and both require dc bias, when the dc bias power consumption needs to be very low, more components and resistor area are needed to reduce the current, it is usually difficult to achieve below 10uA and guarantee the requirement of very high frequency and duty ratio, the mode is realized by switching on and off the P-type MOS transistor or the N-type MOS transistor of the first inverting module, the static power consumption is low, the structure is simple, and the current is prevented from being limited by a resistor, so that the area is small.
It should be noted that, in fig. 15, V1 is a voltage lower than the positive terminal of the power supply obtained by a simple voltage divider circuit, and in fig. 15, equal to Vgs of two N-type MOS transistors, the voltage of V1 is as close as possible to the high level of the first square wave signal during use, so that the inverter between V1 and the negative terminal of the power supply does not leak electricity; the VO1 and the second square-wave signal are both level shift input signals, and the VO3 is a voltage for converting the voltage of the second square-wave signal into a voltage from the positive voltage terminal to the negative voltage terminal of the power supply through one level shift. Thus, both R3 and levelshift in the LDO occupy a large area, and the branch R3 and the adjacent branch on the right always have static current, which is considered as leakage current.
On the other hand, an embodiment of the present invention further provides a chip, which includes the interface circuit in any of the above embodiments.
It can be understood that, in the chip provided by the embodiment of the present invention, an input signal (a first square wave signal) in an interface circuit converts the first square wave signal into a second square wave signal through a conversion device included in the interface circuit, where a high level of the first square wave signal is lower than a level of a positive terminal of the power supply; the second square wave signal is a square wave signal having a high level same as the level of the positive terminal of the power supply and a low level same as the first square wave signal and is in phase with the first square wave signal; the conversion device with the structures formed by the first inverting module, the second inverting module and the current limiting module not only saves chip description, but also can reduce static power consumption; in addition, after the feedback module is added in the conversion device, the second square wave signal output by the conversion device has a good duty ratio, so that the third square wave signal output by the whole interface circuit has a good duty ratio. It should be noted that a chip generally includes a plurality of pins, and each pin may adopt one interface circuit in the above embodiments, so as to reduce the static power consumption of the interface circuit and improve the duty ratio of the square wave input into the chip.
In the above embodiments, the descriptions of the embodiments have emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The interface circuit and the chip provided by the embodiment of the present invention are introduced in detail, and a specific example is applied in the description to explain the principle and the implementation of the present invention, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (17)
1. A conversion apparatus, comprising: at least two inverting modules and a current limiting module, wherein;
the input end and the output end of each of the at least two inverting modules are electrically connected in sequence; the input end of a first inverting module of the at least two inverting modules is used for accessing a first square wave signal input from the outside; the output end of a second anti-phase module of the at least two anti-phase modules is used for outputting a second square wave signal which is in phase with the first square wave signal and has a high level equal to the potential of the positive end of the power supply;
the current-limiting module is connected in series between the positive end of the power supply and the first inverting module and used for reducing leakage current on the first inverting module when the high level of the first square wave signal is not matched with the potential of the positive end of the power supply.
2. The switching device of claim 1, wherein the first inverting module comprises a first P-type switch element and a first N-type switch element, wherein the gate terminal of the first P-type switch element and the gate terminal of the first N-type switch element are electrically connected and are input terminals of the first inverting module; the drain terminal of the first P-type switch component is electrically connected with the drain terminal of the first N-type switch component and is the output terminal of the first inverting module; the source terminal of the first P-type switch component is electrically connected with the current limiting module; the source terminal of the first N-type switch component is electrically connected with the negative terminal of the power supply.
3. The switching device of claim 2, wherein the second inverting module comprises a second P-type switch element and a second N-type switch element, wherein a gate terminal of the second P-type switch element and a gate terminal of the second N-type switch element are electrically connected and are input terminals of the second inverting module; the drain terminal of the second P-type switch component is electrically connected with the drain terminal of the second N-type switch component and is the output terminal of the second inverting module; the source terminal of the second P-type switch component is electrically connected with the positive end of the power supply; the source terminal of the second N-type switch component is electrically connected with the negative terminal of the power supply.
4. The switching device of claim 2, wherein the current limiting module comprises at least one of: a resistance component, a third P-type switch component and a diode component.
5. The switching device of claim 4, wherein when the current limiting module comprises a third P-type switch element, the source terminal of the third P-type switch element is electrically connected to the positive power supply terminal; the drain terminal of the third P-type switch component is electrically connected with the gate terminal and then electrically connected with the source terminal of the first P-type switch component.
6. The switching device of claim 4, wherein when the current limiting module comprises the diode assembly, the positive terminal of the diode assembly is electrically connected to the positive terminal of the power supply, and the negative terminal of the diode assembly is electrically connected to the source terminal of the first P-type switch assembly.
7. The switching device of claim 4, wherein the resistive component comprises at least one resistor in series.
8. The switching device of claim 4, wherein the third P-type switching element comprises at least one P-type Metal Oxide Semiconductor (MOS) transistor having a gate terminal and a drain terminal electrically connected in series.
9. The conversion apparatus of claim 4, wherein the diode assembly comprises at least one diode in series.
10. The switching device of claim 3, wherein the first P-type switching element and the second P-type switching element are P-type MOS transistors; the first N-type switch component and the second N-type switch component are N-type MOS transistors.
11. The switching device of claim 1, further comprising a feedback module connected in parallel across the current limiting module, wherein an input of the feedback module is electrically connected to an output of the second inverting module for improving a duty cycle of the second square wave signal.
12. The switching device of claim 11, wherein the feedback module is a fourth P-type switch element, wherein a gate terminal of the fourth P-type switch element is an input terminal of the feedback module, and the input terminal is electrically connected to the output terminal of the second inverting module; the fourth P-type switch component is connected with the current limiting module in parallel through a source end and a drain end, and the source end is connected to the high potential side of the current limiting module; the drain terminal is connected to the low potential side of the current limiting module.
13. The switching device of claim 12, wherein the fourth P-type switching element is a P-type MOS transistor.
14. An interface circuit, comprising: a switching device according to any one of the preceding claims 1 to 13.
15. The interface circuit of claim 14, wherein the interface circuit further comprises: a Schmitt trigger device and an inverting device, wherein;
the Schmitt trigger device is electrically connected with the conversion device and is used for accessing a second square wave signal and filtering the second square wave signal;
the phase inversion device is electrically connected with the Schmitt trigger device and is used for accessing the filtered second square wave signal and inverting the filtered second square wave signal so as to output a third square wave signal with the same phase as the first square wave signal.
16. The interface circuit of claim 15, wherein the inverting means comprises: at least N inversion modules connected in series, wherein N is an integer not less than 1.
17. A chip comprising the interface circuit of any of claims 14 to 16.
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Application publication date: 20220422 |