CN114388535A - Backside illuminated image sensor and method for manufacturing the same - Google Patents
Backside illuminated image sensor and method for manufacturing the same Download PDFInfo
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- CN114388535A CN114388535A CN202011118732.2A CN202011118732A CN114388535A CN 114388535 A CN114388535 A CN 114388535A CN 202011118732 A CN202011118732 A CN 202011118732A CN 114388535 A CN114388535 A CN 114388535A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14645—Colour imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The embodiment of the invention provides a back-illuminated image sensor and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate comprising a photosensitive unit; forming a deep trench on the back surface of the semiconductor substrate; forming a doped epitaxial layer on the surface of the deep groove by epitaxial growth; wherein a lateral PN junction is formed on a sidewall of the deep trench. And continuously growing high-K dielectric material and filling material on the deep groove epitaxial layer to complete the isolation between pixels, thereby reducing the optical and electrical crosstalk between pixels.
Description
Technical Field
The invention relates to the field of manufacturing of semiconductor devices, in particular to a back-illuminated image sensor and a preparation method thereof.
Background
Backside deep trenches are used to isolate individual pixels in a backside illuminated image sensor to reduce cross talk (crosstalk) due to incoming light. In back-illuminated high-pixel products, the n-type injection depth of a light sensing region in a pixel is increased continuously in order to ensure a certain full-well capacity due to the reduction of the size of the pixel region. The depth of the p-type isolation layer used to isolate the photosensitive region is also increased. Due to the limitation of the thickness of the photoresist used to block the p-type doping, one ion implantation on the front side of the silicon substrate cannot reach the required depth completely. Therefore, in the back-end process, deep trench etching is performed on the back surface of the silicon substrate, and a second ion implantation and annealing are performed in the deep trench to achieve the pixel isolation effect. However, the second ion implantation may cause some damage to the device, increasing the chance of dark current generation. Meanwhile, in the subsequent high-temperature annealing, risks such as functional damage and metal diffusion can be caused to the circuit at the front section.
Aiming at the back deep trench isolation process of the existing back-illuminated image sensor, one scheme is to directly isolate deep trenches without carrying out secondary ion implantation and diffusion, and although the function loss of a device caused by high temperature is avoided, the crosstalk of light and dark current between pixels cannot be sufficiently isolated. Another solution is to perform a second ion implantation p-type doping of the deep trench region before etching and filling the back deep trench isolation, wherein the depth of the deep trench is about 2 to 3 microns. Since there are lattice damage regions and malformative clusters after p-type doping is completed and some of the ions are not in the substitutional sites during implantation, thermal annealing is typically required to repair the lattice defects and to allow most of the implanted ions to move to the substitutional sites. Due to the high temperature of the thermal annealing process, the function loss of the previously made circuit, including the devices in the middle and the rear sections, is caused. Both of the above solutions have disadvantages, one of which may have optical crosstalk and dark current, and the other of which may damage the device under high temperature sintering.
Disclosure of Invention
The invention provides a back-illuminated image sensor and a preparation method thereof, aiming at the problems in the prior art.
An aspect of the present invention provides a method of manufacturing a back-illuminated image sensor. The method comprises the following steps: providing a semiconductor substrate comprising a photosensitive unit; forming a deep trench on the back surface of the semiconductor substrate; forming a doped epitaxial layer on the surface of the deep groove by epitaxial growth; wherein a lateral PN junction is formed on a sidewall of the deep trench.
Optionally, the temperature of the epitaxial growth does not exceed 950 ℃.
Optionally, the method further includes: forming a transistor on the front surface of the semiconductor substrate; cobalt silicide is formed on the surface of the gate, the drain or the source of the transistor to improve the thermal stability during the epitaxial growth process.
Optionally, the transistor formed on the front surface of the semiconductor substrate includes: forming a transistor including an LDD region and a Halo region through a Lightly Doped Drain (LDD) and lateral ion (pocket implant) implantation process to reduce a short channel effect and prevent a source and a drain of the transistor from being perforated; wherein the doping element comprises boron, indium or arsenic.
Optionally, the method further includes: forming a plurality of metal layers on the front surface of the semiconductor substrate; connecting a first metal layer in the multiple metal layers with cobalt silicide on the surface of a grid electrode, a drain electrode or a source electrode of the transistor through tungsten; wherein, a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer and a first dielectric layer are formed on the surface of the tungsten.
Optionally, each of the plurality of metal layers includes: a copper line, a diffusion barrier layer and a second dielectric layer; the diffusion barrier layer is formed on the side wall and the bottom of the copper wire; wherein the diffusion barrier layer comprises a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer.
Optionally, a gap with a certain width exists between the diffusion barrier layer and the second dielectric layer to relieve stress generated by thermal expansion of the copper wire.
Optionally, one or more layers of isolation layers of SiCN, SiCO, or SiN are formed on the top of the copper wire.
Optionally, the second dielectric layer is made of SiH4 or TEOS by PECVD or SACVD.
Optionally, the forming a doped epitaxial layer on the deep trench includes: and forming the doped epitaxial layer on the side wall and the bottom of the deep groove and the back surface of the semiconductor substrate.
Optionally, the thickness of the doped epitaxial layer is 0.05-0.1 micrometer.
Optionally, the front surface of the semiconductor substrate includes: doping the isolation region; the photosensitive unit is partially isolated by the doped isolation region; the forming the deep trench includes: aligning the doped isolation region, and forming the deep trench by etching; wherein the deep trench extends from the backside to a surface or an interior of the doped isolation region.
Optionally, after the doped epitaxial layer is formed on the deep trench, filling at least one dielectric layer in the deep trench to form a deep trench isolation structure; the at least one dielectric layer comprises HfO2、Al2O3、SiO2、TaO2At least one of; and continuously filling at least one of W or Al in the at least one dielectric layer.
Optionally, forming a color filter on the deep trench isolation structure; and forming a micro lens on the color filter.
Optionally, the multilayer metal layer is bonded with a carrier wafer through a bonding oxide layer; and thinning the back surface of the semiconductor substrate.
Another aspect of the present invention provides a back-illuminated image sensor. The back-illuminated image sensor includes: a semiconductor substrate having a front surface and a back surface; the semiconductor substrate comprises a photosensitive unit and a doped isolation region; the doped isolation region is formed inside the semiconductor substrate and extends from the front surface to the inside of the semiconductor; the deep trench isolation structure is formed on the back surface of the semiconductor substrate and extends to the inside of the semiconductor substrate from the back surface; the deep trench isolation structure includes: a deep trench extending from the backside to the surface or the interior of the doped isolation region; the epitaxial doping layer is formed on the surface of the deep groove; and forming a lateral PN junction on the side wall of the deep groove.
Optionally, the backside illuminated sensor further comprises: the transistor is formed on the front surface of the semiconductor substrate; a plurality of metal layers formed over the front side of the semiconductor substrate; wherein, cobalt silicide is formed on the surface of the grid electrode, the drain electrode or the source electrode of the transistor so as to improve the thermal stability in the epitaxial growth process.
Optionally, the transistor further comprises a Lightly Doped Drain (LDD) region and a Halo region formed by LDD and lateral ion implantation processes to reduce short channel effects and prevent source and drain punchthrough of the transistor; wherein the doping element comprises boron, indium or arsenic.
Optionally, a first metal layer in the multiple metal layers is connected with cobalt silicide on the surface of a gate, a drain or a source of the transistor through tungsten; wherein, a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer and a first dielectric layer are formed on the surface of the tungsten.
Optionally, each of the plurality of metal layers includes: a copper line, a diffusion barrier layer and a second dielectric layer; the diffusion barrier layer is formed on the side wall and the bottom of the copper wire; wherein the diffusion barrier layer comprises a TaN/Ti/TiN composite layer, a Ti/TiN layer or a Ta/TaN layer.
Optionally, a gap with a certain width exists between the diffusion barrier layer and the second dielectric layer to relieve stress generated by thermal expansion of the copper wire.
Optionally, one or more layers of isolation layers of SiCN, SiCO, or SiN are formed on the top of the copper wire.
Optionally, after the doped epitaxial layer is formed on the deep trench, filling at least one dielectric layer in the deep trench to form a deep trench isolation structure; the at least one dielectric layer comprises HfO2、Al2O3、SiO2、TaO2At least one of; and continuously filling at least one of W or Al in the at least one dielectric layer.
Optionally, the backside illuminated sensor further comprises: the color filter is formed on the deep groove isolation structure; and the micro lens is formed on the color filter. Optionally, the epitaxial doped layer is formed by epitaxial growth, and the temperature does not exceed 950 ℃.
Optionally, the thickness of the epitaxial layer is 0.05-0.1 micrometer.
Compared with the prior art, the invention has the following beneficial effects:
according to the embodiment of the invention, an epitaxial technology is adopted in the back deep trench isolation process of the back side illumination type image sensor to grow a layer of high-doped strong-inversion isolation region in the deep trench to form the lateral PN junction.
Since the epitaxy for deep trench isolation is relatively low temperature compared to common epitaxy technology, the temperature is still high compared to the conventional process of middle and back-end devices (e.g., interlayer dielectric layer, metal layer, etc.). Therefore, the embodiments of the present invention are improved in the middle-end and later-end processes, for example, cobalt silicide (Co-silicide) is used as the connection conductor in the gate, drain or source interconnection process. Since cobalt silicide has high thermal stability, it increases heat resistance. The isolation between the pixel units can be effectively carried out by epitaxially growing a strong inversion isolation region in the back deep trench at low temperature in combination with cobalt silicide, and meanwhile, the damage of high temperature to the middle-section circuit and the rear-section circuit can be reduced.
The dielectric layer of the embodiment of the invention adopts silicon oxide, and replaces the traditional dielectric layer made of low dielectric constant material. Since the mechanical strength of silicon oxide is greater than that of a low dielectric constant material, mechanical damage (e.g., fracture) to the dielectric layer due to deformation can be better resisted under the condition that metal (e.g., copper) expands with heat and contracts with cold.
Drawings
Fig. 1 is a schematic view of an interface structure of an image sensor according to an embodiment of the present invention;
fig. 2A is a schematic diagram of an exemplary structure of a transistor according to an embodiment of the invention;
FIG. 2B is a schematic diagram of an exemplary structure of another transistor according to an embodiment of the invention;
FIG. 3 is an exemplary schematic diagram of a connector according to an embodiment of the present invention;
fig. 4A is an exemplary structural schematic diagram of a metal interconnect structure according to an embodiment of the present invention;
FIG. 4B is an exemplary schematic diagram of another metal interconnect structure according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method of fabricating a back-illuminated image sensor according to an embodiment of the present invention;
fig. 6 to 12 are sectional views of structures in the process of manufacturing a back-illuminated image sensor according to an embodiment of the present invention;
fig. 13 is an exemplary flowchart of another method for manufacturing a back-illuminated image sensor according to an embodiment of the present invention.
Detailed Description
The invention aims to grow a layer of high-doped strong-inversion isolation region in a deep trench by adopting an epitaxial technology in a process of isolating the deep trench on the back of a high-pixel back-illuminated image sensor. Meanwhile, in the gate, drain, source, etc. connection process, cobalt silicide (Co-silicide) is used as a connection conductor. Co-salicide has high thermal stability and can increase the heat-bearing capacity. The back deep groove is internally and externally epitaxially grown with a strong inversion isolation region combined with Co-salicide, so that the pixel regions can be effectively isolated, and meanwhile, the damage of high temperature to the middle-section circuit and the rear-section circuit can be reduced.
Fig. 1 is a schematic diagram of an exemplary back-illuminated image sensor according to an embodiment of the present invention.
As shown in fig. 1, the back-illuminated image sensor 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has a Front Side (FS) and a Back Side (BS). The semiconductor substrate 10 includes a plurality of photosensitive cells 11 and doped isolation regions 12. The doped isolation region 12 is formed on the front surface of the semiconductor substrate 10 and extends from the front surface into the semiconductor substrate 10. The semiconductor substrate 10 may be p-type or n-type; the light sensing unit 11 may be a photodiode. The doped isolation region 12 may be p-type or n-type.
The back-illuminated image sensor 100 includes a Deep Trench Isolation (DTI) structure 13. The deep trench isolation structure 13 is formed on the backside of the semiconductor substrate 10 and extends from the backside to the inside of the semiconductor substrate. The deep trench isolation structure 13 may be formed partially or entirely in the doped isolation region 12. The deep trench isolation structure 13 comprises a deep trench extending from the backside to the surface or the interior of the doped isolation region 12. The deep trench isolation structure 13 includes an epitaxial doped layer 131 formed at the deep trench surface. On the sidewalls and bottom of the deep trench and the back surface of the semiconductor substrate 10, a doped epitaxial layer 131 is formed. The epitaxial doped layer 131 is inverted with respect to the light sensing unit 11. For example, the light sensing unit 11 is n-type, and the epitaxial doped layer 131 is p-type; the photosite 11 is p-type and the epitaxial doped layer 131 is n-type. Thus, the deep trench sidewalls may form a lateral PN junction. The epitaxial doped layer 131 may be other materials such as silicon or germanium. For example, Boron (Boron, B) or other p-type doping element may be used for doping, and the doping concentration may be controlled between 1e15 and 1e 17.
In some embodiments, the thickness of the epitaxial doped layer 131 may be 0.05 to 0.1 microns. In some embodiments, the doping concentration profile of the epitaxial doping layer 131 may be a uniform profile or a non-uniform profile. In some embodiments, the temperature of the epitaxial growth does not exceed 950 ℃; in some embodiments, the temperature of the epitaxial growth may be appropriately adjusted according to the heat resistance of different devices (e.g., a connection conductor, a metal layer, etc. on the surface of a source, a drain, or a gate of a transistor), for example, the temperature of the epitaxial growth does not exceed 800 ℃.
The deep trench isolation structure 13 further includes at least one dielectric layer 132 filled in the deep trench, and a filling material 133 in the at least one dielectric layer. By way of illustration only, only one dielectric layer 132 and fill material 133 are shown in fig. 1. The dielectric layer 132 may comprise hafnium oxide (HfO)2) Alumina (Al)2O3) Silicon oxide (SiO)2) Tantalum oxide (TaO)2) At least one of (1). The filling material 133 may include at least one of Tungsten (Tungsten, W) or aluminum (Al).
A plurality of transistors 14 are formed on the front surface of the semiconductor substrate 10. Transistor 14 includes a source 141, a drain 142, and a gate 143. Cobalt silicide 15 (Co-silicide) is formed on the surfaces of the source electrode 141, the drain electrode 142, and the gate electrode 143, and may be used as a connection conductor to another connection member. In the embodiment of the invention, cobalt silicide (Co-silicide) is used for replacing nickel silicide (Ni-silicide) in the traditional process, and although the cobalt silicide (Co-silicide) has higher resistivity than the nickel silicide (Ni-silicide), the cobalt silicide has better thermal stability at high temperature (more than 800 ℃). Ni-Salicide undergoes a change in resistivity upon annealing at 600 ℃ for a long period of time.
Fig. 2A and 2B respectively show an exemplary structural diagram of a transistor. In fig. 2A, the transistor 14 is an N-type transistor. The transistor 14 in fig. 2B is a P-type transistor. Shallow Trench Isolation (STI) is used to isolate different transistors. Transistor 14 also includes isolation 144 and gate oxide 145. In order to reduce the short channel effect and prevent the source and drain from punch-through, in the embodiment of the present invention, an LDD region is formed in the transistor 14 by Lightly Doped Drain (LDD); halo regions are formed by a pocket implant process. In this process, the NLDD doping element may include Arsenic (As), Phosphorus (P), etc., and the N Pocket doping element may include Boron (Boron, B), Indium (Indium, In), etc. PLDD doping elements may include Boron (Boron, B), Indium (Indium, In), etc., and P Pocket doping elements may include Arsenic (Arsenic, As), phosphorous (P), etc. The traditional process adopts phosphorus element as doping element in NLDD (N-type transistor lightly doped drain) or P Pocket. Because phosphorus can be seriously diffused in a subsequent high-temperature process, and arsenic cannot be diffused, the embodiment of the invention preferentially adopts arsenic for doping.
The back-illuminated image sensor 100 includes an inter-layer dielectric layer 20 (ILD) and a plurality of metal layers. By way of example only, the multiple metal layers show only the first metal layer 31 and the second metal layer 32. In some embodiments, the plurality of metal layers may further include a third metal layer, a fourth metal layer, and the like, which are not limited herein. The interlayer dielectric layer 20 includes a connection member 21 and a first dielectric layer 22. The first metal layer 31 of the multi-metal layers is connected to cobalt silicide (Co-silicide) on the surface of the source 141, the drain 142, or the gate 143 of the transistor 14 by tungsten (W). The structure of the connector 21 is shown in fig. 3, and the connector 21 includes tungsten (W) 221, a composite layer 222, and a first dielectric layer 22 (ILD). The first dielectric layer 22 may be silicon oxide or other low dielectric constant material. Alternatively, the composite layer 222 may be a TaN/Ti/TiN composite layer, i.e., a TaN layer, a Ti layer, and a TiN layer are sequentially formed on the surface of tungsten (W). Alternatively, the composite layer 222 may be a Ti/TiN composite layer, in which a Ti layer and a TiN layer are sequentially formed on the surface of tungsten (W). Alternatively, the composite layer 222 may be a Ta/TaN composite layer, i.e., a Ta layer and a TaN layer are sequentially formed on the surface of tungsten (W). Wherein, the TaN/Ti/TiN composite layer has better barrier effect on the diffusion of metal tungsten to the first dielectric layer 22 than the Ti/TiN composite layer or the Ta/TaN composite layer at high temperature. Wherein, the Ti layer can be prepared by Metal Organic Chemical Vapor Deposition (MOCVD) or Ionized Metal Plasma (IMP); the TiN layer can be prepared by Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD); the Ta layer and the TaN layer may be formed by PVD or Atomic Layer Deposition (ALD).
Each metal layer includes a metal interconnection 33, a connection 35, and a second dielectric layer 34 (IMD). The connecting member 35 may connect adjacent metal layers, and the connecting member 35 may be made of other metal materials such as tungsten and copper.
The second dielectric layer 34 is a silicon oxide dielectric layer, and is prepared by using SiH4 or teos (tetraethyl orthosilicate) through a Plasma Enhanced Chemical Vapor Deposition (PECVD) or a low-atmospheric pressure Vapor Deposition (SACVD). Although the dielectric constant of silicon oxide (k = 3.9) is higher than that of conventional low-k materials (k = 2.4-3.3) and causes a certain RC Delay (RC Delay), the thermal stability of the silicon oxide dielectric layer is better than that of conventional low-k layers, such as SiCOH or fteos (f doped TEOS oxide) fluorine-doped silicon oxide. The latter two materials are thermally decomposed at high temperature, and the dielectric constant is increased. Meanwhile, the silicon oxide has stronger mechanical property than SiCOH, and plays a good role in blocking the thermal expansion of the copper wire in a high-temperature process.
Fig. 4A is a schematic diagram of an exemplary metal interconnect structure 33. As shown in fig. 4A, the metal interconnection structure 33 includes a copper line 331, a diffusion barrier layer 332, an isolation layer 333, and a second dielectric layer 34. Diffusion barrier 332 is formed on the sidewalls and bottom of copper line 331. An isolation layer 333 is formed on top of the copper line 331. Alternatively, the diffusion barrier layer 332 may comprise a TaN/Ti/TiN composite layer, i.e., a TaN layer, a Ti layer and a TiN layer are sequentially formed on the copper surface. Alternatively, the diffusion barrier layer 332 may be a Ti/TiN composite layer, i.e., a Ti layer and a TiN layer are sequentially formed on the copper surface. Alternatively, the diffusion barrier layer 332 may be a Ta/TaN composite layer, i.e., a Ta layer and a TaN layer are sequentially formed on the copper surface. The spacer layer 333 may be one or more layers of SiCN, SiCO, or SiN. Wherein, the Ti layer can be prepared by MOCVD or IMP method; the TiN layer can be prepared by adopting a PVD or ALD method; the Ta layer and the TaN layer can be prepared by adopting a PVD or ALD method. The isolation layer 333 may be formed by PECVD.
Fig. 4B is a schematic diagram of another exemplary metal interconnect structure 33. A gap of a certain width exists between the diffusion barrier layer 332 and the second dielectric layer 34. The gap is advantageous to reduce damage caused by mechanical pressing of the copper wire 331 against the second dielectric layer 34 on the sidewall during thermal expansion and contraction in the subsequent process.
The backside illuminated image sensor 100 includes a color filter 60 formed on the deep trench isolation structure 13. The back-illuminated image sensor 100 includes a microlens 70 formed on a color filter 60. The backside illuminated image sensor 100 includes a carrier wafer 50 connected to a metal layer 32 by a bonding oxide layer 40.
Fig. 5 is an exemplary flowchart of a method for manufacturing a back-illuminated image sensor according to an embodiment of the present invention. Fig. 6 to 12 are sectional views of structures in the process of manufacturing a back-illuminated image sensor according to an embodiment of the present invention.
The method 500 for manufacturing a backside illuminated image sensor comprises the steps of:
As shown in fig. 6, the semiconductor substrate 10 has a Front Side (FS) and a Back Side (BS). The semiconductor substrate 10 includes a plurality of photosensitive cells 11 and doped isolation regions 12. The doped isolation region 12 is formed inside the semiconductor substrate 10 and extends from the front surface to inside the semiconductor substrate 10. The semiconductor substrate 10 may be p-type or n-type; the light sensing unit 11 may be a photodiode. The doped isolation region 12 may be p-type or n-type.
First, as shown in fig. 7, a plurality of transistors 14 need to be formed on the front surface of the semiconductor substrate 10. Transistor 14 includes a source 141, a drain 142, and a gate 143. Cobalt silicide 15 (Co-silicide) is formed on the surfaces of the source electrode 141, the drain electrode 142, and the gate electrode 143, and may be used as a connection conductor to another connection member. In the embodiment of the invention, cobalt silicide (Co-silicide) is used for replacing nickel silicide (Ni-silicide) in the traditional process, and although the cobalt silicide (Co-silicide) has higher resistivity than the nickel silicide (Ni-silicide), the cobalt silicide has better thermal stability at high temperature (more than 800 ℃). The detailed structure of the transistor 14 is described with reference to fig. 2A and 2B and related descriptions.
Fig. 2A shows an N-type transistor. Fig. 2B shows a P-type transistor. Shallow Trench Isolation (STI) is used to isolate different transistors. Transistor 14 also includes isolation 144 and gate oxide 145. To reduce short channel effects and prevent source and drain punch-through, the method uses Lightly Doped Drain (LDD) and lateral ion (pocket implant) implantation processes to form LDD and Halo regions in the transistor 14. In this process, the doping element may include Boron (Boron, B), Indium (Indium, In), Arsenic (As), Phosphorus (P), and the like. In the traditional process, phosphorus is adopted as a doping element in NLDD (N-type transistor lightly doped drain) and PLDD (P-type transistor lightly doped drain). Because phosphorus can be seriously diffused in a subsequent high-temperature process which may be met, and arsenic cannot be diffused, the method preferentially adopts arsenic for doping.
Next, an inter-layer dielectric (ILD) layer 20 and a plurality of metal layers are formed on the front surface of the semiconductor substrate 10. By way of example only, the multiple metal layers show only the first metal layer 31 and the second metal layer 32. In some embodiments, the plurality of metal layers may further include a third metal layer, a fourth metal layer, and the like, which are not limited herein. The interlayer dielectric layer 20 includes a connection member 21 and a first dielectric layer 22. The first metal layer 31 of the multi-metal layers is connected to cobalt silicide (Co-silicide) on the surface of the source 141, the drain 142, or the gate 143 of the transistor 14 by tungsten (W). The structure of the connection member 21 is shown in fig. 3, and the connection member 21 includes tungsten (tungsten) 221, a composite layer 222, and a first dielectric layer 22 (ILD). The first dielectric layer 22 may be silicon oxide or other low dielectric constant material. Alternatively, the composite layer 222 may be a TaN/Ti/TiN composite layer, i.e., a TaN layer, a Ti layer, and a TiN layer are sequentially formed on the surface of tungsten (W). Alternatively, the composite layer 222 may be a Ti/TiN composite layer, in which a Ti layer and a TiN layer are sequentially formed on the surface of tungsten (W). Alternatively, the composite layer 222 may be a Ta/TaN composite layer, i.e., a Ta layer and a TaN layer are sequentially formed on the surface of tungsten (W). Wherein, the TaN/Ti/TiN composite layer has better barrier effect on the diffusion of metal tungsten to the first dielectric layer 22 than the Ti/TiN composite layer or the Ta/TaN composite layer at high temperature. Wherein, the Ti layer can be prepared by MOCVD or IMP method; the TiN layer can be prepared by adopting a PVD method; the Ta layer and the TaN layer can be prepared by adopting a PVD or ALD method.
Each metal layer includes a metal interconnection 33, a connection 35, and a second dielectric layer 34 (IMD). The connecting member 35 may connect adjacent metal layers (e.g., the metal layer 31 and the metal layer 32), and the connecting member 35 may be made of other metal materials such as tungsten and copper.
The second dielectric layer 34 is a silicon oxide dielectric layer and is formed by PECVD or SACVD using SiH4 or TEOS. Although the dielectric constant of silicon oxide (k = 3.9) is higher than that of conventional low-k materials (k = 2.4-3.3) and causes a certain RC Delay (RC Delay), the thermal stability of the silicon oxide dielectric layer is better than that of conventional low-k layers, such as SiCOH or fteos (f doped TEOS oxide) fluorine-doped silicon oxide. The latter two materials are thermally decomposed at high temperature, and the dielectric constant is increased. Meanwhile, the silicon oxide has stronger mechanical property than SiCOH, and plays a good role in blocking the thermal expansion of the copper wire in a high-temperature process.
The metal interconnection structure 33 can be referred to fig. 4A and 4B. As shown in fig. 4A, the metal interconnection structure 33 includes a copper line 331, a diffusion barrier layer 332, an isolation layer 333, and a second dielectric layer 34. Diffusion barrier 332 is formed on the sidewalls and bottom of copper line 331. An isolation layer 333 is formed on top of the copper line 331. Alternatively, the diffusion barrier layer 332 may comprise a TaN/Ti/TiN composite layer, i.e., a TaN layer, a Ti layer and a TiN layer are sequentially formed on the copper surface. Alternatively, the diffusion barrier layer 332 may be a Ti/TiN composite layer, i.e., a Ti layer and a TiN layer are sequentially formed on the copper surface. Alternatively, the diffusion barrier layer 332 may be a Ta/TaN composite layer, i.e., a Ta layer and a TaN layer are sequentially formed on the copper surface. The spacer layer 333 may be one or more layers of SiCN, SiCO, or SiN. Wherein, the Ti layer can be prepared by MOCVD or IMP method; the TiN layer can be prepared by adopting a PVD method; the Ta layer and the TaN layer can be prepared by adopting a PVD or ALD method. The isolation layer 333 may be formed by PECVD.
Fig. 4B is a schematic diagram of another exemplary metal interconnect structure 33. A gap of a certain width exists between the diffusion barrier layer 332 and the second dielectric layer 34. The gap is advantageous to reduce damage caused by mechanical pressing of the copper wire 331 against the second dielectric layer 34 on the sidewall during thermal expansion and contraction in the subsequent process.
As shown in fig. 8, after the carrier wafer 50 is connected to the multi-layered metal layer by bonding the oxide layer 40, the back surface of the semiconductor substrate 10 may be thinned to a certain thickness.
As shown in fig. 9A, a deep trench 130 is formed by masking, etching, etc. to align with the central region of the doped isolation region 12 and extend from the back surface to the surface or inside of the doped isolation region 12. It is noted that the deep trench 130 may partially or completely enter the interior of the doped isolation region 12. As shown in fig. 9B, a portion of the deep trench 130 can be surrounded by the doped isolation region 12. The deep trench 130 can have a width less than the width of the doped isolation region 12.
As shown in fig. 10, a doped epitaxial layer 131 may be formed on the surface of the deep trench 130 through a low temperature epitaxial growth process. Specifically, an epitaxial doping layer 131 and a photosensitive cell 11 are formed on the sidewall and the bottom of the deep trench 130 and the back surface of the semiconductor substrate 10, wherein the epitaxial doping layer 131 is doped with an epitaxial layer 131. For example, the light sensing unit 11 is n-type, and the epitaxial doped layer 131 is p-type; the photosite 11 is p-type and the epitaxial doped layer 131 is n-type. Thus, the deep trench sidewalls may form a lateral PN junction. The epitaxial doped layer 131 may be silicon or germanium. For example, Boron (Boron, B) or other p-type doping element may be used for doping, and the doping concentration may be controlled between 1e15 and 1e 17.
In some embodiments, the thickness of the epitaxial doped layer 131 may be 0.05 to 0.1 microns. In some embodiments, the doping concentration profile of the epitaxial doping layer 131 may be a uniform profile or a non-uniform profile. In some embodiments, the temperature of the epitaxial growth does not exceed 950 ℃; in some embodiments, the temperature of the epitaxial growth may be appropriately adjusted according to the heat resistance of different devices (e.g., a connection conductor, a metal layer, etc. on the surface of a source, a drain, or a gate of a transistor), for example, the temperature of the epitaxial growth does not exceed 800 ℃.
As shown in fig. 11 and 12, at least one dielectric layer and fill material, such as dielectric layer 132 and fill material 133, may continue to be filled within deep trench 130. The dielectric layer may include hafnium oxide (HfO)2) Alumina (Al)2O3) Silicon oxide (SiO)2) Tantalum oxide (TaO)2) At least one of (1). For example, the dielectric layer 132 may be HfO2、Al2O3、SiO2Or TaO2(ii) a The filler material 133 may be tungsten or aluminum.
As shown in fig. 1, after the deep trench isolation structure 13 is formed, the color filter 60 and the microlens 70 are continuously formed, thereby forming the back-illuminated image sensor.
Fig. 13 is an exemplary flowchart of another method for manufacturing a back-illuminated image sensor according to an embodiment of the present invention.
The method 1300 of manufacturing a backside illuminated image sensor comprises the steps of:
step 1302, forming a deep trench on the back surface of the semiconductor substrate;
step 1303, forming a doped epitaxial layer on the surface of the deep trench through epitaxial growth; wherein a lateral PN junction is formed on a sidewall of the deep trench.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (26)
1. A method of fabricating a back-illuminated image sensor, comprising:
providing a semiconductor substrate comprising a photosensitive unit;
forming a deep trench on the back surface of the semiconductor substrate;
forming a doped epitaxial layer on the surface of the deep groove by epitaxial growth;
wherein a lateral PN junction is formed on a sidewall of the deep trench.
2. The method of claim 1, wherein the temperature of the epitaxial growth does not exceed 950 ℃, and the epitaxial material is single crystal silicon or single crystal germanium.
3. The method of claim 1, further comprising:
forming a transistor on the front surface of the semiconductor substrate;
cobalt silicide is formed on the surface of the gate, the drain or the source of the transistor to improve the thermal stability during the epitaxial growth process.
4. The method of claim 1, wherein the transistor formed on the front side of the semiconductor substrate comprises:
forming a transistor including an LDD region and a Halo region through a Lightly Doped Drain (LDD) and lateral ion (pocket implant) implantation process to reduce a short channel effect and prevent a source and a drain of the transistor from being perforated; wherein the doping element comprises boron, indium or arsenic.
5. The method of claim 3, further comprising:
forming a plurality of metal layers on the front surface of the semiconductor substrate;
connecting a first metal layer in the multiple metal layers with cobalt silicide on the surface of a grid electrode, a drain electrode or a source electrode of the transistor through tungsten;
wherein, a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer and a first dielectric layer are formed on the surface of the tungsten.
6. The method of claim 5, wherein each of the plurality of metal layers comprises:
a copper line, a diffusion barrier layer and a second dielectric layer;
the diffusion barrier layer is formed on the side wall and the bottom of the copper wire;
wherein the diffusion barrier layer comprises a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer.
7. The method of claim 6 wherein a gap of a width exists between the diffusion barrier layer and the second dielectric layer to relieve stress caused by thermal expansion of the copper lines.
8. The method of claim 7 wherein the copper line is topped with a spacer layer of one or more of SiCN, SiCO or SiN.
9. The method of claim 6, wherein the second dielectric layer is formed using silane or tetraethyl orthosilicate by Plasma Enhanced Chemical Vapor Deposition (PECVD) or sub-atmospheric pressure chemical vapor deposition (SACVD).
10. The method of claim 1, wherein the forming a doped epitaxial layer on the deep trench comprises:
and forming the doped epitaxial layer on the side wall and the bottom of the deep groove and the back surface of the semiconductor substrate.
11. The method of claim 10, wherein the doped epitaxial layer has a thickness of 0.05 to 0.1 microns.
12. The method of claim 1, wherein the semiconductor substrate front side comprises:
doping the isolation region; the photosensitive unit is partially isolated by the doped isolation region;
the forming the deep trench includes:
aligning the doped isolation region, and forming the deep trench by etching; wherein the deep trench extends from the backside to a surface or an interior of the doped isolation region.
13. The method of claim 1,
after the doped epitaxial layer is formed on the deep groove, filling at least one dielectric layer in the deep groove to form a deep groove isolation structure; the at least one dielectric layer comprises HfO2、Al2O3、SiO2、TaO2At least one of;
and continuously filling at least one of W or Al in the at least one dielectric layer.
14. The method of claim 13,
forming a color filter on the deep trench isolation structure;
and forming a micro lens on the color filter.
15. The method of claim 5,
bonding the multilayer metal layer with a bearing wafer through a bonding oxide layer;
and thinning the back surface of the semiconductor substrate.
16. A backside illuminated image sensor, comprising:
a semiconductor substrate having a front surface and a back surface; the semiconductor substrate comprises a photosensitive unit and a doped isolation region; the doped isolation region is formed on the front surface of the semiconductor substrate and extends from the front surface to the interior of the semiconductor;
the deep trench isolation structure is formed on the back surface of the semiconductor substrate and extends to the interior of the semiconductor from the back surface;
the deep trench isolation structure includes:
a deep trench extending from the backside to the surface or the interior of the doped isolation region; the epitaxial doping layer is formed on the surface of the deep groove; and forming a lateral PN junction on the side wall of the deep groove.
17. The back-illuminated image sensor of claim 16, further comprising:
the transistor is formed on the front surface of the semiconductor substrate;
a plurality of metal layers formed over the front side of the semiconductor substrate;
wherein, cobalt silicide is formed on the surface of the grid electrode, the drain electrode or the source electrode of the transistor so as to improve the thermal stability in the epitaxial growth process.
18. The back-illuminated image sensor of claim 17,
the transistor further includes a Lightly Doped Drain (LDD) region and a Halo region formed by a pocket implant process to reduce a short channel effect and prevent a source and a drain of the transistor from being penetrated; wherein the doping element comprises boron, indium or arsenic.
19. The back-illuminated image sensor of claim 17,
the first metal layer in the multiple metal layers is connected with the cobalt silicide on the surface of the grid electrode, the drain electrode or the source electrode of the transistor through tungsten;
wherein, a TaN/Ti/TiN composite layer, a Ti/TiN layer or a Ta/TaN layer and a first dielectric layer are formed on the surface of the tungsten.
20. The back-illuminated image sensor of claim 17, wherein each of the plurality of metal layers comprises:
a copper line, a diffusion barrier layer and a second dielectric layer;
the diffusion barrier layer is formed on the side wall and the bottom of the copper wire;
wherein the diffusion barrier layer comprises a TaN/Ti/TiN composite layer, a Ti/TiN composite layer or a Ta/TaN composite layer.
21. The back-illuminated image sensor of claim 20, wherein a gap of a width exists between the diffusion barrier layer and the second dielectric layer to relieve stress caused by thermal expansion of the copper lines.
22. The back-illuminated image sensor of claim 20, wherein the copper lines are topped with a spacer layer of one or more of SiCN, SiCO, or SiN.
23. The back-illuminated image sensor of claim 16, wherein the deep trench isolation structure further comprises:
at least one dielectric layer filled in the deep trench; the at least one dielectric layer comprises HfO2、Al2O3、SiO2、TaO2At least one of; and at least one of W or Al is filled in the at least one dielectric layer.
24. The back-illuminated image sensor of claim 16, further comprising:
the color filter is formed on the deep groove isolation structure;
and the micro lens is formed on the color filter.
25. The back-illuminated image sensor as in any one of claims 16-24, the epitaxially doped layer is formed by epitaxial growth and the temperature does not exceed 950 ℃.
26. The back-illuminated image sensor of any one of claims 16-24, wherein the epitaxial layer has a thickness of 0.05-0.1 microns.
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