CN114333690A - Drive circuit, display panel and display device - Google Patents
Drive circuit, display panel and display device Download PDFInfo
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Abstract
The application discloses drive circuit, display panel and display device. The driving circuit comprises a first control unit and a second control unit, wherein the first control unit comprises a first transistor, and the first control unit is used for adjusting the conducting state of the first transistor according to a first data signal when receiving the first data signal output by the first data line; the second control unit comprises a second transistor, and is used for adjusting the conducting state of the second transistor according to a first data signal when receiving the first data signal output by the second data line; the first data line and the second data line alternately output a first data signal during a first frame refresh period. According to the embodiment of the application, the transistors in the two control units can be kept in a dynamic clamping state, the phenomenon that the device characteristics drift due to the fact that the driving transistors are in a one-way clamping state for a long time is avoided, and the service life of the driving circuit is prolonged.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a driving circuit, a display panel and display equipment.
Background
At present, in a Mini LED (sub millimeter Light emitting diode)/Micro LED (Micro Light emitting diode) display panel, a transistor is generally connected in series with a Light emitting device to control the Light emitting device to emit Light.
However, when the transistor is turned on to make the light emitting device emit light, the gate of the transistor is kept at a high potential, and the source and the drain of the transistor are kept at a low potential, so that the transistor is in a unidirectional clamping state in an operating state. When the transistor is in a unidirectional clamping state for a long time, the characteristic drift of the device is easily caused, so that the threshold voltage of the transistor is changed, and the luminous brightness and the luminous effect of the luminous device are influenced.
Disclosure of Invention
The embodiment of the application provides a driving circuit, a display panel and display equipment, and can solve the technical problem that a transistor in the existing driving circuit is in unidirectional clamping voltage and characteristic drift occurs.
In a first aspect, an embodiment of the present application provides a driving circuit, where the driving circuit includes:
the first control unit comprises a first transistor, the first end of the first transistor is connected with a first power supply signal through a light-emitting device, the second end of the first transistor is connected with a second power supply signal, the data signal end of the first control unit is connected with a first data line, and the scanning signal end of the first control unit is connected with a scanning signal line; the first control unit is used for adjusting the conducting state of the first transistor according to the first data signal when receiving the first data signal output by the first data line;
the second control unit comprises a second transistor, the first end of the second transistor is connected with the first power supply signal through the light-emitting device, the second end of the second transistor is connected with the second power supply signal, the data signal end of the second control unit is connected with the second data line, and the scanning signal end of the second control unit is connected with the scanning signal line; the second control unit is used for adjusting the conducting state of the second transistor according to the first data signal when receiving the first data signal output by the second data line;
the first data line and the second data line alternately output a first data signal in a first frame refresh period.
In a second aspect, an embodiment of the present application provides a display panel, including:
a plurality of light emitting devices arranged in an M x N array;
the driving circuits are respectively correspondingly connected with the light-emitting devices and are the driving circuits;
the two scanning signal ends of the driving circuits in the same row are connected with the corresponding same scanning signal line;
and two data signal ends of the driving circuits in the same column are respectively connected with the two corresponding data signal lines.
In a third aspect, the present application provides a display device, which includes the above display panel.
Compared with the prior art, the driving circuit provided by the embodiment of the application is respectively communicated with the light-emitting device through the two transistors in the two control units by arranging the two control units, and the two transistors can control the light-emitting device to emit light. In the first frame refresh period, the two data lines alternately output the first data signal, one of the control units is used to drive the light emitting device 30 to emit light in one cycle period, and the other control unit is used to drive the light emitting device 30 to emit light in the next cycle period. When the driving transistors of the control units are switched back and forth between a light-emitting driving state and a light-emitting non-driving state, the clamping states of the driving transistors are also switched between positive clamping and negative clamping, so that the driving transistors in the two control units are kept in dynamic clamping states, the phenomenon that the driving transistors are in a one-way clamping state for a long time to cause the characteristics of devices to drift is avoided, and the service life of the driving circuit is prolonged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a driving circuit according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating signal timings and node potentials of a first control unit during a first frame refresh period according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating signal timings and node potentials of a second control unit during a first frame refresh period according to an embodiment of the present disclosure;
FIG. 7 is a diagram illustrating signal timing and node potentials for a second frame refresh period according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present application.
In the drawings:
1. a drive circuit; 10. a first control unit; 20. a second control unit; 30. a light emitting device; scan, scanning signal line; data1, a first Data line; data2, a second Data line; emit1, a first light emission control line; emit2, a second light emission control line; T1-T6, first transistor-sixth transistor; c1, a first capacitance; c2, a second capacitor; VDD, a first power supply signal; VSS, a second power supply signal; .
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.
At present, in a Mini LED/Micro LED display panel, a transistor is generally connected in series with a light emitting device, and the light emitting device is controlled to emit light by outputting a scanning signal line by line.
When the light emitting device emits light, the transistor on the light emitting circuit is in a conducting state. In the conducting state, the grid electrode of the transistor is in a high potential, and the source electrode and the drain electrode of the transistor are kept in a low potential, so that the transistor is in a unidirectional clamping state. When the transistor is in a unidirectional clamping state for a long time, the transistor is easy to generate device characteristic shift, so that the threshold voltage of the transistor is changed. When the threshold voltage of the transistor is shifted, the transistor cannot be normally turned on when receiving an effective signal of a scan signal, or is abnormally turned on when not receiving the scan signal. That is, when the threshold voltage of the transistor is shifted, the light emission control of the light emitting device is not performed, and the light emission luminance and the light emission effect of the light emitting device are affected.
In order to solve the above technical problem, embodiments of the present application provide a driving circuit, a display panel and a display device. The following first describes a driving circuit provided in an embodiment of the present application.
Fig. 1 shows a schematic structural diagram of a driving circuit according to an embodiment of the present application. The drive circuit comprises a first control unit 10 and a second control unit 20.
The first control unit 10 includes a first transistor T1, a first terminal of the first transistor T1 is connected to a first power signal VDD through the light emitting device 30, a second terminal of the first transistor T1 is connected to a second power signal VSS, a Data signal terminal of the first control unit 10 is connected to a first Data line Data1, a Scan signal terminal of the first control unit 10 is connected to a Scan signal line Scan, and the first control unit 10 can adjust a turn-on state of the first transistor T1 according to a first Data signal when receiving the first Data signal output from the first Data line Data 1.
The second control unit 20 includes a second transistor T2, a first terminal of the second transistor T2 is connected to the first power signal VDD through the light emitting device 30, a second terminal of the second transistor T2 is connected to the second power signal VSS, a Data signal terminal of the second control unit 20 is connected to the second Data line Data2, a Scan signal terminal of the second control unit 20 is connected to the Scan signal line Scan, and the first control unit 10 may adjust a turn-on state of the second transistor T2 according to the first Data signal when receiving the first Data signal output from the second Data line Data 2.
In the first frame refresh period, the first Data line Data1 and the second Data line Data2 alternately output the first Data signal.
The display panel may include a plurality of pixel units arranged in an array, each of which is composed of a driving circuit and a light emitting device 30. The pixel units in the same row are connected to the same Scan signal line Scan. In the first control unit 10, the first transistor T1 may communicate the light emitting device 30 with the first power signal VDD and the second power signal VSS when turned on to drive the light emitting device 30 to emit light, and the first transistor T1 is a driving transistor in the first control unit 10. Likewise, the second transistor T2 is a driving transistor in the second control unit 20.
The first frame refresh period may include a plurality of image frames. In each image frame, the display panel may send the scanning signals line by line from the scanning signal line Scan of the first row until the scanning signal line Scan of the last row finishes sending the scanning signals, indicating that the image frame is finished. That is, each pixel unit on the display panel receives the scan signal only once and only once in each image frame.
The cycle period in which the first Data line Data1 and the second Data line Data2 alternately output the first Data signal may be set to one image frame or a plurality of image frames within the first frame refresh period. That is, the first Data signal is alternately output every one image frame of the first Data line Data1 and the second Data line Data2 or the first Data signal is alternately output every a plurality of image frames of the first Data line Data1 and the second Data line Data 2.
The first Data line Data1 may output the first Data signal in the first image frame or image frames in a certain cycle period. The first Data signal is output through the second Data line Data2 at an image frame or a plurality of image frames subsequent to the image frame or the plurality of image frames. That is, the Data lines outputting the first Data signals may alternate between the first Data lines Data1 and the second Data lines Data2 every one or more image frames.
In this cycle, if the first Data signal is output through the first Data line Data1, when the plurality of pixel units in the same row receive the Scan signal sent by the Scan signal line Scan, and if it is necessary to control some of the plurality of pixel units in the row to emit light, the driving circuits corresponding to some of the pixel units may be determined, and the first Data signal for driving the light emitting device 30 to emit light may be output through the first Data line Data1 connected to these driving circuits. That is, the first Data lines Data1 may be connected to the first control units 10 of the plurality of driving circuits on the same column, and the number of the first Data lines Data1 is the same as the number of columns of the driving circuits. In the plurality of rows of the first Data lines Data1, if it is necessary to control the light emitting devices 30 on the corresponding row to emit light, a first Data signal for driving the light emission is transmitted through the first Data line Data1 on the corresponding row; if it is necessary to control the light emitting devices 30 on the corresponding columns not to emit light, a first Data signal for not driving light emission is transmitted through the first Data line Data1 on the corresponding column. For example, the first Data signal may be an active high signal, and when it is necessary to control the corresponding light emitting device 30 to emit light, the first Data signal may be transmitted through the first Data line Data1 connected to the driving circuit corresponding to the light emitting device 30; when the light emitting device 30 is not required to emit light, a low level signal may be transmitted.
It is understood that a data writing transistor is provided in each of the first and second control units 10 and 20, and the data writing transistor may be turned on upon receiving a scan signal to write a data signal to the driving transistor. Since the plurality of driving circuits in the same row are connected to the same scanning signal line Scan, the data writing transistors of the driving circuits in the same row are turned on in synchronization with each other when the same scanning signal is received. For each driving circuit, since the first control unit 10 and the second control unit 20 are connected to the same Scan signal line Scan and receive the same Scan signal, the data writing transistors in the first control unit 10 and the second control unit 20 are also kept turned on or off synchronously. That is, the data writing transistors of the first control unit 10 and the second control unit 20 of each driving circuit on the same row are kept turned on in synchronization.
When the Data writing transistors of the two control units receive the scan signal and are turned on in synchronization, since the first Data line Data1 outputs the first Data signal at this time, the first Data signal may be written into the first transistor T1 of the first control unit 10 through the Data writing transistor and control the on state of the first transistor T1. Since the second Data line Data2 does not output a corresponding signal, even if the Data writing transistor in the second control unit 20 is turned on, the second transistor T2 in the second control unit 20 cannot receive the first Data signal, and at this time, the second transistor T2 cannot adjust the turned-on state by receiving the first Data signal. That is, the first Data signal is output on the first Data line Data1, the first control unit 10 can drive the light emitting device 30 to emit light at this time, and the second control unit 20 does not perform the driving operation.
It can be understood that when the display panel outputs the first Data signal through the first Data line Data1, if the pixel unit corresponding to the driving circuit needs to emit light, the first Data signal is a turn-on signal for controlling the turn-on of the driving transistor; if the pixel unit corresponding to the driving circuit is not required to emit light, the first data signal is a cut-off signal for controlling the cut-off of the driving transistor. For example, when the first transistor T1 is an N-type transistor and the driving circuit is required to drive the light emitting device 30 to emit light, the first data signal is a high level signal, and when the first control unit 10 receives a Scan signal through the Scan signal line Scan, the high level signal may be connected to the gate of the first transistor T1 to turn on the first transistor T1. If the light emitting device 30 is not required to emit light, the first data signal may be a low level signal, and when the first control unit 10 receives the Scan signal through the Scan signal line Scan and switches the low level signal to the gate of the first transistor T1, the first transistor T1 is kept turned off. That is, when the first Data line Data1 outputs the first Data signal, the first transistor T1 may be turned on or off according to a signal level of the first Data signal.
For the second control unit 20, although the second Data line Data2 of the second control unit 20 is also connected to the second transistor T2 when the first Data line Data1 of the first control unit 10 is connected to the first transistor T1, since the second Data line Data2 does not output the first Data signal, the second transistor T2 of the second control unit 20 cannot receive the first Data signal at this time, and thus cannot adjust the on state. It can be understood that the second Data line Data2 may continuously output a turn-off signal controlling the turn-off of the second transistor T2 when the first Data signal is not output, so that the second transistor T2 maintains a turn-off state due to the receipt of the turn-off signal when the second control unit 20 receives the scan signal.
Within a certain cycle period, the first transistor T1 of the first control unit 10 of the driving circuit can receive the first Data signal transmitted by the first Data line Data1 to drive the light emitting device 30 to emit light or extinguish. At this time, the second transistor T2 of the second control unit 20 does not receive the first data signal, and cannot drive the light emitting device 30 to emit light.
When the first control unit 10 drives the light emitting device 30 to emit light, if the first transistor T1 is turned on, the gate of the first transistor T1 is at a high potential, and the source and the drain of the first transistor T1 are at a low potential, so that the first transistor T1 is in a forward-direction clamping state. While the second control unit 20 does not drive the light emitting device 30 to emit light, the gate of the second transistor T2 is at a low voltage level, and the second transistor T2 is kept in a negative-voltage-clamping state.
When the next cycle period is entered, the output signals of the first Data line Data1 and the second Data line Data2 alternate, and at this time, the first Data signal is output from the second Data line Data2, and the second transistor T2 in the second control unit 20 can drive the light emitting device 30 to emit light by receiving the first Data signal output from the second Data line Data 2. When the second transistor T2 is turned on, the gate of the second transistor T2 is at a high voltage level, and the source and the drain of the second transistor T2 are at a low voltage level, so that the second transistor T2 is in a forward clamping state. The gate of the first transistor T1 is at a low voltage level, and the first transistor T1 is kept at the negative-going clamp state.
With one or more image frames as a cycle period, in the current cycle period, the driving transistor of one of the first control unit 10 and the second control unit 20 can receive the written first data signal and drive the light emitting device 30 to emit light, and when the light emitting device 30 is driven to emit light, the driving transistor of the control unit is in a positive clamping state, and the driving transistor of the other control unit is in a negative clamping state. When the next cycle is entered, the driving transistor that has been kept in the positive-direction pinch-off state in the previous cycle does not drive the light-emitting device 30 to emit light in the previous cycle, and thus keeps keeping the negative-direction pinch-off state. The driving transistor that was kept in the negative-direction pinch-off state in the previous cycle drives the light emitting device 30 to emit light in the present cycle, that is, keeps the positive-direction pinch-off state.
In each two adjacent cycle periods, the driving transistors in the first control unit 10 and the second control unit 20 are both held in positive clamping in one cycle period and in negative clamping in the other cycle period. The driving transistor can be switched between a positive clamping state and a negative clamping state, so that the driving transistor can be in a dynamic clamping state, and the phenomenon that the device characteristics of the transistor drift due to long-time unidirectional clamping is avoided.
In the present embodiment, the driving circuit can drive the light emitting device 30 to emit light by using one of the control units in one cycle period and drive the light emitting device 30 to emit light by using the other control unit in the next cycle period by providing the first control unit 10 and the second control unit 20. When the driving transistors of the control units are switched back and forth between a light-emitting driving state and a light-emitting non-driving state, the clamping states of the driving transistors are also switched between positive clamping and negative clamping, so that the driving transistors in the two control units are kept in dynamic clamping states, the phenomenon that the driving transistors are in a one-way clamping state for a long time to cause the characteristics of devices to drift is avoided, and the service life of the driving transistors is prolonged.
In some embodiments, the first frame refresh period may include a plurality of image frames, and the first Data line Data1 outputs the first Data signal and the second Data line Data2 outputs the low potential signal from the nth frame of the first frame refresh period; from the N + M-th frame of the first frame refresh period, the second Data line Data2 outputs the first Data signal, and the first Data line Data1 outputs the low potential signal. Wherein N, M may be a positive integer.
In the N-th frame to the N + M-1 frame of the first frame refresh period, a total of M image frames may be included, in which the first Data signal may be output from the first Data line Data1, and the second Data line Data2 outputs the low potential signal, so that the second transistor T2 of the second control unit 20 receives the low potential signal to be kept off and in the negative-direction pinch-off state.
In M image frames starting from the N + M-th frame of the first frame refresh period, the first Data signal may be output from the second Data line Data2, and the first Data line Data1 outputs a low potential signal, so that the first transistor T1 of the first control unit 10 receives the low potential signal to be kept off and to be in a negative-direction pinch-off state.
That is, the first Data line Data1 and the second Data line Data2 are alternately output every M image frames. In the M image frames, one of the first transistor T1 of the first control unit 10 or the second transistor T2 of the second control unit 20 maintains a negative-direction pinch-in state, and the other one maintains a positive-direction pinch-in state. In the following M image frames, the transistors in the negative clamping state are switched to the positive clamping state, and the transistors in the positive clamping state are switched to the negative clamping state, so that the dynamic clamping of the transistors is realized.
In some embodiments, in the nth frame of the first frame refresh period, the first Data line Data1 outputs the first Data signal, and the second Data line Data2 outputs the low potential signal; in the (N + 1) th frame of the first frame refresh period, the second Data line Data2 outputs the first Data signal, and the first Data line Data1 outputs the low potential signal.
It is understood that, when M is 1, the first Data line Data1 and the second Data line Data2 may output the first Data signal every other one image frame. That is, the first transistor T1 is positively and negatively clamped in any adjacent two image frames, respectively, and the second transistor T2 is also positively and negatively clamped in any adjacent two image frames, respectively. The first Data line Data1 and the second Data line Data2 are arranged to alternately output the first Data signals at intervals of one image frame, so that the frequency of dynamic clamping can be improved, and the phenomenon that the transistor keeps positive clamping or negative clamping under a plurality of image frames to generate device characteristic drift can be avoided.
In the above embodiment, the first transistor T1 and the second transistor T2 are N-type transistors, for example. When the N-type transistors are turned on by a high-potential signal, the two transistors are turned on to the cell, and the driving transistor in the control cell that drives the light emitting device 30 to emit light is in a positive-direction clamping state, while the driving transistor in the control cell that does not drive the light emitting device 30 to emit light is in a negative-direction clamping state. The driving transistors in the two control units may be P-type transistors, and the first transistor T1 and the second transistor T2 are turned on by low-level signals. The driving transistor in the control unit that drives the light emitting device 30 to emit light is in a negative-direction pinch-off state, and the driving transistor in the control unit that does not drive the light emitting device 30 to emit light is in a positive-direction pinch-off state.
Depending on the transistor type of the driving transistor, it is necessary to adjust the signal potential of the first Data signal and the signal potential of the other Data signal in the first Data line Data1 and the second Data line Data2 so that the first transistor T1 and the second transistor T2 can be in positive-going pinch and negative-going pinch, respectively, and can switch between the positive-going pinch and the negative-going pinch to realize dynamic pinch.
Referring to fig. 2, in some embodiments, the first control unit 10 may include a third transistor T3, a first terminal of the third transistor T3 is connected to the first terminal of the first transistor T1, a second terminal of the third transistor T3 is connected to the light emitting device 30, and a control terminal of the third transistor T3 is connected to the first light emitting control line Emit 1. The second control unit 20 may include a fourth transistor T4, a first terminal of the fourth transistor T4 being connected to the first terminal of the second transistor T2, a second terminal of the fourth transistor T4 being connected to the light emitting device 30, and a control terminal of the fourth transistor T4 being connected to the second light emission control line Emit 2.
The third transistor T3 is a light emission control transistor in the first control unit 10, and may receive the first light emission control signal transmitted from the first light emission control line Emit1 to control light emission of the light emitting device 30. The fourth transistor T4 is a light emission control transistor in the second control unit 20 and can receive the second light emission control signal transmitted by the second light emission control line Emit2 to control light emission of the light emitting device 30.
In some embodiments, from the nth frame of the first frame refresh period, the first emission control line Emit1 outputs an emission control signal, and the second emission control line Emit2 outputs a low potential signal; from the N + M-th frame of the first frame refresh period, the first emission control line Emit1 outputs a low potential signal, and the second emission control line Emit2 outputs an emission control signal.
When the cycle period is M image frames, if the first transistor T1 in the first control unit 10 receives the first data signal and drives the light emitting device 30 to Emit light, the first light emission control line Emit1 may output a light emission control signal to the third transistor T3 to control the display luminance of the light emitting device 30. If the second transistor T2 in the second control unit 20 receives the first data signal and drives the light emitting device 30 to Emit light, the second emission control line Emit2 may output a light emission control signal to the fourth transistor T4 to control the display luminance of the light emitting device 30. That is, when the first control unit 10 drives the light emitting device 30 to Emit light, the first light emission control line Emit1 outputs a light emission control signal, and the second light emission control line Emit2 outputs a low potential signal; when the second control unit 20 drives the light emitting device 30 to Emit light, the second light emission control line Emit2 outputs a light emission control signal, and the first light emission control line Emit1 outputs a low potential signal.
It should be noted that the light emitting device 30 can be driven to emit light only when the first transistor T1 and the third transistor T3 are turned on simultaneously, the first transistor T1 and the third transistor T3 can be N-type transistors, and when the first transistor T1 is turned on, the gate is at a high potential, and the source and the drain are at a low voltage; when the third transistor T3 is turned on, the gate is also at a high potential, and the source and drain are at a low potential. That is, when the first control unit 10 drives the light emitting device 30 to emit light, the first transistor T1 and the third transistor T3 are in a forward direction pinch state. At this time, the first data signal received by the second transistor T2 is a low-level signal, and the same signal received by the fourth transistor T4 is a low-level signal. I.e., the second transistor T2 and the fourth transistor T4 are in a negative-going pinch-off state.
Similarly, when the second control unit 20 drives the light emitting device 30 to emit light, the first transistor T1 and the third transistor T3 are in a negative-direction clamping state, and the second transistor T2 and the fourth transistor T4 are in a positive-direction clamping state. The first Data signal is alternately output through the first Data line Data1 and the second Data line Data2, and the light emission control signal is alternately output through the first light emission control line Emit1 and the second light emission control line Emit2, so that the transistors can be kept in a dynamic clamping state, and the service life of the transistor for driving the light emitting device 30 to Emit light is prolonged.
In the above embodiment, one of the two light emission control lines outputs the light emission control signal, and the other outputs the low potential signal, which is exemplified by the third transistor T3 and the fourth transistor T4 both being N-type transistors. It is to be understood that, when the third transistor T3 and the fourth transistor T4 are P-type transistors, one of the two light-emitting control lines outputs a light-emitting control signal, and the light-emitting control signal and the N-type transistor are in opposite phases, and the other light-emitting control line outputs a high-level signal.
In some embodiments, during the second frame refresh period, the first Data line Data1 and the second Data line Data2 each output the second Data signal, and the first emission control line Emit1 and the second emission control line Emit2 each output the emission control signal.
The second frame refresh period may include a plurality of image frames, and the first Data line Data1 and the second Data line Data2 may each output the second Data signal within each image frame, so that the first transistor T1 and the second transistor T2 may each receive the second Data signal when the first control unit 10 and the second control unit 20 in the driving circuit receive the scan signal. And the first emission control line Emit1 and the second emission control line Emit2 each output an emission control signal so that the first control unit 10 and the second control unit 20 can each drive the light emitting device 30 to Emit light in synchronization.
As an alternative embodiment, the signal voltage value of the second data signal may be the same as the signal voltage value of the first data signal.
When the signal voltage value of the second data signal is the same as the signal voltage value of the first data signal, the first transistor T1 of the first control unit 10 and the second transistor T2 of the second control unit 20 can each supply a driving current when the driving current of the light emitting device 30 is increased compared to the driving current when the single control unit is driven, so that the light emitting luminance of the light emitting device 30 is improved. That is, when the light emitting device 30 is driven to emit light by the first control unit 10 and the second control unit 20 at the same time, if the signal voltage value of the data signal is kept constant, the driving current of the light emitting device 30 increases and the light emission luminance increases.
In some embodiments, the signal voltage value of the second data signal may also be less than the signal voltage value of the first data signal.
When the signal voltage value of the second data signal is smaller than the signal voltage value of the first data signal, the driving transistors of the two control units can receive the second data signal and provide the driving current for the light emitting device 30. By adjusting the signal voltage value of the second data signal, the driving current of the light emitting device 30 during light emission is the same as the driving current provided for the light emitting device 30 by a single control unit receiving the first data signal, and the light emission luminance of the light emitting device 30 in the second frame refresh period can be kept consistent with the light emission luminance in the first frame refresh period.
It is to be understood that, when the signal voltage value of the second data signal is adjusted such that the light-emitting luminance is consistent with the light-emitting luminance in the first frame refresh period, since the signal voltage value of the second data signal is smaller than the signal voltage value of the first data signal, the gate potentials of the first transistor T1 and the second transistor T2 when receiving the second data signal are smaller than the gate potential when receiving the first data signal. At this time, although the first transistor T1 and the second transistor T2 are in the forward direction pinch-in state, the pinch-in voltage is reduced due to the reduction of the gate potential, so that the influence of the pinch-in voltage can be reduced, the time required for the transistors to generate the device characteristic drift is increased, and the service life of the transistors is prolonged.
It should be noted that, the light-emitting luminance of the first frame refresh period and the light-emitting luminance of the second frame refresh period are kept consistent, which means that the light-emitting luminance is kept consistent under the same light-emitting control signal.
Referring to fig. 3, in some embodiments, the first control unit 10 may further include a fifth transistor T5 and a first capacitor C1, a control terminal of the fifth transistor T5 is connected to the Scan signal line Scan, a first terminal of the fifth transistor T5 is connected to the first data signal line, a control terminal of the first transistor T1 is connected to a second terminal of the fifth transistor T5, a first terminal of the first capacitor C1 is connected to the control terminal of the first transistor T1, and a second terminal of the first capacitor C1 is connected to the second power signal VSS.
The second control unit 20 may further include a sixth transistor T6 and a second capacitor C2, a control terminal of the sixth transistor T6 is connected to the Scan signal line Scan, a first terminal of the sixth transistor T6 is connected to the second data signal line, a control terminal of the second transistor T2 is connected to a second terminal of the sixth transistor T6, a first terminal of the second capacitor C2 is connected to a control terminal of the second transistor T2, and a second terminal of the second capacitor C2 is connected to the second power supply signal VSS.
The fifth transistor T5 is a Data writing transistor of the first control unit 10, when the gate of the fifth transistor T5 receives a scan signal, the fifth transistor T5 is turned on, the first Data line Data1 is connected to the gate of the first transistor T1 and the first end of the first capacitor C1, at this time, the gate of the first transistor T1 is turned on under the first Data signal, the first capacitor C1 can receive the first Data signal and store energy, and when the fifth transistor T5 is turned off, the first capacitor C1 can release stored charges, so that the gate potential of the first transistor T1 is continuously maintained as the signal voltage of the first Data signal, thereby driving the first transistor T1 to be continuously maintained on.
Similarly, the sixth transistor T6 is a data writing transistor of the second control unit 20, and the way in which the sixth transistor T6 and the second capacitor C2 drive the second transistor T2 to be turned on is the same as the way in which the fifth transistor T5 and the first capacitor C1 drive the first transistor T1, and therefore, the description thereof is omitted.
Referring to fig. 4, an embodiment of the present invention further provides a display panel, which includes a plurality of light emitting devices 30, a plurality of driving circuits 1, M scanning signal lines, and 2N data signal lines.
The plurality of light emitting devices 30 are arranged in an M × N array, the plurality of driving circuits 1 are respectively connected to the plurality of light emitting devices 30, and the driving circuit 1 is the driving circuit 1 in the above embodiment. Two scanning signal ends of the driving circuits 1 in the same row are connected to the same corresponding scanning signal line Scan, and two data signal ends of the driving circuits 1 in the same column are connected to the corresponding two data signal lines, respectively.
The M scanning signal lines are respectively connected to the driving circuits 1 in M rows, each driving circuit 1 in each row includes a scanning signal terminal of the first control unit 10 and a scanning signal terminal of the second control unit 20, and both the scanning signal terminals are connected to the same scanning signal line Scan. That is, one scanning signal line Scan is connected to 2N scanning signal lines Scan of N driving circuits 1 in the same row.
The 2N Data signal lines are respectively connected to the driving circuits 1 of the N columns, and the 2N Data signal lines include N first Data lines Data1 and N second Data lines Data 2. Each of the driving circuits 1 on each column includes a Data signal terminal of the first control unit 10 and a Data signal terminal of the second control unit 20, which are connected to one first Data line Data1 and one second Data line Data2, respectively.
The M scanning signal lines may output scanning signals line by line to control the driving circuit 1 line by line to drive the light emitting device 30 to emit light.
During the first frame refresh period, the display panel transmits the corresponding first Data signals through only the N first Data lines Data1 or transmits the corresponding first Data signals through only the N second Data lines Data 2.
When the corresponding first Data signal is transmitted through the N first Data lines Data1, the first control unit 10 of each driving circuit 1 on the display panel drives the light emitting device 30 to emit light, the transistors in the first control unit 10 on the light emitting loop are clamped in the positive direction, and the corresponding transistors in the second control unit 20 are clamped in the negative direction.
When the corresponding first Data signal is transmitted through the N second Data lines Data2, the second control unit 20 of each driving circuit 1 on the display panel drives the light emitting device 30 to emit light, the transistors in the second control unit 20 on the light emitting circuit are clamped in the positive direction, and the corresponding transistors in the first control unit 10 are clamped in the negative direction.
The N first Data lines Data1 and the N second Data lines Data2 alternately output first Data signals, so that transistors on a light emitting loop in the two control units can be switched between a positive clamping state and a negative clamping state, the phenomenon that the transistors are in unidirectional clamping for a long time to generate device characteristic drift is avoided, and the service life of the display panel is prolonged.
Note that, as shown in fig. 4, the first Data line Data1 and the second Data line Data2 may be respectively connected to Data signal terminals of two control units of the driving circuit 1 from both sides of the driving circuit 1. The first Data line Data1 and the second Data line Data2 may also be disposed to be located at one side of the driving circuit 1, for example, both at the left or right side. When the first Data line Data1 and the second Data line Data2 are both located on the same side of the driving circuit 1, the first Data line Data1 and the second Data line Data2 need to be disposed on different metal layers to avoid overlapping of the first Data line Data1 and the second Data line Data2 when accessing the Data signal ends of the two control units of the driving circuit 1. If the first Data line Data1 and the second Data line Data2 are disposed on the same metal layer, the routing lines formed between the two Data lines and the driving circuit 1 need to be disposed on different metal layers.
It is understood that the first Data line Data1 and the second Data line Data2 may be disposed at the same metal layer when the first Data line Data1 and the second Data line Data2 are accessed from both sides of the driving circuit 1, respectively.
In some embodiments, the display panel may also output the second Data signal through both the N first Data lines Data1 and the N second Data lines Data2, and by adjusting the signal voltage of the second Data signal, the driving current of the light emitting device 30 can be made to be consistent with the driving current when the N first Data lines Data1 and the N second Data lines Data2 alternately output the first Data signal, at this time, since the signal voltage of the second Data signal is reduced, the clamping voltage of the transistor on the light emitting loop in the forward clamping state is reduced, the time for the transistor to generate the device characteristic drift can be also prolonged, and the service life of the display panel is prolonged.
In some embodiments, the first frame refresh period may include a plurality of image frames, and starting from the nth frame of the first frame refresh period, one of the two data signal lines corresponding to the driving circuits 1 of the same column outputs the first data signal, and the other outputs the low potential signal; starting from the N + M frame of the first frame refresh period, one of the two data signal lines corresponding to the driving circuits 1 in the same column outputs a low potential signal, and the other outputs a first data signal; wherein N, M is a positive integer.
When the cycle period is set to M image frames, the nth frame to the (N + M-1) th frame of the first frame refresh period may output the first Data signal through the N first Data lines Data 1; the N + M frame to the N +2M-1 frame of the first frame refresh period may output the first Data signal through the N second Data lines Data 2. Thereby realizing that the first control unit 10 and the second control unit 20 alternately drive the light emitting device 30 to emit light every M image frames.
In some embodiments, the display panel may further include 2M light-emitting control lines, and the two light-emitting control terminals of the driving circuit 1 in the same row are respectively connected to the two corresponding light-emitting control lines.
The 2M light emission control lines include M first light emission control lines Emit1 and M second light emission control lines Emit 2. Each of the driving circuits 1 may include the third transistor T3 of the first control unit 10 and the fourth transistor T4 within the second control unit 20. The gate of the third transistor T3 is connected to the first emission control line Emit1 corresponding to the row in which the drive circuit 1 is located, and the gate of the fourth transistor T4 is connected to the second emission control line Emit2 corresponding to the row in which the drive circuit 1 is located.
In the first frame refresh period, the display panel may output the light emission control signal through the M first light emission control lines Emit1 when the first control unit 10 drives the light emitting devices 30; when the second control unit 20 drives the light emitting devices 30, light emission control signals are output through the M second light emission control lines Emit 2.
It is understood that, when the driving circuit 1 includes the driving transistor and the emission control transistor, both of which are in the emission circuit, and since the second emission control line Emit2 does not output the emission control signal when the first control unit 10 operates, both of the fourth transistor T4 and the second transistor T2 are in the negative-direction pinch-off state. Namely, the driving transistor and the light-emitting control transistor on the light-emitting loop can be switched between a positive clamping state and a negative clamping state, so that the influence of unidirectional clamping is avoided, and the service life is prolonged.
In some embodiments, the second frame refresh period may include a plurality of image frames, and in each image frame of the second frame refresh period, two data signal lines corresponding to the driving circuits 1 of the same column each output the second data signal, and two light-emitting control lines corresponding to the driving circuits 1 of the same row each output the light-emitting control signal.
In the second frame refresh period, the first control unit 10 and the second control unit 20 of the driving circuit 1 receive the same scan signal, the same second data signal, and the same light emission control signal, and the first control unit 10 and the second control unit 20 can synchronously perform light emission control on the light emitting device 30.
As an alternative embodiment, the signal voltage value of the second data signal may be set to be the same as the signal voltage value of the first data signal. At this time, since the first control unit 10 and the second control unit 20 both supply the driving current to the light emitting device 30, the light emission luminance of the light emitting device 30 is increased as compared with the light emission luminance when the driving current is supplied by a single control unit.
As an alternative embodiment, the signal voltage value of the second data signal may be set to be smaller than the signal voltage value of the first data signal.
When the signal voltage value of the second data signal is the same as the signal voltage value of the first data signal, the light emission luminance of the light emitting device 30 is larger than the light emission luminance under the first data signal, and by decreasing the signal voltage value of the second data signal, the light emission luminance of the light emitting device 30 can be decreased. When the signal voltage value of the second data signal is reduced so that the light-emitting luminance of the light-emitting device 30 is kept consistent with the light-emitting luminance under the first data signal, the same light-emitting effect as that of a single control unit driving a forensic device can be achieved. And at this moment, because the signal voltage value of the second data signal is reduced, the gate potentials of the transistors in the two control units are reduced, and at this moment, although the transistors are in a forward clamping state, the device characteristic drift speed of the transistors is reduced because the clamping value is reduced, so that the service lives of the transistors and the display panel are prolonged.
It is understood that the first frame refresh period and the second frame refresh period may correspond to two different light emission driving modes, respectively.
The first frame refresh period corresponds to a first light-emitting driving mode in which the first control unit 10 and the second control unit 20 alternately control the light-emitting device 30 to emit light. At the same time, only one control unit drives the light emitting device 30.
As shown in fig. 5 and 6, in the first light emitting driving mode, taking the cycle period of the first frame refresh period as an example of one image frame, fig. 5 shows the scan signal and the first data signal received by the first control unit 10 and the potentials of the corresponding nodes, where N1 is the gate potential of the first transistor T1, and N2 is the gate potential of the third transistor T3.
In the nth image frame, the first control unit 10 and the second control unit 20 may receive the same effective Scan signal Scan, the first control unit 10 may receive an effective first Data signal through the first Data line Data1, and the second control unit 20 may receive a continuously low signal through the second Data line Data 2. At this time, the gate potential of the first transistor T1 is high, and the gate potential of the third transistor T3 when receiving the emission control signal is also high. The gate potential of the second transistor T2 is low, the fourth transistor T4 does not receive the emission control signal, and the gate potential is low. That is, in the nth image frame, the first transistor T1 and the third transistor T3 are positively clamped, and the second transistor T2 and the fourth transistor T4 are negatively clamped.
At the N +1 th image frame, the first control unit 10 and the second control unit 20 can still receive the same effective Scan signal Scan, at this time, the first control unit 10 can receive the continuous low-potential signal through the first Data line Data1, and the second control unit 20 can receive the effective first Data signal through the second Data line Data 2. And at this time, the fourth transistor T4 receives the light emitting control signal, and the second transistor T2 does not receive the light emitting control signal. That is, in the N +1 th image frame, the first transistor T1 and the third transistor T3 are negatively clamped, and the second transistor T2 and the fourth transistor T4 are positively clamped.
The second frame refresh period corresponds to a second light emission driving mode in which the second first control unit 10 and the second control unit 20 simultaneously control the light emitting device 30 to emit light.
As shown in fig. 7, the first control unit 10 and the second control unit 20 are operated synchronously, the first control unit 10 and the second control unit 20 receive the same scan signal, and the first Data line Data1 and the second Data line Data2 also output the same Data signal.
Taking the nth image frame as an example, when the light emitting device is driven to be turned on, the gates of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all kept at a high potential, and at this time, the first transistor T1, the third transistor T3 and the fourth transistor T4 are all in a forward voltage clamping state, but when the light emitting device 30 is driven by two control units to emit light rays with the same brightness, the gate potentials of the first transistor T1 and the second transistor T2 can adopt a lower data voltage, so that the voltage clamping of the first transistor T1 and the second transistor T2 is reduced, and the influence of unidirectional voltage clamping is reduced.
An embodiment of the present application further provides a display device, please refer to fig. 8, where the display device may be a PC, a television, a display, a mobile terminal, a tablet computer, a wearable device, and the like, and the display device may include the driving circuit provided in the embodiment of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted by a first data signal carried in a carrier wave over a transmission medium or communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present application are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present application. It should be noted that there are no specific structures in the above description, and it will be apparent to those skilled in the art that various modifications, decorations, or changes can be made without departing from the principle of the present application, and the technical features can be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the present invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.
Claims (17)
1. A driver circuit, characterized in that the driver circuit comprises:
the first control unit comprises a first transistor, wherein a first end of the first transistor is connected with a first power supply signal through a light-emitting device, a second end of the first transistor is connected with a second power supply signal, a data signal end of the first control unit is connected with a first data line, and a scanning signal end of the first control unit is connected with a scanning signal line; the first control unit is used for adjusting the conducting state of the first transistor according to a first data signal when receiving the first data signal output by the first data line;
a second control unit including a second transistor, a first end of the second transistor being connected to a first power signal through the light emitting device, a second end of the second transistor being connected to a second power signal, a data signal end of the second control unit being connected to a second data line, and a scan signal end of the second control unit being connected to the scan signal line; the second control unit is used for adjusting the conducting state of the second transistor according to the first data signal when receiving the first data signal output by the second data line;
the first data line and the second data line alternately output a first data signal during a first frame refresh period.
2. The drive circuit according to claim 1, wherein the first frame refresh period includes a plurality of image frames, and starting from an nth frame of the first frame refresh period, the first data line outputs the first data signal, and the second data line outputs the low potential signal; starting from the N + M frame of the first frame refresh period, the second data line outputs a first data signal, and the first data line outputs a low potential signal; n, M is a positive integer.
3. The driver circuit according to claim 2, wherein the first data line outputs a first data signal and the second data line outputs a low potential signal in an nth frame of the first frame refresh period; in the (N + 1) th frame of the first frame refresh period, the second data line outputs a first data signal, and the first data line outputs a low potential signal.
4. The drive circuit according to claim 2, wherein the first control unit further comprises:
a third transistor, a first end of the third transistor being connected to the first end of the first transistor, a second end of the third transistor being connected to the light emitting device, and a control end of the third transistor being connected to a first light emitting control line;
the second control unit further includes:
a fourth transistor, a first end of the fourth transistor being connected to the first end of the second transistor, a second end of the fourth transistor being connected to the light emitting device, and a control end of the fourth transistor being connected to a second light emission control line.
5. The drive circuit according to claim 4, wherein the first light emission control line outputs a light emission control signal and the second light emission control line outputs a low potential signal from an nth frame of a first frame refresh period; the first light emission control line outputs a low potential signal and the second light emission control line outputs a light emission control signal from an N + M-th frame of a first frame refresh period.
6. The drive circuit according to claim 4, wherein the second frame refresh period includes a plurality of image frames, and wherein the first data line and the second data line each output the second data signal and the first light emission control line and the second light emission control line each output the light emission control signal in each image frame of the second frame refresh period.
7. The driving circuit according to claim 6, wherein the signal voltage value of the second data signal is the same as the signal voltage value of the first data signal.
8. The driving circuit according to claim 6, wherein the signal voltage value of the second data signal is smaller than the signal voltage value of the first data signal.
9. The drive circuit according to any one of claims 1 to 8, wherein the first control unit further comprises:
a control end of the fifth transistor is connected with the scanning signal line, and a first end of the fifth transistor is connected with the first data signal line;
the control end of the first transistor is connected with the second end of the fifth transistor;
a first end of the first capacitor is connected with the control end of the first transistor, and a second end of the first capacitor is connected with a second power supply signal;
the second control unit further includes:
a control end of the sixth transistor is connected with the scanning signal line, and a first end of the sixth transistor is connected with the second data signal line;
the control end of the second transistor is connected with the second end of the sixth transistor;
and a first end of the second capacitor is connected with the control end of the second transistor, and a second end of the second capacitor is connected with a second power supply signal.
10. A display panel, comprising:
a plurality of light emitting devices arranged in an M x N array;
a plurality of driving circuits respectively connected to the plurality of light emitting devices, the driving circuits being as set forth in any one of claims 1 to 8;
the two scanning signal ends of the driving circuit in the same row are connected with the same corresponding scanning signal line;
and two data signal ends of the driving circuit in the same column are respectively connected with the two corresponding data signal lines.
11. The display panel according to claim 10, wherein the first frame refresh period includes a plurality of image frames, and wherein one of the two data signal lines corresponding to the driving circuits in the same column outputs the first data signal and the other outputs the low potential signal, starting from an nth frame of the first frame refresh period; starting from the (N + M) th frame of the first frame refreshing period, one of two data signal lines corresponding to the driving circuits in the same row outputs a low-potential signal, and the other outputs a first data signal; wherein N, M is a positive integer.
12. The display panel according to claim 11, characterized by further comprising:
and two light-emitting control ends of the driving circuit in the same row are respectively connected with the two corresponding light-emitting control lines.
13. The display panel according to claim 12, wherein one of the two light-emission control lines corresponding to the driver circuits in the same row outputs a high-potential signal and the other outputs a low-potential signal from an nth frame of the first frame refresh period; starting from the (N + M) th frame of the first frame refresh period, one of the two light-emitting control lines corresponding to the driving circuits in the same row outputs a low-potential signal, and the other outputs a high-potential signal.
14. The display panel according to claim 12, wherein the second frame refresh period comprises a plurality of image frames, and in each image frame of the second frame refresh period, two data signal lines corresponding to the driving circuits in the same column output the second data signal, and two light-emitting control lines corresponding to the driving circuits in the same row output the light-emitting control signal.
15. The display panel according to claim 14, wherein the signal voltage value of the second data signal is the same as the signal voltage value of the first data signal.
16. The display panel according to claim 14, wherein a signal voltage value of the second data signal is smaller than a signal voltage value of the first data signal.
17. A display device characterized in that it comprises a display panel as claimed in any one of claims 10-16.
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