CN114326908B - LDO circuit with built-in automatic temperature compensation function, working method and power supply - Google Patents
LDO circuit with built-in automatic temperature compensation function, working method and power supply Download PDFInfo
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Abstract
The invention belongs to the field of circuit design, and provides an LDO circuit with an automatic temperature compensation function, a working method and a power supply. The LDO circuit comprises a soft start circuit, a high-temperature leakage current compensation circuit and a high-temperature leakage current compensation circuit, wherein the soft start circuit comprises a high-temperature leakage current compensation circuit; the soft start circuit is used for electrifying the input voltage to a voltage threshold value in a soft start mode and preventing the band gap amplifier from being turned off by mistake when the input voltage reaches a set high temperature; a bias circuit for starting operation when the input voltage is powered up to a set voltage threshold and providing a bias current for the bandgap amplifier; the band-gap amplifier is used for adjusting the grid voltage of the power tube contained in the band-gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable; and an output circuit for outputting a stable set voltage.
Description
Technical Field
The invention belongs to the field of circuit design, and particularly relates to an LDO circuit with an automatic temperature compensation function, a working method and a power supply.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
In the power supply IC, an important development branch is a DC-DC converter. The DC-DC converter converts an input direct current voltage into another direct current voltage with stable output. It is realized by adjusting the internal resistance according to load variation, sometimes called a direct current chopper. The DC-DC converters can be roughly classified into two kinds of linear voltage regulators and switching voltage regulators according to the operation mode of the transmission power tube. The switching regulator is a discrete system, and the power tube inside the switching regulator works in a high-frequency switching state, so that the on-resistance is small. When larger current passes through, the power consumed on the power tube is small, and the power efficiency is high and can reach more than 85%. Sometimes referred to as a "high efficiency energy efficient power supply". The current voltage regulator has become a mainstream product, but the large switching noise is a fatal disadvantage, and the application in the fields of low noise, low ripple simulation and radio frequency is greatly limited. Whereas linear voltage regulation is the opposite, it is a continuous system. The power tube has the advantages of low efficiency, large heating value of the power tube and output always smaller than input, but has good linear adjustment rate, load adjustment rate, high power supply rejection ratio and low noise, and can just make up the defects of the switching type voltage stabilizer. Linear voltage regulators are also widely used in electronic devices with high noise and ripple requirements due to their low ripple voltage. However, its inefficiency brings it with it a number of inconveniences.
Low-dropout (LDO) linear voltage regulator has become the first choice for power management in mobile electronic devices such as mobile communication terminals, portable computers, personal Digital Assistants (PDAs) and the like due to its simple structure, low cost, low noise, low power consumption, and small package size. LDO voltage stabilizer generally works at-20-80 ℃, but in applications such as automobile electronics and environment detection, the LDO voltage stabilizer is required to stably provide power for an electronic system in a wider temperature range (-40-130 ℃).
The inventors have found that since Metal Oxide Semiconductor (MOS) devices in LDO circuits are severely leaky at high temperatures, this affects the operational stability of LDO circuits in high temperature environments.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides an LDO circuit with an automatic temperature compensation function, a working method and a power supply, which can enable the LDO circuit to stably operate under high temperature conditions and are particularly suitable for operation under severe environments and under the condition of large load variation.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a first aspect of the present invention provides an LDO circuit with an automatic temperature compensation function, comprising:
a soft start circuit including a high temperature leakage current compensation circuit; the soft start circuit is used for electrifying the input voltage to a voltage threshold value in a soft start mode and preventing the band gap amplifier from being turned off by mistake when the input voltage reaches a set high temperature;
a bias circuit for starting operation when the input voltage is powered up to a set voltage threshold and providing a bias current for the bandgap amplifier;
the band-gap amplifier is used for adjusting the grid voltage of the power tube contained in the band-gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable;
and an output circuit for outputting a stable set voltage.
As one implementation mode, the soft start circuit comprises a current mirror, a high-temperature leakage current compensation circuit, a first triode and a start capacitor; one end of the starting capacitor is connected with the base electrode of the first triode, and the other end of the starting capacitor is connected with the positive electrode of the current source; the other end of the starting capacitor and the negative electrode of the current source are respectively connected with the drains of the two power switching tubes of the current mirror; one end of the high-temperature leakage current compensation circuit is connected with two sources of the current mirror, and the other end of the high-temperature leakage current compensation circuit is connected with the cathode of the current source.
As an implementation mode, the high-temperature leakage current compensation circuit comprises two N-type power switching tubes and four P-type power switching tubes, wherein the first N-type power switching tube and the second N-type power switching tube are connected in series, the source electrode of the first N-type power switching tube and the grid electrode of the second N-type power switching tube are connected with the negative electrode of a current source, the first P-type power switching tube and the second P-type power switching tube are oppositely arranged and are directly connected with each other, and the third P-type power switching tube and the fourth P-type power switching tube are oppositely arranged and are directly connected with each other; the grid electrode of the first P type power switch tube is connected with the drain electrode and the drain electrode of the first N type power switch tube, the drain electrode of the second P type power switch tube is respectively connected with the drain electrode of the second N type power switch tube and the drain electrode of the fourth P type power switch tube, and the drain electrode of the third P type power switch tube is connected with the emitter electrode of the first triode.
As an implementation mode, the second N-type power switch tube is connected in parallel with the starting capacitor and is used for controlling the return signal when in short circuit.
As one embodiment, the bias circuit comprises a bias voltage source, a bias current source and a third N-type power switch tube, wherein the bias current source and the third N-type power switch tube are connected in series and then connected in parallel with the bias voltage source.
As one embodiment, the bandgap amplifier includes a PMOS current mirror, an NPN differential pair, and an NMOS buffer follower, the PMOS current mirror being a load of the NPN differential pair for driving the NMOS buffer follower.
As an implementation mode, the band gap amplifier further comprises a fourth N-type power switch tube, a fifth N-type power switch tube, a sixth N-type power switch tube and an N-channel buffer which are connected in series, wherein a grid electrode of the N-channel buffer is connected with a collector electrode of one NPN type triode in the NPN type differential pair, a source electrode of the N-channel buffer is connected with a drain electrode of the fourth N-type power switch tube, and a drain electrode of the N-channel buffer is connected with a grid electrode of the PMOS current mirror.
As an implementation manner, the output circuit includes a fifth P-type power switch tube and an RC network connected in series with the fifth P-type power switch tube, where the RC network includes five branches connected in parallel, the first branch is a divided voltage formed by two resistors, the second branch is connected in series with a capacitor, the third branch is an RC serial branch, the fourth branch is also connected in series with a capacitor, and the fifth branch is connected in series with an output resistor.
A second aspect of the present invention provides an operation method of an LDO circuit based on the built-in automatic temperature compensation function as described above, comprising:
the soft start circuit is utilized to electrify the input voltage to a voltage threshold value in a soft start mode, and the band gap amplifier is prevented from being turned off by mistake when the set high temperature is reached;
when the input voltage is powered up to a set voltage threshold, the bias circuit starts to work and provides bias current for the band gap amplifier;
the band gap amplifier adjusts the grid voltage of the power tube contained in the band gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable;
and finally, outputting stable set voltage by an output circuit.
A third aspect of the invention provides a power supply comprising an LDO circuit with built-in automatic temperature compensation function as described above.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides an LDO circuit with an internal automatic temperature compensation function, which relates to a high-temperature leakage current compensation circuit in a soft start circuit, wherein an input voltage is electrified to a voltage threshold value in a soft start mode to start a bias circuit, and the automatic temperature compensation can be realized by preventing a band gap amplifier from being switched off by mistake when the set high temperature is reached, so that the stable operation under the high temperature condition is realized, the LDO circuit is particularly suitable for operation under the severe environment and under the condition of large load change, and meanwhile, the stability of output voltage is improved.
The invention discloses an LDO circuit with an automatic temperature compensation function, which is designed to be an output circuit, wherein the output circuit is composed of a fifth P-type power switch tube and an RC network connected with the fifth P-type power switch tube in series, the RC network comprises five branches connected in parallel, the first branch is divided voltage composed of two resistors, the second branch is connected with a capacitor in series, the third branch is an RC series branch, the fourth branch is also connected with a capacitor in series, the fifth branch is connected with an output resistor in series, the low-frequency main pole point is enabled to be positioned at an output end, more in-phase zero points are introduced to offset the influence of parasitic poles, and avalanche effects caused by phase offset of other poles are restrained.
Additional aspects of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention.
FIG. 1 is a schematic diagram of an LDO circuit with an automatic temperature compensation function built in according to an embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present invention. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
Term interpretation:
LDO, i.e. low dropout linear regulator.
PMOS, P-channel metal-oxide-semiconductor.
The performance of a linear voltage regulator is generally attributed to 3 indicators: accuracy, power conversion efficiency and usage requirements. Precision refers to the ability of a voltage regulator to maintain and stabilize the output voltage within a small range of its target value under all possible operating conditions. The power conversion efficiency describes how much energy drawn from the input power source can reach the load. The operating limits of the input voltage, the output capacitance, the equivalent series resistance of the output capacitance and the load current define the working environment in which the voltage regulator can normally work within the index range.
Output accuracy includes adverse effects caused by non-idealities in the manufacturing process, and non-idealities in the circuit's ability to respond to temperature, supply and load current variations. The process and temperature can produce permanent steady state disturbances to the output, the input and load can slowly change the output, and the output can be interrupted instantaneously, the latter, unfortunately, often having a greater impact than the former. Deep knowledge of each mechanism affecting the output can better manage and distribute circuit redundancy during the design process. It is the overall accuracy that ultimately determines the specification of a voltage regulator, which represents the additive impact of all variations.
The most basic precision error of a voltage stabilizer is from the initial offset voltage of an integrated circuit caused by manufacturing process fluctuation, and the source of the initial offset voltage is reference voltage v REF Error of (v), reference voltage v REF Is used to generate an output target voltage; system pair v OUT The sensitivity of the fluctuations ultimately depends on the sensing v OUT And control S 0 Is provided. If there is an infinite loop gain, v FB Will match v REF But because the gain is limited, v FB Cannot be exactly equal to v REF Thereby generating a gain error; due to the effect of negative feedback, reference v REF Any change in (2) will pass through the equivalent closed loop gain A of the system CL Output v delivered to a voltage regulator OUT . Thus, v introduced by temperature REF Drift of (c) causes v OUT Is a variation of (c). The temperature drift causes the input reference voltage of the error amplifier in the voltage regulator to vary with temperature; the linear adjustment rate is a steady state metric representing the change in output voltage caused by a slow and significant change in input supply voltage. In other words, line refers to the input power of the regulator, and linear regulation refers to the steady-state gain of the regulator from input to output; power Supply Ripple Rejection (PSRR) indicates v OUT Time-dependent, i.e. frequency-dependent, changes at low frequencies with power supply gain A IN0 Reciprocal; by load current i LOAD The output voltage variation caused by the steady state variation of (a) is defined as the load regulation rate;
the basic function of a voltage regulator is to regulate power and transfer energy from a power supply to an electronic load. In this regard, accuracy is an indicator of the regulation performance of the regulator, while the power conversion efficiency indicates how much energy can reach the load, which ideally receives all the energy from the power supply, however, the power transistor S 0 And error amplifier A EA And the feedback controller consumes power P in the form of heat dissipation LOSS . Thus, the power conversion efficiency is the ratio of output power to input power, always less than 100%.
The invention provides an LDO circuit with an automatic temperature compensation function, which belongs to output end compensation and refers to the fact that a low-frequency main polar point is positioned at an output end. This typically occurs in high power systems where the load is suddenly so large that a large output capacitance is required. Without other poles and zeros, the gain is 20dB per frequency10 octaves down so gain bandwidth product A LG0 p 0 At crossing the output pole p 0 The value is constant. In other words, if there is no other pole and zero interference, the low frequency gain A LG0 How much the main pole frequency p decreases 0 How much the rise, the unity gain frequency f 0dB Equal to p 0 A LG0 Or equivalent to GBW frequency f GBW 。
F with lowest bandwidth in worst case of system 0dB At this point, all parasitic poles still have to be at the highest f possible 0dB Above, f is reduced 0dB Power consumption may be saved by having the maximum value of (a) in the minimum range, because the higher the parasitic pole frequency, the higher the quiescent current of the transistor is required.
In linear regulators, not every performance indicator is required to be independent of temperature, for example, the differential voltage does not necessarily need to be independent of temperature. Designing a circuit with excessive performance for achievement alone not only increases silicon area, power consumption and risk, but often does not have any necessity. Regardless of the specific application requirements, it is important to know the temperature dependence of the performance parameters in order to enable the designed circuit to function properly within standard or extended commercial temperature ranges (0-85 ℃ and-40-125 ℃).
Diode or base-emitter voltages, gate-source voltages, and zener diode voltages are all very useful zero order reference voltages because the voltages they produce at process corners are substantially predictable. However, in modern voltage regulator applications, zener voltages are less practical than base-emitter voltages and gate-source voltages due to their voltages up to 5-8V, as they are typically higher than the breakdown voltage of the process. Thus, adjusting the resistive voltage divider in parallel feedback via the power transistor with a base-emitter voltage or a gate-source voltage converts a very popular approach to designing a self-referenced voltage regulator that is not temperature independent.
Taking temperature independence into account increases the complexity of the circuit, although absolute temperature independence is not to be achieved. The simplest approach is to find a voltage or current that is not inherently temperature dependent, but which is not actually present. However, the gate-source voltage can be decomposed into a threshold voltage and a drain-source saturation voltage. The temperature independence of the circuit is increased, in a more general sense, by combining elements with complementary temperature effects to obtain a temperature independent module by counteracting the effects of temperature on the respective elements. The most practical approach is to find two voltages or currents that vary inversely with temperature, e.g., a PTAT voltage can cancel the effect of a CTAT voltage so that their sum hardly varies with temperature. The temperature characteristics of the two components making up the reference need not be linear to provide an almost constant output, so long as they cancel each other out the effects of temperature. Voltages or currents that do not vary with process corner, die-to-die, wafer-to-wafer, lot-to-lot variations are of paramount importance, as better tolerance performance is ultimately more important than having a benchmark of temperature independence and predictability that is considered to be highly accurate.
The PN junction voltage generally decreases with increasing temperature at a rate of about-2.2 mV/. Degree.C. Because its linear portion is much larger than its higher order term, the diode voltage is often complementary to the PTAT voltage, which is why it is known as CTAT with temperature complementary characteristics, the compensated reference voltage v REF Is flat over most of the temperature range. Using v PTAT And v CTAT The cancellation of the first order components to achieve the temperature independent reference is referred to as first order temperature compensation.
Bandgap references are a very popular circuit whose core is to compensate for the inherent CTAT characteristic of a diode voltage or base-emitter voltage with a PTAT voltage, named bandgap because the zero order temperature term of the diode voltage is the bandgap voltage of silicon, which is also why the diode voltage is 1.2V at absolute zero degrees. In addition, more importantly, because the PTAT voltage used to compensate the diode voltage or the base-emitter voltage has no zero order term, i.e., the PTAT voltage is equal to zero at absolute zero degrees, the reference voltage only remains the diode voltage after cancellation of the first and higher order componentsThe zero order component, the bandgap circuit also produces a reference voltage of approximately only 1.2V. In general, the same principle applies to the current generated by the diode and PTAT voltages, except that the bandgap voltage at this time is converted to a current defined by a resistor by trans-impedance conversion. Similarly, the diode voltage and the PTAT voltage in combination in proportion may produce a reference voltage that is much less than a 1.2V bandgap voltage, which may be in the range of 0.2-1V. Whatever the ratio and in whatever circuit combination is implemented, any use of diode voltage and PTAT voltage to generate the reference voltage follows the bandgap approach, even when applied to the core of a voltage regulator. Input voltage v IN Output voltage v OUT Output capacitance C 0 、C 0 Or R ESR Output current i O Or load current i LOAD The range of values of (c) may describe the operational limits of the voltage regulator.
In order to improve the efficiency of portable equipment and prolong the working time of a battery, a large output capacitor is used in combination with low static current and low input voltage and in order to improve the abrupt load response, and the LDO circuit with the built-in automatic temperature compensation function provided by the invention uses an output end compensation PMOS solution to realize LDO.
The LDO circuit with the built-in automatic temperature compensation function and the working principle thereof are described in detail below with reference to specific circuit schematic diagrams:
example 1
Referring to fig. 1, the present embodiment provides an LDO circuit with an automatic temperature compensation function, which includes: soft start circuit, bias circuit, band gap amplifier and output circuit.
Wherein:
(1) A soft start circuit including a high temperature leakage current compensation circuit; the soft start circuit is used for powering up the input voltage to a voltage threshold value in a soft start mode and preventing the band gap amplifier from being turned off by mistake when the set high temperature is reached.
As shown in fig. 1, the soft start circuit includes a current mirror, a high-temperature leakage current compensation circuit, a first triode QS and a start capacitor CS; one end of the starting capacitor CS is connected with the base electrode of the first triode QS, and the other end of the starting capacitor CS is connected with the positive electrode of the current source I13; the other end of the starting capacitor CS and the negative electrode of the current source I13 are respectively connected with the drains of the two power switching tubes of the current mirror; one end of the high-temperature leakage current compensation circuit is connected with two sources of the current mirror, and the other end of the high-temperature leakage current compensation circuit is connected with the cathode of the current source I13.
Specifically, the high-temperature leakage current compensation circuit comprises two N-type power switching tubes and four P-type power switching tubes, wherein a first N-type power switching tube MS1 and a second N-type power switching tube MS2 are connected in series, a source electrode of the first N-type power switching tube MS1 and a grid electrode of the second N-type power switching tube MS2 are both connected with a negative electrode of a current source, a first P-type power switching tube MS3 and a second P-type power switching tube MS4 are oppositely arranged, the grid electrodes are directly connected, and a third P-type power switching tube MB5 and a fourth P-type power switching tube MB6 are oppositely arranged and the grid electrodes are directly connected; the grid electrode of the first P-type power switch tube MS3 is connected with the drain electrode and the drain electrode of the first N-type power switch tube MS1, the drain electrode of the second P-type power switch tube MS4 is respectively connected with the drain electrode of the second N-type power switch tube MS2 and the drain electrode of the fourth P-type power switch tube MB6, and the drain electrode of the third P-type power switch tube MB5 is connected with the emitter electrode of the first triode QS.
In this embodiment, the second N-type power switch tube MS2 is connected in parallel with the start capacitor CS, and is used for controlling the return signal during short circuit.
The soft start circuit of this embodiment can normally operate at-40-150deg.C, as shown in FIG. 1, M S2 A switching tube for controlling a return signal when short-circuited; m is M S1 ～M S4 And M B5 、M B6 Is a high-temperature leakage current compensation circuit. The basic principle is as follows: when the input voltage V DD When the voltage is electrified to be more than 2V, the current BIAS circuit BIAS starts to work and provides BIAS current I for the error amplifier BS At this time M S5 Handle M S6 Current I in (a) BS Replication into I S3 And make triode Q S Conduction, base current I B Start to C S And (5) charging.
(2) And the bias circuit is used for starting to work when the input voltage is powered up to a set voltage threshold value and providing bias current for the band gap amplifier.
As shown in fig. 1, the bias circuit includes a bias voltage source V1, a bias current source I11, and a third N-type power switching tube NM5, where the bias current source I11 and the third N-type power switching tube NM5 are connected in series and then connected in parallel with the bias voltage source V1.
Since the bias current greatly affects the performance of the error amplifier, the replication accuracy of the current mirror is severely affected by temperature, and in order to prevent the bias current from drifting at high temperature, high temperature compensation tubes (MB 1 to MB6 in fig. 1) are added to each bias tube of the error amplifier. These transistors can be regarded as reversely connected diodes, and at high temperature, the reverse leakage current is increased to offset the offset of the bias current caused by the temperature rise, so that the error amplifier can still work normally under extremely small bias current and extremely high temperature.
(3) The band gap amplifier is used for adjusting the grid voltage of the power tube contained in the band gap amplifier to enable the power tube to be conducted and start to supply current to a load until the output voltage of the LDO circuit is stable.
As shown in fig. 1, the bandgap amplifier includes a PMOS current mirror, an NPN differential pair, and an NMOS buffer follower NM1, the PMOS current mirror being a load of the NPN differential pair for driving the NMOS buffer follower NM1.
The NPN differential pair comprises a triode Q2 and a triode Q4. The PMOS current mirror includes a power switch tube PM2 and a power switch tube PM0.
In a specific implementation, the bandgap amplifier further includes a fourth N-type power switching tube NM3, a fifth N-type power switching tube NM4, a sixth N-type power switching tube NM5, and an N-channel buffer NM0, where a gate of the N-channel buffer NM0 is connected to a collector of one NPN transistor Q2 in the NPN differential pair, a source of the N-channel buffer NM0 is connected to a drain of the fourth N-type power switching tube NM3, and a drain of the N-channel buffer NM0 is connected to a gate of the PMOS current mirror.
The current mirror loads PM2-PM0 typically produce a pair of pole-zero pairs that are located very close together so that their co-action has no significant effect on the phase margin. The level shift follower NM0 and the mirror transistor PM2 constituteA negative feedback loop, which must be stable. There are two poles in this loop: high frequency pole p at NM0 source G3 And a low frequency pole p of a set bandwidth at the PM2 drain D3 . Thus, pole p D3 Must be high enough to guarantee the closed loop bandwidth p of the current mirror M Slightly higher than f 0dB(MAX) . To ensure the stability of the current mirror loop, the pole p of the gate of NM0 D3 Must be dominant pole, and p G3 Must be within the closed loop bandwidth p M Nearby. The drain capacitance of PM2 shunts the parallel resistor to form pole p D3 Far below p G3 Therefore C GSNM0 Also the gate load of PM 2. The combined action of the whole loop is achieved by p D3 The feedback conversion of (2) produces the current mirror pole p of the system M When from Q D2 When the input small signal is not absorbed by the current mirror load PM0, the current mirror generates a position of about 2p M Zero z of (2) M This helps to reduce the impact of avalanche effects generated adjacent poles.
(4) And an output circuit for outputting a stable set voltage.
In a specific implementation, the output circuit includes a fifth P-type power switch tube PM1 and an RC network connected in series with the fifth P-type power switch tube PM1, where the RC network includes five branches connected in parallel, the first branch is a divided voltage formed by two resistors R6 and R7, the second branch is connected in series with a capacitor C1, the third branch is an RC serial branch, the RC serial branch is formed by connecting R5 and C2 in series, the fourth branch is also connected in series with a capacitor C3, and the fifth branch is connected in series with an output resistor R0.
The invention adopts the PMOS voltage stabilizer with the compensation of the output end to lead the output pole p 0 Is the dominant pole of low frequency. In practice, the frequency passes through the principal pole point p when the other poles and zeros remain at higher frequencies under all temperatures, process angles and operating conditions 0 The loop gain will then decrease linearly with increasing frequency in a single-pole roll-off fashion. Thus, when the low frequency loop gain A LG0 When 1 is reached, f is set approximately 0dB I.e. the gain-bandwidth product.
Set-up error amplifier A E Requires a high resistance node v for gain OE Thus, the pole p associated with this node OE Typically the second dominant pole of the system. Although the output capacitance C 0 Is equivalent to the series resistance R ESR Possibly at p OE Zero z, near which phase margin is introduced ESR However, R is ESR With process angle and temperature, z is very variable ESR Will also vary greatly with process angle and temperature. Thus p is OE Far away from f 0dB(MIN) The following period z ESR Can counteract p OE Is risky but such that f 0dB(MAX) In all cases less than z ESR(MIN) It is too conservative. So that the second dominant pole p OE At f 0dB(MIN) Nearby, but always well below f 0dB(MAX) . To make p OE At f 0dB(MIN) Nearby, v OE The resistance at this point must be relatively low, which is why the channel lengths of mirror devices PM2 and PM0 are relatively short, because the channel length modulation effect will result in a lower output resistance for short channel devices.
As the frequency increases, the next pole appears to be at the gate v of PM1 B Buffer pole p at OB Due to the absence of z ESR In the case of (1), p 0 And p OE Has produced a large phase shift, p OB Must be much higher than f 0dB(MIN) But not necessarily higher than f 0dB(MAX) . Due to z ESR Is f 0dB Move to f 0dB(MAX) Mainly due to z ESR Can counteract p 0 The function of (2) is p OB At f 0dB(MAX) The phase change caused by the vicinity leaves a margin.
At p OB After the frequency, the system is not designed to include the frequency at v FB The feedback pole p of (2) FB 、C B The bypass pole p of (2) B And mirror pole p M All the remaining parasitic poles in the interior leave a phase margin so that they must all have a frequency much higher than f 0dB(MAX) . Maintaining the parasitic pole at high frequency requires additional quiescent current to be consumed in order toMaintain stability, place them only slightly above f 0dB(MAX) . Although higher than f 0dB(MAX) The effect of a single pole of 10 octaves on the phase margin is small, but the combined effect of multiple poles on f 0dB The effect of nearby feedback loop phase shifts may be as common as the avalanche effect. Phase margin at f 0dB Rapid deterioration in the vicinity means that process deviations and temperature variations are more likely to disrupt the stability of the system, since small movements of the pole-zero position will cause large variations in the phase margin. This means that the circuit may be in an unstable state under certain conditions, causing the circuit to oscillate when turned on or the load changes rapidly.
The in-phase zero (i.e., the left half-plane zero) may restore some phase margin, thereby suppressing avalanche effects from other pole phase shifts. Therefore, parasitic pole needs to be placed at f 0dB(MAX) At the position of 10 octaves, more in-phase zero points can be introduced to counteract the influence of parasitic poles. The feedforward capacitor C1 in fig. 1 starts to shunt the feedback resistor R6 at 1/2 pi R6C1 frequency, thereby generating a zero z1 that can improve the phase margin. At f 0dB(MAX) A zero z is produced in the following frequency range ESR Will cause f 0dB(MAX) Closer to the parasitic pole, which can make the effect of the parasitic pole on the phase margin more severe. Zero z1 is set below f to prevent process variations and temperature variations 0dB(MAX) Is usually designed to be slightly higher than f 0dB(MAX) Is a position of (c).
C B For C 0 R of (2) ESR The parallel effect of (a) will generate a pole p B . The maximum value of the bypass capacitance is less than C B(MAX) In position p B At f 0dB(MAX) At 10 octaves. At the feedback node v FB The capacitance of the feedback resistor R6 and the feedback resistor R7 in parallel limits the magnitude of the parallel resistor, because the pole generated by the capacitance and the parallel resistor formed by R6 and R7 must be 10 times f 0dB(MAX) Above.
The outstanding advantage of the output-side compensation voltage stabilizer is that the output-side compensation voltage stabilizer has a large output capacitance C 0 And a large error amplifier bandwidth p E . Large output capacitance C 0 The ability of the voltage regulator to suppress the effects of a wide range of fast high power load transients can be enhanced. High p E The benefits of parallel feedback to PSR can be extended to higher frequencies. The most fundamental challenge here is to guarantee p E Higher than the system bandwidth f 0dB To avoid unstable conditions of feedback, the difficulty is firstly that the high gain is achieved by a medium transconductance current flowing through a large resistor, and for large resistors the capacitance will start to shunt at lower frequencies, and secondly that the power-on transistor is typically large, so it provides a large load capacitance to the output resistor of the error amplifier, causing the poles they produce to lie at low frequencies.
ESR zero z ESR Provide a phase margin, in practice z ESR Is unpredictable and thus unreliable. The reason is ESR resistance R ESR The range of variation with temperature and process can be as high as + -50% - + -100%, and the characteristic data of ESR is often unreliable, so that simulation models are often inaccurate. Thus z ESR May be located within the bandwidth of the voltage regulator or may be outside the bandwidth. To maintain stable system conditions, it is common practice to establish a low frequency main pole and place the second pole at unity gain frequency f 0dB Nearby. In a linear voltage regulator, the two poles are the output pole p 0 And error amplifier pole p E . After determining which pole should be the dominant pole, the purpose of the compensation is to understand all possible disturbances in the system and to ensure that the loop is at f 0dB The phase shift at the position is not more than 140 DEG under the change of temperature and process angle, and further, the frequency f when the phase shift of the system reaches 180 DEG is ensured 180° Distance f 0dB 10 octaves away, which helps to avoid transient instability when the system is restarted after a first start or sleep.
The power efficiency and accuracy are error amplifier a E Key parameters in the design. First, and power transistor S 0 And buffer A B Similarly, A E The most basic requirement is that at very low supply voltages v IN At this time through S 0 Is very low, A E Can still work normally and the static working current i Q Low in order to improve power efficiency and prolong the service life of the battery. A is that E It must also be able to respond quickly to suppress load transients and supply ripple to adjust the output signal v 0 Is a negative influence of (2). Furthermore, steady-state accuracy parameters such as load adjustment rate, linear adjustment rate and initial accuracy depend on the reference voltage v REF And error amplifier A E Performance of A E The gain of (a) must be high but not so high as to affect the stability of the circuit. The systematic and random input reference offset voltage Vos must also be low. From the system, A E The output stage of (a) must also take into account a B Current and drive voltage requirements of (a). In sum, A E Should have a low v IN(MIN Low i Q High bandwidth, high power supply rejection ratio, high gain and low offset, and its output v OE Must be identical to A B Is adapted to the driving capability requirements of the vehicle.
In this embodiment, the PMOS current mirrors PM2-PM0 are used as the loads of the NPN differential pairs Q2-Q4 to drive an NMOS buffer follower NM1, and then the PMOS power switching transistor PM1 is controlled by this buffer. N-channel buffer NM0 diode connects PM2, thereby connecting the source-gate voltage v of PM1 SG0 And gate-source voltage v of NM1 GSNM1 Source-drain voltage v for PM0 SD0 V of the total influence of (2) with PM2 SG2 V of and NM0 GSNM0 V for PM2 SD2 The first order matching is the total effect of (a) to minimize the system mismatch caused by the voltage mismatch on the current mirror. Capacitor C1 is used to couple v 0 Is fed forward to the feedback node v FB On this, this introduces an in-phase zero (i.e. left half plane zero) z FF The phase margin is improved around the system unity gain. The input differential pairs employ BJTs because they generally match better than MOSFETs, resulting in lower input reference offset.
Example two
The working principle of the LDO circuit with the built-in automatic temperature compensation function according to the first embodiment is as follows:
the soft start circuit is utilized to electrify the input voltage to a voltage threshold value in a soft start mode, and the band gap amplifier is prevented from being turned off by mistake when the set high temperature is reached;
when the input voltage is powered up to a set voltage threshold, the bias circuit starts to work and provides bias current for the band gap amplifier;
the band gap amplifier adjusts the grid voltage of the power tube contained in the band gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable;
and finally, outputting stable set voltage by an output circuit.
Example III
The present embodiment provides a power supply, which includes the LDO circuit with built-in automatic temperature compensation function as described in the first embodiment.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. An LDO circuit with an automatic temperature compensation function, comprising:
a soft start circuit including a high temperature leakage current compensation circuit; the soft start circuit is used for electrifying the input voltage to a voltage threshold value in a soft start mode and preventing the band gap amplifier from being turned off by mistake when the input voltage reaches a set high temperature;
a bias circuit for starting operation when the input voltage is powered up to a set voltage threshold and providing a bias current for the bandgap amplifier;
the band-gap amplifier is used for adjusting the grid voltage of the power tube contained in the band-gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable;
an output circuit for outputting a stable set voltage;
the soft start circuit comprises a current mirror, a high-temperature leakage current compensation circuit, a first triode and a start capacitor; one end of the starting capacitor is connected with the base electrode of the first triode, and the other end of the starting capacitor is grounded; the grid electrodes of the two power switching tubes of the current mirror are connected with the drain electrode of the power switching tube PMS6 of the current mirror, and the drain electrode of the PMS6 is connected with the positive electrode of the current source; the sources of the two power switching tubes of the current mirror are connected with a power supply; the emitter of the first triode is connected with the drain electrode of a power switch tube PMS5 of the current mirror, and the collector of the first triode is grounded;
the high-temperature leakage current compensation circuit comprises two N-type power switching tubes and four P-type power switching tubes, wherein the first N-type power switching tube and the second N-type power switching tube are connected in series, the source electrode of the first N-type power switching tube and the grid electrode of the second N-type power switching tube are both connected with the negative electrode of a current source, the grid electrode of the first N-type power switching tube is connected with the drain electrode of the second N-type power switching tube, and the source electrode of the second N-type power switching tube is grounded; the first P-type power switch tube and the second P-type power switch tube are oppositely arranged, the grid electrodes are directly connected, the source electrodes of the first P-type power switch tube and the second P-type power switch tube are connected with a power supply, the third P-type power switch tube and the fourth P-type power switch tube are oppositely arranged, the grid electrodes are directly connected, and the source electrodes of the third P-type power switch tube and the fourth P-type power switch tube are connected with the power supply; the grid electrode of the first P type power switch tube is connected with the drain electrode, and is connected with the drain electrode of the first N type power switch tube, the drain electrode of the second P type power switch tube is respectively connected with the drain electrode of the second N type power switch tube and the drain electrode of the fourth P type power switch tube, and the drain electrode of the third P type power switch tube is connected with the emitter electrode of the first triode;
the second N-type power switch tube is connected with the starting capacitor in parallel and is used for controlling a return signal when in short circuit;
the bias circuit comprises a bias voltage source, a bias current source and a third N-type power switching tube, wherein the bias current source and the third N-type power switching tube are connected in series and then connected with the bias voltage source in parallel;
the band gap amplifier comprises a PMOS current mirror, an NPN differential pair and an NMOS buffer follower, wherein the PMOS current mirror is a load of the NPN differential pair and is used for driving the NMOS buffer follower;
the band gap amplifier further comprises a fourth N-type power switch tube, a fifth N-type power switch tube, a sixth N-type power switch tube, a first N-channel buffer and a second N-channel buffer which are connected in series, wherein the sources of the two P-type power switch tubes of the PMOS current mirror are connected with a power supply, the grid electrodes of the two P-type power switch tubes are mutually connected and connected with the source electrode of the first N-channel buffer, the grid electrode of the first N-channel buffer is connected with the collector electrode of a first NPN-type triode in the NPN-type differential pair and is connected with the drain electrode of the first P-type power switch tube of the PMOS current mirror, the base electrode of the first NPN-type triode is connected with the voltage division node of the output voltage division resistor, the base electrode of the second NPN-type triode is connected with the output of the band gap reference circuit, the collector electrode of the second NPN-type power switch tube is connected with the drain electrode of the current mirror, the source electrode of the first N-type power switch tube is connected with the drain electrode of the fourth N-type power switch tube, the drain electrode of the fifth N-type power switch tube is connected with the drain electrode of the second NPN-type power switch tube, the drain electrode of the fifth N-type triode is connected with the drain electrode of the second NPN-type power switch tube, the grid electrode of the second NPN-type triode is connected with the second N-type power switch tube is connected with the drain electrode of the second NPN-type power switch tube, the second NPN-type triode is connected with the grid electrode of the second NPN-type power switch tube is connected with the N-type power transistor, the grid electrode of the second NPN-type power switch is connected with the N-type power transistor is connected with the N-type power transistor connected with the second N-type power switch resistor voltage resistor connected with the N-type power switch resistor voltage resistor;
the output circuit comprises a fifth P-type power switch tube and an RC network connected in series with the fifth P-type power switch tube, wherein the RC network comprises five branches connected in parallel, the first branch is a voltage dividing circuit formed by two resistors, the second branch is connected in series with a capacitor, the third branch is an RC series branch, the fourth branch is also connected in series with a capacitor, and the fifth branch is connected in series with an output resistor.
2. An operating method of an LDO circuit based on the built-in automatic temperature compensation function according to claim 1, comprising:
the soft start circuit is utilized to electrify the input voltage to a voltage threshold value in a soft start mode, and the band gap amplifier is prevented from being turned off by mistake when the set high temperature is reached;
when the input voltage is powered up to a set voltage threshold, the bias circuit starts to work and provides bias current for the band gap amplifier;
the band gap amplifier adjusts the grid voltage of the power tube contained in the band gap amplifier to be conducted and starts to provide current for a load until the output voltage of the LDO circuit is stable;
finally, outputting stable set voltage by an output circuit;
the soft start circuit comprises a current mirror, a high-temperature leakage current compensation circuit, a first triode and a start capacitor; one end of the starting capacitor is connected with the base electrode of the first triode, and the other end of the starting capacitor is grounded; the grid electrodes of the two power switching tubes of the current mirror are connected with the drain electrode of the power switching tube PMS6 of the current mirror, and the drain electrode of the PMS6 is connected with the positive electrode of the current source; the sources of the two power switching tubes of the current mirror are connected with a power supply; the emitter of the first triode is connected with the drain electrode of a power switch tube PMS5 of the current mirror, and the collector of the first triode is grounded;
the high-temperature leakage current compensation circuit comprises two N-type power switching tubes and four P-type power switching tubes, wherein the first N-type power switching tube and the second N-type power switching tube are connected in series, the source electrode of the first N-type power switching tube and the grid electrode of the second N-type power switching tube are both connected with the negative electrode of a current source, the grid electrode of the first N-type power switching tube is connected with the drain electrode of the second N-type power switching tube, and the source electrode of the second N-type power switching tube is grounded; the first P-type power switch tube and the second P-type power switch tube are oppositely arranged, the grid electrodes are directly connected, the source electrodes of the first P-type power switch tube and the second P-type power switch tube are connected with a power supply, the third P-type power switch tube and the fourth P-type power switch tube are oppositely arranged, the grid electrodes are directly connected, and the source electrodes of the third P-type power switch tube and the fourth P-type power switch tube are connected with the power supply; the grid electrode of the first P type power switch tube is connected with the drain electrode, and is connected with the drain electrode of the first N type power switch tube, the drain electrode of the second P type power switch tube is respectively connected with the drain electrode of the second N type power switch tube and the drain electrode of the fourth P type power switch tube, and the drain electrode of the third P type power switch tube is connected with the emitter electrode of the first triode;
the second N-type power switch tube is connected with the starting capacitor in parallel and is used for controlling a return signal when in short circuit;
the bias circuit comprises a bias voltage source, a bias current source and a third N-type power switching tube, wherein the bias current source and the third N-type power switching tube are connected in series and then connected with the bias voltage source in parallel;
the band gap amplifier comprises a PMOS current mirror, an NPN differential pair and an NMOS buffer follower, wherein the PMOS current mirror is a load of the NPN differential pair and is used for driving the NMOS buffer follower;
the band gap amplifier further comprises a fourth N-type power switch tube, a fifth N-type power switch tube, a sixth N-type power switch tube, a first N-channel buffer and a second N-channel buffer which are connected in series, wherein the sources of the two P-type power switch tubes of the PMOS current mirror are connected with a power supply, the grid electrodes of the two P-type power switch tubes are mutually connected and connected with the source electrode of the first N-channel buffer, the grid electrode of the first N-channel buffer is connected with the collector electrode of a first NPN-type triode in the NPN-type differential pair and is connected with the drain electrode of the first P-type power switch tube of the PMOS current mirror, the base electrode of the first NPN-type triode is connected with the voltage division node of the output voltage division resistor, the base electrode of the second NPN-type triode is connected with the output of the band gap reference circuit, the collector electrode of the second NPN-type power switch tube is connected with the drain electrode of the current mirror, the source electrode of the first N-type power switch tube is connected with the drain electrode of the fourth N-type power switch tube, the drain electrode of the fifth N-type power switch tube is connected with the drain electrode of the second NPN-type power switch tube, the drain electrode of the fifth N-type triode is connected with the drain electrode of the second NPN-type power switch tube, the grid electrode of the second NPN-type triode is connected with the second N-type power switch tube is connected with the drain electrode of the second NPN-type power switch tube, the second NPN-type triode is connected with the grid electrode of the second NPN-type power switch tube is connected with the N-type power transistor, the grid electrode of the second NPN-type power switch is connected with the N-type power transistor is connected with the N-type power transistor connected with the second N-type power switch resistor voltage resistor connected with the N-type power switch resistor voltage resistor;
the output circuit comprises a fifth P-type power switch tube and an RC network connected in series with the fifth P-type power switch tube, wherein the RC network comprises five branches connected in parallel, the first branch is a voltage dividing circuit formed by two resistors, the second branch is connected in series with a capacitor, the third branch is an RC series branch, the fourth branch is also connected in series with a capacitor, and the fifth branch is connected in series with an output resistor.
3. A power supply comprising the LDO circuit with built-in automatic temperature compensation function according to claim 1.
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