CN114264800A - Method for manufacturing nanopore, nanopore structure and single nanopore sensor - Google Patents
Method for manufacturing nanopore, nanopore structure and single nanopore sensor Download PDFInfo
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- CN114264800A CN114264800A CN202111588323.3A CN202111588323A CN114264800A CN 114264800 A CN114264800 A CN 114264800A CN 202111588323 A CN202111588323 A CN 202111588323A CN 114264800 A CN114264800 A CN 114264800A
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Abstract
The invention discloses a method for manufacturing a nanopore, a nanopore structure and a single nanopore sensor, wherein the method for manufacturing the nanopore comprises the following steps: providing a silicon wafer; forming a first mask layer and a second mask layer; forming a first patterned layer including a first sub-groove; forming a second patterned layer; forming a first etching cavity; forming a second etching cavity; forming a metal layer; forming a third etching cavity to expose the metal layer at the cone tip; adding electrolyte solution into the first etching cavity, and adding electrochemical corrosion solution into the second etching cavity; and performing electrochemical corrosion on the metal layer at the conical tip to form the nano-hole. Thus, it is possible to facilitate the fabrication of a metal nanopore structure having an extremely small size by a relatively simple method.
Description
Technical Field
The present invention relates to the field of sensors, and in particular, to a method of fabricating a nanopore, a nanopore structure, and a single nanopore sensor.
Background
Solid state nanopores can be used to read and store data in biomolecules and in the field of molecular computing. In addition, solid state nanopores can be used in the fields of energy harvesting and power generation, DNA and protein sequencing, and liquid and gas filtration and purification. When the solid-state nanopore is used for detecting the biomolecule, the size of the molecular blocking current is not only related to the size of the nanopore, but also influenced by the property of the nanopore material. However, how to prepare metal nanopores with extremely small sizes in batches at low cost has become one of the key challenges in preparing metal nanopores at present.
Therefore, the current methods of fabricating nanopores, nanopore structures, and single nanopore sensors remain to be improved.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
In one aspect of the present invention, the present invention provides a method of fabricating a nanopore, comprising: providing a silicon wafer having a first main surface and a second main surface which are oppositely arranged; forming a first mask layer on the first main surface of the silicon wafer, and forming a second mask layer on the second main surface of the silicon wafer; performing first dry etching on the first mask layer to form a first patterning layer, wherein the first patterning layer comprises a first sub-groove; performing second dry etching on the second mask layer to form a second patterning layer, wherein the second patterning layer comprises a second sub-groove, and the orthographic projection of the first sub-groove on the silicon wafer is positioned inside the orthographic projection of the second sub-groove on the silicon wafer; performing first wet etching on the first sub-groove to form a first etching cavity, wherein the first etching cavity is of a conical structure, and the conical tip of the conical structure faces the second etching cavity; performing second wet etching on the second sub-groove to form a second etching cavity, wherein the first etching cavity is not communicated with the second etching cavity; forming a metal layer on the surface of one side of the first etching cavity, which is far away from the second etching cavity; carrying out third wet etching on the second etching cavity to form a third etching cavity so as to expose the metal layer positioned at the conical tip; adding electrolyte solution into the first etching cavity, and adding electrochemical corrosion solution into the second etching cavity; and performing electrochemical corrosion on the metal layer positioned at the conical tip to form the nanopore. Thus, it is possible to facilitate the fabrication of a metal nanopore structure having an extremely small size by a relatively simple method.
According to an embodiment of the present invention, the electrochemically etching the metal layer at the cone tip further comprises: the etching device is connected to a first circuit structure, the first circuit structure comprises a first power supply and an ammeter, the first power supply is connected with the ammeter in series, one of the positive pole and the negative pole of the first power supply is electrically connected with the first etching cavity, and the other of the positive pole and the negative pole of the first power supply is electrically connected with the third etching cavity; connecting a second circuit structure, wherein the second circuit structure comprises a second power supply and a grounding wire, one of the positive pole and the negative pole of the second power supply is electrically connected with the metal layer, the other of the positive pole and the negative pole of the second power supply is electrically connected with the third etching cavity, and the grounding wire is grounded; performing the electrochemical etching on the metal layer at the cone tip to form the nanopore. Thus, the nanopores may be formed by electrochemical etching.
According to an embodiment of the present invention, further comprising: a self-stop device coupled to the first etch chamber and the second circuit structure. Thus, the formation of nanopores can be further controlled.
According to an embodiment of the present invention, the electrolyte solution includes at least one of potassium chloride and sodium chloride. Thus, the metal layer can be protected conveniently.
According to an embodiment of the present invention, the electrochemical etching solution includes at least one of hydrochloric acid, nitric acid, sodium chloride, and potassium chloride. Therefore, the electrochemical corrosion of the metal layer material at the cone tip can be facilitated.
According to an embodiment of the present invention, the forming the first patterned layer further comprises: forming a first photoresist layer on one side of the first mask layer, which is far away from the silicon wafer, performing first patterning treatment on the first photoresist layer to expose part of the surface of the first mask layer, and performing first dry etching on the first mask layer to form the first patterning layer. Thus, the preparation of the first patterned layer having the first groove may be facilitated.
According to an embodiment of the present invention, the forming the second patterned layer further comprises: and forming a second photoresist layer on one side of the second mask layer, which is far away from the silicon wafer, performing second patterning treatment on the second photoresist layer to expose part of the surface of the second mask layer, and performing second dry etching on the second mask layer to form a second patterning layer. Thus, the preparation of the second patterned layer having the second grooves may be facilitated.
According to an embodiment of the present invention, a material forming the first mask layer and the second mask layer includes at least one of silicon nitride and silicon oxide. Thus, the preparation of the patterned layer can be facilitated.
According to an embodiment of the present invention, the first dry etching and the second dry etching are ICP. Thus, the first and second grooves can be formed easily and accurately. Thereby, the depth of the third etching chamber can be easily controlled.
According to the embodiment of the invention, the etching rate of the first wet etching is v1The etching rate of the second wet etching is v2，v1:v2(60-80): (5-15), thereby facilitating control of the depths of the first etching chamber and the second etching chamber.
According to the embodiment of the invention, the etching rate of the third wet etching is v3，v1:v3(60-80): (1-5). Thereby, the depth of the third etching chamber can be easily controlled.
According to the embodiment of the invention, the etching solution of the first wet etching, the etching solution of the second wet etching and the etching solution of the third wet etching are potassium hydroxide solutions. Thus, the control of the wet etching rate can be facilitated.
According to the embodiment of the invention, the depth of the first etching cavity is 3-5 microns in the thickness direction of the silicon wafer. Thus, the formation of the metal layer can be facilitated.
According to the embodiment of the invention, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns. Thereby, the cone tip structure can be conveniently exposed.
According to an embodiment of the present invention, a material forming the metal layer includes at least one of iron, aluminum, platinum, and titanium. Thus, formation of a nanopore of an extremely small size may be facilitated.
According to an embodiment of the present invention, the process of forming the metal layer includes at least one of electron beam evaporation and magnetron sputtering. Thus, the metal layer having the entire layer structure can be easily formed.
According to an embodiment of the invention, the pore size of the nanopore is 1-10 nm. Thus, a nanopore structure of extremely small pore size can be conveniently obtained.
In another aspect of the present invention, the present invention provides a nanopore structure, which is fabricated by the aforementioned method. Thus, the nanopore structure has all the features and advantages of the fabrication of the nanopore structure, which are not described herein.
In yet another aspect of the invention, the invention proposes a single nanopore sensor comprising the aforementioned nanopore structure. Thus, the single nanopore sensor has all the features and advantages of the nanopore structure described above, which are not described herein.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 shows a schematic flow diagram of a method of fabricating a nanopore according to one embodiment of the invention;
FIG. 2 shows a partial schematic flow diagram of a method of fabricating a nanopore according to yet another embodiment of the invention;
FIG. 3 shows a schematic flow diagram of a subsequent process for preparing a nanopore of the embodiment of FIG. 2;
FIG. 4 shows a partial flow diagram of a method of forming a first patterned layer according to one embodiment of the invention;
FIG. 5 is a schematic flow chart illustrating a subsequent process of the method of forming the first patterned layer of the embodiment of FIG. 4;
FIG. 6 shows a partial flow diagram of a method of forming a second patterned layer in accordance with one embodiment of the present invention;
FIG. 7 is a schematic flow chart illustrating a subsequent process of the method of forming the second patterned layer of the embodiment of FIG. 6;
fig. 8 shows a schematic structural diagram of a nanopore structure according to one embodiment of the invention.
Description of the drawings:
1: a first power supply; 2: a second power supply; 3: an ammeter; 4: a self-stop device; 10: a first photoresist layer; 11: a first mask plate; 20: a second photoresist layer; 21: a second mask plate; 100: a silicon wafer; 210: a first mask layer; 211: a first patterned layer; 220: a second mask layer; 221: a second patterned layer; 310: a first etching chamber; 320: a second etching cavity; 330: a third etching chamber; 400: a metal layer; 500: a nanopore.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The present application is based on the discovery by the inventors of the following technical problems:
in the related technology, the electrical property of the surface of the metal material is flexible and adjustable, so that the metal nano-hole has great potential in the field of biomolecule detection, and the method for preparing the silicon-based solid nano-hole by combining the anisotropic wet etching and the semiconductor MEMS process is widely applied due to low cost and high efficiency. In the application, the inventor finds that a taper cavity is formed on the front side of a silicon wafer by utilizing anisotropic wet etching, the silicon wafer is thinned by utilizing the wet etching on the back side until a taper structure is exposed, and finally, the extremely-small-aperture nanopore with controllable aperture can be formed by electrochemical corrosion.
In one aspect of the present invention, the present invention provides a method of fabricating a nanopore, and particularly, referring to fig. 1, the method of fabricating a nanopore including the steps of:
s10: providing a silicon wafer
According to some embodiments of the invention, a silicon wafer is provided at this step, the silicon wafer having a first major surface and a second major surface disposed opposite. The thickness of the silicon wafer is not particularly limited, and for example, the thickness of the silicon wafer may be 250-300 μm.
S20: forming a first mask layer on a first main surface of a silicon wafer, and forming a second mask layer on a second main surface of the silicon wafer
According to some embodiments of the present invention, referring to fig. 2 (a), the first mask layer 210 and the second mask layer 220 are formed at this step, and the material for forming the first mask layer and the second mask layer is not particularly limited as long as it does not undergo an etching reaction with an etching solution for wet etching a silicon wafer, for example, the material for forming the first mask layer and the second mask layer may include at least one of silicon nitride and silicon oxide.
S30: performing a first dry etching process on the first mask layer
According to some embodiments of the present invention, referring to fig. 2 (b), the first mask layer is subjected to a first dry etching at this step to form a first patterned layer 211, wherein the first patterned layer includes a first sub-recess, i.e., a recess formed by a region of the first mask layer etched away by the first dry etching. Therefore, in the subsequent wet etching process, anisotropic wet etching can be carried out along the first sub-groove to form a first etching cavity.
According to some embodiments of the invention, referring to fig. 4 and 5, forming the first patterned layer further comprises:
referring to (b) of fig. 4, a first photoresist layer 10 is formed on a side of the first mask layer 210 away from the silicon wafer 100.
Referring to fig. 4 (c), a first patterning process is performed on the first photoresist layer to expose a portion of the surface of the first mask layer, specifically, in this step, the first mask plate 11 may be used to shield an area that needs to be reserved on the first photoresist layer, so that an area corresponding to the first groove on the first photoresist layer is etched away through the light irradiation process, and a portion of the surface of the first mask layer 210 corresponding to the first groove is exposed.
Referring to (d) and (e) of fig. 5, the first patterned layer 211 is formed by performing a first dry etching on the first mask layer 210 at this step, wherein a first groove is formed in a region not blocked by the first mask plate during the first patterning process, that is, a position in the first patterned layer 211 where the original material of the first mask layer 210 is not present.
Referring to (f) of fig. 5, after the first patterned layer 211 is formed, the remaining first photoresist layer may be removed by a photo process, and in particular, the same conditions as the aforementioned first patterning process for the first photoresist layer may be applied, except that a mask plate is not required for the masking.
According to some embodiments of the present invention, the method of the first dry etching is not particularly limited, and for example, the first dry etching may be performed by using an inductively coupled plasma method.
S40: performing a second dry etching on the second mask layer
According to some embodiments of the present invention, referring to fig. 2 (b), the second mask layer is subjected to a second dry etching at this step to form a second patterned layer 221, wherein the second patterned layer 211 includes a second sub-groove, i.e., a groove formed in the second mask layer at a region etched away by the second dry etching. For example, the first sub-grooves may be coaxially disposed with the second sub-grooves, one first sub-groove corresponds to one second sub-groove, and the width of the first sub-groove is smaller than that of the second sub-groove. Therefore, in the subsequent wet etching process, anisotropic wet etching can be performed along the second sub-groove to form a second etching cavity.
According to some embodiments of the invention, forming the second patterned layer further comprises:
referring to (b) of fig. 6, a second photoresist layer 20 is formed on a side of the second mask layer 220 away from the silicon wafer 100.
Referring to fig. 6 (c), a second patterning process is performed on the second photoresist layer to expose a part of the surface of the second mask layer, specifically, in this step, the second mask plate 21 may be used to shield an area that needs to be reserved on the second photoresist layer, so that an area corresponding to the second groove on the second photoresist layer is etched away through the light irradiation process, and a part of the surface of the second mask layer 210 corresponding to the second groove is exposed.
Referring to (d) and (e) of fig. 7, the second mask layer 220 is subjected to a second dry etching process to form a second patterned layer 221 through this step. The second groove is formed in a region not shielded by the second mask plate during the second patterning process, that is, a position of the second patterning layer 221 not having the original material of the first mask layer 220 is the second groove.
Referring to (f) of fig. 7, after the second patterning layer 221 is formed, the remaining first photoresist layer may be removed through a photo process, and in particular, the same conditions as those for the aforementioned second patterning process on the second photoresist layer may be applied, except that a mask plate is not required for the masking.
According to some embodiments of the present invention, the method of the second dry etching is not particularly limited, and for example, the second dry etching may be performed by using an inductively coupled plasma method.
When it needs to be specifically stated, the forming sequence of the first patterned layer and the second patterned layer is not particularly limited, for example, the first mask layer and the second mask layer may be formed on the surfaces of both sides of the silicon wafer, and then the first mask layer is subjected to the first dry etching, and then the second mask layer is subjected to the second dry etching; or forming a first mask layer on one side surface of the silicon wafer, performing first dry etching on the first mask layer, forming a second mask layer on the other side surface of the silicon wafer, and performing second dry etching on the second mask layer. The selection can be made by those skilled in the art according to the actual situation.
S50: carrying out first wet etching on the first sub-groove
According to some embodiments of the present invention, referring to (c) of fig. 2, in this step, the first etching chamber 310 is formed by performing the first wet etching on the first sub-groove, and the structure of the first etching chamber 310 is not particularly limited as long as the structure exposed by the first etching chamber has a tip when the third etching chamber is formed by the third wet etching, for example, the first etching chamber 310 may be a tapered structure, and the tapered tip of the tapered structure faces the second etching chamber 320.
According to some embodiments of the present invention, the etching liquid of the first wet etching is not particularly limited, and for example, the etching liquid of the first wet etching may be a potassium hydroxide solution. The silicon wafer has anisotropy when being subjected to wet etching by adopting a potassium hydroxide solution, so that a first etching cavity with a conical structure is formed conveniently.
According to some embodiments of the present invention, the depth of the first etching cavity is not particularly limited, and for example, the depth of the first etching cavity may be 3 to 5 micrometers in the thickness direction of the silicon wafer. When the depth of the first etching cavity is within the range, etching liquid with lower concentration can be adopted for etching treatment, so that the etching depth of the first etching cavity can be conveniently regulated and controlled.
S60: performing second wet etching on the second sub-groove
According to some embodiments of the present invention, referring to fig. 2 (c), in this step, a second wet etching is performed on the second sub-groove to form a second etching cavity 320, wherein the first etching cavity 310 is not communicated with the second etching cavity 320, so that the metal layer with a tapered structure may be exposed by a subsequent third wet etching, and if the first etching cavity is communicated with the second etching cavity, the metal layer with a tapered structure may not be formed.
According to some embodiments of the invention, the etch rate v of the first wet etch is lower than the etch rate v of the second wet etch1And the etching rate v of the second wet etching2Is not particularly limited, e.g., v1:v2(60-80): (5-15). Therefore, the first etching cavity with the conical structure can be conveniently and quickly formed, the second etching cavity can be quickly formed, and the second etching cavity is not communicated with the second etching cavity through speed regulation.
According to some embodiments of the present invention, the concentration of the etching liquid of the second wet etching liquid is not particularly limited, for example, the concentration of the etching liquid of the second wet etching liquid may be the same as the concentration of the etching liquid of the first wet etching.
According to some embodiments of the present invention, the depth of the second etching chamber is not particularly limited, for example, when the sum of the height of the second etching chamber and the height of the first etching chamber is a and the thickness of the silicon wafer substrate is b, the difference of b-a should be not less than 5 μm. Namely, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns. Specifically, when the thickness of the silicon wafer is 300 microns, the depth of the second etching cavity can be 290 microns; when the thickness of the silicon wafer is 250 micrometers, the depth of the second etching cavity can be 240 micrometers. When the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns, the etching rate can be conveniently regulated and controlled during the subsequent third wet etching; when the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is less than 5 microns, the depth of the third etching cavity is not favorably controlled, the metal layer except the conical tip structure is easily exposed, and the formation of the nano-hole with smaller aperture is not favorably realized.
It should be noted that, the first wet etching and the second wet etching may be performed synchronously, or may be performed sequentially, for example, the first wet etching may be performed first, and then the second wet etching is performed, or the second wet etching may be performed first, and then the first wet etching is performed. The selection can be made by those skilled in the art according to the actual situation.
It should be particularly noted that the rate adjustment of the first wet etching and the second wet etching is not limited to the adjustment of the concentration of the etching solution, and the etching temperature and the etching time of the first wet etching and the second wet etching may also be adjusted to realize a structure in which the depth of the second etching cavity is larger and the depth of the first etching cavity is smaller.
S70: forming a metal layer on the surface of one side of the first etching cavity far away from the second etching cavity
According to some embodiments of the present invention, referring to (d) of fig. 2, a metal layer 400 is formed at a surface of the first etch chamber 310 on a side away from the second etch chamber 320 in this step. The material forming the metal layer is not particularly limited, and for example, the material forming the metal layer may include at least one of iron, aluminum, platinum, and titanium. The metal layer can be made of various materials, so that the surface electrical properties of the inner wall of the formed nano hole are different, and the inner wall of the formed nano hole has different physical and chemical properties correspondingly, so that the nano hole can be widely applied to the fields of semiconductors, integrated circuits, nano processing and the like.
According to some embodiments of the present invention, the process of forming the metal layer is not particularly limited as long as it can form the metal layer on a side surface of the first etching chamber away from the second etching chamber, and for example, the process of forming the metal layer may include at least one of electron beam evaporation and magnetron sputtering.
S80: performing third wet etching on the second etching cavity
According to some embodiments of the present invention, referring to (e) of fig. 3, the third etching cavity 330 is formed by a third wet etching at this step such that the depth of the second etching cavity is increased, thereby exposing the metal layer 400 at the taper tip.
According to some embodiments of the present invention, the concentration of the etching liquid of the third wet etching liquid is not particularly limited, for example, the concentration of the etching liquid of the third wet etching liquid may be the same as the concentration of the etching liquid of the second wet etching.
According to some embodiments of the invention, the etch rate v of the first wet etch is lower than the etch rate v of the second wet etch1Etching with third wet etchingRate of erosion v3Is not particularly limited, e.g., v1:v3(60-80): (1-5). Therefore, the third etching cavity can be formed conveniently and slowly, so that the metal layer at the conical tip is exposed slowly, and the metal layer which does not need to be etched subsequently is not exposed excessively.
S90: adding electrolyte solution into the first etching cavity, and adding electrochemical corrosion solution into the second etching cavity
According to some embodiments of the present invention, the kind of the electrolyte solution is not particularly limited, and for example, the electrolyte solution may include at least one of potassium chloride and sodium chloride. Therefore, when the conical tip of the metal layer is subjected to electrochemical corrosion, the structure of the metal layer close to one side of the first etching cavity is not corroded, so that the electrochemical corrosion is only carried out at the conical tip, and the pore size regulation and control of the formed nano-pore are facilitated to be improved.
According to some embodiments of the present invention, the kind of the electrochemical etching solution is not particularly limited as long as it can electrochemically etch the material of the metal layer under the energized condition, and for example, the electrochemical etching solution may include at least one of hydrochloric acid, nitric acid, sodium chloride, and potassium chloride, and specifically, the nitric acid may be a dilute nitric acid solution. Therefore, when a bias voltage is applied to the metal layer, electrochemical corrosion can be caused to occur on the metal material at the conical tip of the metal layer, and a nano-pore structure is generated.
It should be particularly noted that the adjustment of the rate of the third wet etching is not limited to the adjustment of the concentration of the etching solution, and the third etching chamber structure may also be formed by adjusting the etching temperature and the etching time of the third wet etching.
S100: electrochemical corrosion is carried out on the metal layer at the cone tip
According to some embodiments of the present invention, referring to (f) of fig. 3, electrochemically etching the metal layer 400 at the cone tip further includes:
the first circuit structure is connected, the first circuit structure comprises a first power supply 1 and an ammeter 3, the first power supply 1 is connected with the ammeter 3 in series, one of the positive pole and the negative pole of the first power supply 1 is electrically connected with the first etching cavity 310, and the other of the positive pole and the negative pole of the first power supply 1 is electrically connected with the third etching cavity 330. A second circuit structure is connected, the second circuit structure includes a second power supply 2 and a ground line, one of a positive electrode and a negative electrode of the second power supply 2 is electrically connected to the metal layer 400, the other of the positive electrode and the negative electrode of the second power supply is electrically connected to the third etching chamber 330, and the ground line is grounded. Specifically, because one of the positive and negative electrodes of the first and second power supplies is electrically connected to the third etching chamber, the ends of the positive and negative electrodes of the first and second power supplies, which are electrically connected to the third etching chamber, can be simultaneously connected to the same pole piece, thereby simplifying the circuit structure.
According to some embodiments of the present invention, the first power source 1 may be a dc voltage regulator and the second power source 2 may be a bias power source, so that when no nanopore is formed at the conical tip structure of the metal layer 400, the first circuit structure has no loop current, and the reading of the ammeter 3 is 0 pA; the metal layer is biased by the second power supply 2, and a current loop is formed in the second circuit structure due to the fact that the second circuit structure is provided with a grounding wire, so that electrochemical corrosion occurs at the conical tip of the metal layer 400, and the nano through hole is formed. When the nano-hole is formed at the conical tip structure of the metal layer 400, a loop current is formed in the first circuit structure, and the current is rapidly increased when monitored by the ammeter, which indicates that the nano-hole is formed, and the electrochemical corrosion reaction can be stopped.
For the convenience of understanding, the following is a brief description of the principle that the circuit structure can realize electrochemical corrosion of the metal layer at the cone tip:
in the present invention, the second power source is a bias power source, so for a metal layer having a tapered structure, the tapered point is a pointed structure, so the voltage at the tapered point should be greater than that at other positions, the electrochemical corrosion rate should be faster than that at other positions of the metal layer, and the thickness at the tapered point should be the minimum thickness of the whole metal layer, so the time required for complete electrochemical corrosion is also the shortest. By combining the two points, the conical tip structure of the metal layer is most prone to electrochemical corrosion reaction, and the reaction rate is high. And after the metal layer material at the cone tip is completely reacted, the ammeter can monitor the drastic current change, and at the moment, the electrochemical corrosion reaction can be slowed down or stopped by reducing the voltage of the second power supply 2 or turning off the second power supply 2, so that the nano-pore structure with the extremely small size is realized.
According to some embodiments of the present invention, the detection accuracy of the ammeter should be high so as to realize the monitoring of the current change of the circuit when the nanopore is formed, for example, the monitoring accuracy of the ammeter 3 should reach the pico ampere level when the pore size of the formed nanopore is in the range of 1-10 nm. Specifically, when the pore diameter of the formed nanopore is 10nm, the current value monitored by the ammeter 3 varies in the range of 10 to 100 pA.
According to some embodiments of the present invention, referring to (f) in fig. 3, the electrochemically etching the metal layer at the cone tip further includes: a self-stop device 4, the self-stop device 4 being connected to the first etch chamber 310 and the second circuit structure. The self-stopping device can receive the current value change of the ammeter 3 in the first circuit structure in real time, and when the self-stopping device monitors that the current value of the ammeter 3 is sharply increased from 0 to dozens of to hundreds of picoamperes, the self-stopping device can automatically control the voltage of the second power supply 2 to be reduced or directly close the second power supply 2, so that the automation of the nanopore manufacturing process is realized. Compared with the manual closing of the second power supply after the change of the ammeter value is observed, the automatic stop device has the advantages of higher reaction speed and higher control precision in control, is more favorable for controlling the electrochemical corrosion reaction, and realizes the manufacture of the extremely small metal nano-hole.
According to some embodiments of the present invention, the ammeter may detect a change in the current value whenever the nanopore is formed by electrochemical etching, thereby determining that the nanopore has been formed. But only when the aperture of the nanopore is within a proper range, the nanopore can have higher detection accuracy and sensitivity when being used as a single nanopore sensor. Specifically, the pore diameter of the nanopore is not particularly limited, and for example, the pore diameter of the nanopore may be 1 to 10 nm. When the aperture of the nanopore is smaller than 1nm, the aperture is too small, so that the nanopore is not suitable for being used as a single nanopore sensor to carry out single molecule detection, and an electrochemical system with extremely high precision and sensitivity is required to control in the preparation process, so that the preparation cost is high; (ii) a When the pore diameter of the nanopore is larger than 10nm, the detection precision is not high when the nanopore is applied to biomolecule detection, and the process consumes long time.
In summary, the present application provides a method for fabricating a nanopore, which has at least the following advantages:
firstly, a metal layer is formed at the conical cavity of the silicon-based nano hole through electron beam evaporation or magnetron sputtering, and a conical tip structure of the metal layer is directly formed by means of the conical structure of the first etching cavity, so that the manufacturing cost is effectively reduced.
Secondly, when the conical tip structure of the electrochemical corrosion metal layer is used, a current monitoring method is adopted, and a self-stopping device is adopted to control the reaction to stop, so that the formation of the nano holes can be effectively detected, the electrochemical corrosion reaction can be stopped in time, the over-etching time is shortened, and the size of the metal nano holes is effectively controlled in a smaller range.
Thirdly, the semiconductor process and the MEMS technology are adopted in the whole preparation process, large-scale preparation can be realized, batch production is easy, and meanwhile, the manufacturing cost can be reduced, so that the manufacturing method can be widely applied to the fields of semiconductors, integrated circuits and nano processing.
In another aspect of the present invention, the present invention provides a nanopore structure, which is fabricated by the aforementioned method. Thus, the nanopore structure has all the features and advantages of the fabrication of the nanopore structure, which are not described herein.
In yet another aspect of the present invention, the present invention proposes a single nanopore sensor, referring to fig. 8, the nanopore sensor comprising the aforementioned nanopore structure. Thus, the single nanopore sensor has all the features and advantages of the nanopore structure described above, which are not described herein. In summary, the single nanopore sensor has the advantages of adjustable internal electrochemical properties, high detection sensitivity, high detection speed and high reproducibility.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (15)
1. A method of fabricating a nanopore, comprising:
providing a silicon wafer having a first main surface and a second main surface which are oppositely arranged;
forming a first mask layer on the first main surface of the silicon wafer, and forming a second mask layer on the second main surface of the silicon wafer;
performing first dry etching on the first mask layer to form a first patterning layer, wherein the first patterning layer comprises a first sub-groove;
performing second dry etching on the second mask layer to form a second patterning layer, wherein the second patterning layer comprises a second sub-groove, and the orthographic projection of the first sub-groove on the silicon wafer is positioned inside the orthographic projection of the second sub-groove on the silicon wafer;
performing first wet etching on the first sub-groove to form a first etching cavity, wherein the first etching cavity is of a conical structure, and the conical tip of the conical structure faces the second etching cavity;
performing second wet etching on the second sub-groove to form a second etching cavity, wherein the first etching cavity is not communicated with the second etching cavity;
forming a metal layer on the surface of one side of the first etching cavity, which is far away from the second etching cavity;
carrying out third wet etching on the second etching cavity to form a third etching cavity so as to expose the metal layer positioned at the conical tip;
adding electrolyte solution into the first etching cavity, and adding electrochemical corrosion solution into the second etching cavity;
and performing electrochemical corrosion on the metal layer positioned at the conical tip to form the nanopore.
2. The method of claim 1, wherein the electrochemically etching the metal layer at the cone tip further comprises:
the etching device is connected to a first circuit structure, the first circuit structure comprises a first power supply and an ammeter, the first power supply is connected with the ammeter in series, one of the positive pole and the negative pole of the first power supply is electrically connected with the first etching cavity, and the other of the positive pole and the negative pole of the first power supply is electrically connected with the third etching cavity;
connecting a second circuit structure, wherein the second circuit structure comprises a second power supply and a grounding wire, one of the positive pole and the negative pole of the second power supply is electrically connected with the metal layer, the other of the positive pole and the negative pole of the second power supply is electrically connected with the third etching cavity, and the grounding wire is grounded;
performing the electrochemical etching on the metal layer at the cone tip to form the nanopore.
3. The method of claim 2, further comprising: a self-stop device coupled to the first etch chamber and the second circuit structure.
4. The method of claim 1, wherein the electrolyte solution comprises at least one of potassium chloride and sodium chloride.
5. The method of claim 1, wherein the electrochemical etching solution comprises at least one of hydrochloric acid, nitric acid, sodium chloride, and potassium chloride.
6. The method of claim 1, wherein the forming a first patterned layer further comprises:
forming a first photoresist layer on one side of the first mask layer far away from the silicon wafer,
performing a first patterning process on the first photoresist layer to expose a portion of a surface of the first mask layer,
and performing the first dry etching on the first mask layer to form the first patterning layer.
7. The method of claim 1, wherein the forming a second patterned layer further comprises:
forming a second photoresist layer on one side of the second mask layer far away from the silicon wafer,
performing a second patterning process on the second photoresist layer to expose a portion of the surface of the second mask layer,
and performing the second dry etching on the second mask layer to form the second patterning layer.
8. The method of claim 1, wherein the material forming the first mask layer and the second mask layer comprises at least one of silicon nitride and silicon oxide;
preferably, the first dry etching and the second dry etching are ICP.
9. The method of claim 1, wherein the first wet etch has an etch rate of v1The etching rate of the second wet etching is v2，v1:v2＝(60-80)：(5-15)；
Optionally, the etch rate of the third wet etch is v3，v1:v3＝(60-80)：(1-5)；
Optionally, the concentration of the etching solution of the first wet etching, the concentration of the etching solution of the second wet etching and the concentration of the etching solution of the third wet etching are the same;
preferably, the etching solution of the first wet etching, the etching solution of the second wet etching and the etching solution of the third wet etching are potassium hydroxide solutions.
10. The method according to claim 9, wherein the depth of the first etching cavity in the thickness direction of the silicon wafer is 3 to 5 μm;
optionally, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns.
11. The method of claim 1, wherein a material forming the metal layer comprises at least one of iron, aluminum, platinum, and titanium.
12. The method of claim 1, wherein the process of forming the metal layer comprises at least one of electron beam evaporation and magnetron sputtering.
13. The method of claim 1, wherein the nanopore has a pore size of 1-10 nm.
14. A nanopore structure, characterized in that it is made by the method of any of claims 1-13.
15. A single nanopore sensor, wherein the nanopore sensor comprises the nanopore structure of claim 14.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1736852A (en) * | 2005-09-09 | 2006-02-22 | 华东师范大学 | Silicon microchannel production method |
| CN1807224A (en) * | 2005-12-27 | 2006-07-26 | 北京大学 | Si base membrane nanometer pore canal and its preparation method |
| CN102901763A (en) * | 2012-09-25 | 2013-01-30 | 清华大学 | Deoxyribonucleic acid (DNA) sequencing device based on graphene nanopore-microcavity-solid-state nanopore and manufacturing method |
| CN103449355A (en) * | 2012-05-31 | 2013-12-18 | 中国科学院微电子研究所 | Method for manufacturing nanopore array |
| CN103820311A (en) * | 2014-02-26 | 2014-05-28 | 清华大学 | Nano-pore apparatus used for single-molecule sequencing, and application method and manufacturing method thereof |
| CN104458813A (en) * | 2014-11-28 | 2015-03-25 | 中国科学院重庆绿色智能技术研究院 | Diamond-like film based nano-pore measurement system and preparation method thereof |
| CN105241587A (en) * | 2015-09-25 | 2016-01-13 | 杭州士兰微电子股份有限公司 | Pressure sensor and manufacturing method thereof |
| CN109313157A (en) * | 2016-04-19 | 2019-02-05 | 巴拉什·塔库拉帕里 | Nanopore sensor, structures and devices including the sensor, and methods of forming and using the same |
| CN110329984A (en) * | 2019-06-06 | 2019-10-15 | 清华大学 | A kind of method and device preparing solid nano hole based on dry etching |
| CN110383055A (en) * | 2017-01-18 | 2019-10-25 | 豪夫迈·罗氏有限公司 | Low noise bimolecular sensors |
-
2021
- 2021-12-23 CN CN202111588323.3A patent/CN114264800B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1736852A (en) * | 2005-09-09 | 2006-02-22 | 华东师范大学 | Silicon microchannel production method |
| CN1807224A (en) * | 2005-12-27 | 2006-07-26 | 北京大学 | Si base membrane nanometer pore canal and its preparation method |
| CN103449355A (en) * | 2012-05-31 | 2013-12-18 | 中国科学院微电子研究所 | Method for manufacturing nanopore array |
| CN102901763A (en) * | 2012-09-25 | 2013-01-30 | 清华大学 | Deoxyribonucleic acid (DNA) sequencing device based on graphene nanopore-microcavity-solid-state nanopore and manufacturing method |
| CN103820311A (en) * | 2014-02-26 | 2014-05-28 | 清华大学 | Nano-pore apparatus used for single-molecule sequencing, and application method and manufacturing method thereof |
| CN104458813A (en) * | 2014-11-28 | 2015-03-25 | 中国科学院重庆绿色智能技术研究院 | Diamond-like film based nano-pore measurement system and preparation method thereof |
| CN105241587A (en) * | 2015-09-25 | 2016-01-13 | 杭州士兰微电子股份有限公司 | Pressure sensor and manufacturing method thereof |
| CN109313157A (en) * | 2016-04-19 | 2019-02-05 | 巴拉什·塔库拉帕里 | Nanopore sensor, structures and devices including the sensor, and methods of forming and using the same |
| CN110383055A (en) * | 2017-01-18 | 2019-10-25 | 豪夫迈·罗氏有限公司 | Low noise bimolecular sensors |
| CN110329984A (en) * | 2019-06-06 | 2019-10-15 | 清华大学 | A kind of method and device preparing solid nano hole based on dry etching |
Non-Patent Citations (1)
| Title |
|---|
| SANG RYUL PARK,ET AL.: "Fabrication of Nanopores in Silicon Chips Using Feedback Chemical Etching", 《 SMALL 》 * |
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