CN114256169A - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN114256169A CN114256169A CN202111500686.7A CN202111500686A CN114256169A CN 114256169 A CN114256169 A CN 114256169A CN 202111500686 A CN202111500686 A CN 202111500686A CN 114256169 A CN114256169 A CN 114256169A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 242
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 64
- 239000004033 plastic Substances 0.000 claims description 97
- 239000000758 substrate Substances 0.000 claims description 80
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- 229920001721 polyimide Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The embodiment of the invention provides a semiconductor packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product is reduced undoubtedly, and the miniaturization of the product is facilitated.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
With the rapid development of the semiconductor industry, Fan-out wafer level package (FOWLP) package structures are widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then packaged on a carrier wafer, the main advantages are high-density integration, the size of a packaged product is small, the product performance is excellent, the signal transmission frequency is high, and the like.
Disclosure of Invention
The object of the present invention includes, for example, providing a semiconductor package structure and a method for manufacturing the same, which can reduce the ball mounting size, facilitate miniaturization of products, and facilitate maintenance and replacement of products.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a semiconductor package structure, including:
a substrate carrier;
a semiconductor device disposed on the substrate carrier;
the plastic package body is arranged on the substrate carrier plate and covers the semiconductor device;
a first interposer and a second interposer disposed on the semiconductor device;
the plastic package body is provided with a first groove and a second groove which penetrate through the semiconductor device, the first adapter plate and the second adapter plate are respectively attached in the first groove and the second groove, one side, far away from the semiconductor device, of the first adapter plate is provided with a plurality of first welding balls, one side, far away from the semiconductor device, of the second adapter plate is provided with a second welding ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
In an optional embodiment, the first interposer and the second interposer are disposed at an interval, and a buffer adhesive layer is disposed at least between the first interposer and the second interposer, and the buffer adhesive layer is disposed on a surface of the plastic package body.
In an optional embodiment, one end of the first adapter plate, which is far away from the second adapter plate, is also provided with the buffer glue layer, and one end of the second adapter plate, which is far away from the first adapter plate, is also provided with the buffer glue layer.
In an alternative embodiment, the first groove and the second groove are communicated, and the first adapter plate and the second adapter plate are connected into a whole.
In an optional implementation manner, a first transfer pad is disposed on one side of the first transfer board close to the semiconductor device, a second transfer pad is disposed on one side of the second transfer board close to the semiconductor device, a first conductive pad and a second conductive pad are disposed on one side of the semiconductor device far away from the substrate carrier board, the first conductive pad is connected with the first transfer pad, and the second conductive pad is connected with the second transfer pad.
In an alternative embodiment, a first adhesive layer is arranged between the first transfer plate and the semiconductor device, so that the first transfer plate is attached to the surface of the semiconductor device; and a second adhesive layer is arranged between the second adapter plate and the semiconductor device so that the second adapter plate is attached to the surface of the semiconductor device.
In an alternative embodiment, a projection of the first transfer plate on the substrate carrier at least partially overlaps a projection of the semiconductor device on the substrate carrier; the projection of the second adapter plate on the substrate carrier plate is at least partially overlapped with the projection of the semiconductor device on the substrate carrier plate.
In an alternative embodiment, the size of the first solder ball is smaller than the size of the second solder ball.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor package structure, where the method is used to manufacture the semiconductor package structure, and includes:
mounting a semiconductor device on a substrate carrier;
plastic packaging is carried out on the substrate carrier plate to form a plastic packaging body which is wrapped outside the semiconductor device;
forming a first groove and a second groove which penetrate through the semiconductor device on the plastic package body in a groove mode;
mounting a first adapter plate in the first groove, and mounting a second adapter plate in the second groove;
cutting the plastic package body and the substrate carrier plate;
the semiconductor device comprises a first adapter plate, a second adapter plate and a semiconductor device, wherein one side of the first adapter plate, which is far away from the semiconductor device, is provided with a plurality of first solder balls, one side of the second adapter plate, which is far away from the semiconductor device, is provided with a second solder ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
In a third aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor package structure, where the method is used to manufacture the semiconductor package structure, and includes:
mounting a semiconductor device on the carrier;
plastic packaging is carried out on the carrier to form a plastic packaging body which is coated outside the semiconductor device;
removing the carrier to expose the semiconductor device on one side surface of the plastic package body;
forming a substrate carrier plate covering the semiconductor device by plastic package on the surface of one side of the plastic package body;
forming a first groove and a second groove which penetrate through the semiconductor device on the surface of the other side of the plastic package body in a groove mode;
mounting a first adapter plate in the first groove, and mounting a second adapter plate in the second groove;
cutting the plastic package body and the substrate carrier plate;
the semiconductor device comprises a first adapter plate, a second adapter plate and a semiconductor device, wherein one side of the first adapter plate, which is far away from the semiconductor device, is provided with a plurality of first solder balls, one side of the second adapter plate, which is far away from the semiconductor device, is provided with a second solder ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
The beneficial effects of the embodiment of the invention include, for example:
the embodiment of the invention provides a semiconductor packaging structure and a preparation method thereof, a semiconductor device is arranged on a substrate carrier plate, a plastic package body coated outside the semiconductor device is arranged, and then a first adapter plate and a second adapter plate are arranged on the semiconductor device, wherein a first groove and a second groove penetrating through the semiconductor device are formed in the plastic package body, the first adapter plate and the second adapter plate are respectively attached in the first groove and the second groove, a first solder ball is arranged on one side of the first adapter plate, which is far away from the semiconductor device, a second solder ball is arranged on one side of the second adapter plate, which is far away from the semiconductor device, the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate, a wiring structure is realized by arranging the adapter plates, and only the adapter plates need to be processed when products are maintained and replaced at the later stage, so that the semiconductor packaging structure is convenient and reliable. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product is reduced undoubtedly, and the miniaturization of the product is facilitated. Compared with the prior art, the semiconductor packaging structure provided by the invention can reduce the size of the embedded balls, is beneficial to miniaturization of products, and is convenient to realize maintenance and replacement of the products.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1a is a schematic cross-sectional view of a semiconductor package structure according to a first embodiment of the present invention;
fig. 1b is a schematic cross-sectional view of a semiconductor package structure according to a first embodiment of the present invention;
fig. 2 is a schematic overall structure diagram of a semiconductor package structure according to a first embodiment of the present invention;
fig. 3 to 9 are process flow diagrams of a method for manufacturing a semiconductor package structure according to a first embodiment of the present invention;
fig. 10 is a schematic view of a semiconductor package structure according to a second embodiment of the invention;
fig. 11 is a schematic view of a semiconductor package structure according to a third embodiment of the invention;
fig. 12 is a schematic view of a semiconductor package structure according to a fourth embodiment of the invention;
fig. 13 is a schematic view of a semiconductor package structure according to a fifth embodiment of the present invention;
fig. 14 is a schematic mounting diagram of a semiconductor package structure according to a fifth embodiment of the invention.
Icon: 100-a semiconductor package structure; 110-a substrate carrier; 130-a semiconductor device; 131-a first conductive pad; 133-a second conductive pad; 135-a line layer; 150-plastic package body; 151-first groove; 153-a second groove; 170-a first transfer plate; 171-first solder balls; 173 — first transfer pad; 175-a first adhesive layer; 180-a buffer glue layer; 190-a second interposer; 191-second solder balls; 193-second landing pad; 195-a second adhesive layer; 200-carrier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, in the conventional fan-out wafer packaging process, since the substrate is etched to form the groove and the ball is implanted after the circuit is exposed, the problem that the grounding resistance of the edge bonding pad is unstable due to the oxide is easily generated. Meanwhile, in the packaging process of the fan-out wafer chip, the problem of plastic package warpage is easily caused due to the fact that thermal expansion coefficients of various materials are not matched in the plastic package process. In addition, in the conventional fan-out packaging structure, the wiring layer is exposed after the groove is formed, and then the ball planting process is performed, so that the ball planting size is large, the occupied area of the whole solder ball is large, the packaging size of the product is large, and the miniaturization of the product is not facilitated. When the product is maintained, the circuit layer can not be maintained, and only the whole circuit layer can be scrapped, so that the maintenance and the replacement can not be realized.
In order to solve the above problems, the present invention provides a novel semiconductor package structure and a method for manufacturing the same, which can avoid a ball-mounting process after etching a slot to expose a circuit layer, and the ball-mounting size is small, thereby facilitating miniaturization of a product. Meanwhile, when a problem occurs on a product circuit layer, only the transfer plate needs to be maintained and replaced, and the product is convenient to maintain and replace. It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1a and fig. 2, the present embodiment provides a semiconductor package structure 100, which can avoid performing a ball-mounting process after etching a trench to expose a circuit layer, and the ball-mounting size is small, which is beneficial to miniaturization of a product. Meanwhile, when a problem occurs on a product circuit layer, only the transfer plate needs to be maintained and replaced, and the product is convenient to maintain and replace.
The semiconductor package structure 100 of the present embodiment includes a substrate carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, wherein the semiconductor device 130 is disposed on the substrate carrier 110, the plastic package body 150 is disposed on the substrate carrier 110, and wraps outside the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, one side of the first interposer 170, which is far away from the semiconductor device 130, is provided with a plurality of first solder balls 171, one side of the second interposer 190, which is far away from the semiconductor device 130, is provided with second solder balls 191, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In the actual manufacturing process, the substrate carrier 110, the semiconductor device 130 and the plastic package body 150 are first manufactured, wherein the substrate carrier 110 may be the carrier 200 or the substrate, and the manufacturing process is performed before the plastic package body 150 is formed, that is, after the semiconductor device 130 is mounted on the substrate carrier 110, the plastic package operation of the plastic package body 150 is completed; the substrate carrier 110 may also be a plastic package structure, which is prepared by mounting the semiconductor device 130 on the carrier 200 after the plastic package body 150 is formed, then forming the plastic package body 150 through plastic package, removing the carrier 200, and forming the substrate carrier 110 through plastic package again at the same position. The specific structure of the substrate carrier 110 may be determined according to different process conditions and different processes, and is not limited herein.
It should be noted that in this embodiment, the substrate carrier 110 may be the carrier 200 or a substrate, and an adhesive layer may be further disposed on the substrate carrier 110, where the material of the adhesive layer may be polyimide, benzocyclobutene, and the like, so as to perform an adhesion function, and meanwhile, the substrate carrier 110 plays a role in protecting the semiconductor device 130, and also alleviates a warpage phenomenon of the plastic package generated when the plastic package forms the plastic package body 150.
In other preferred embodiments of the present invention, the substrate carrier 110 may also be a plastic package structure, which is formed by plastic package with the same plastic package material as the plastic package body 150, and the warpage of the plastic package is greatly reduced due to the same plastic package material.
In the embodiment, by disposing the semiconductor device 130 on the substrate carrier 110, and disposing the plastic package body 150 covering the semiconductor device 130, a first interposer 170 and a second interposer 190 are then disposed on the semiconductor device 130, wherein, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first adapter plate 170 and the second adapter plate 190 are respectively mounted in the first groove 151 and the second groove 153, wherein a side of the first interposer 170 away from the semiconductor device 130 is provided with first solder balls 171, a side of the second interposer 190 away from the semiconductor device 130 is provided with second solder balls 191, the semiconductor device 130 is electrically connected to both the first interposer 170 and the second interposer 190, realize wiring structure through setting up the keysets, only need when later stage product maintenance is changed handle the keysets can, convenient and reliable. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product is reduced undoubtedly, and the miniaturization of the product is facilitated.
It should be noted that in this embodiment, both the first interposer 170 and the second interposer 190 are prepared in advance, the first solder balls 171 and the second solder balls 191 thereon may also be formed in advance, and the first interposer 170 and the second interposer 190 are formed with circuit layers, so that the connection with external circuits can be directly realized through the first solder balls 171 and the second solder balls 191. The first adapter plate 170 and the second adapter plate 190 which are prepared in advance are adopted, so that on one hand, the size of the solder balls can be smaller, the occupied space of the solder balls can be smaller, and the miniaturization of products is facilitated; on the other hand, the product is convenient to maintain and replace; moreover, by preparing the adapter plate in advance, the preparation process of the product is greatly shortened, the process difficulty is reduced, and the preparation efficiency of the product is improved.
In this embodiment, the first interposer 170 and the second interposer 190 are disposed at an interval, and at least a buffer adhesive layer 180 is disposed between the first interposer 170 and the second interposer 190, and the buffer adhesive layer 180 is disposed on the surface of the plastic package body 150. Specifically, the first groove 151 and the second groove 153 are disposed at an interval on a side surface of the plastic package body 150 away from the substrate carrier 110, and the size of the first groove 151 is matched with that of the first interposer 170, and the size of the second groove 153 is matched with that of the second interposer 190. In addition, the first adapter plate 170 and the second adapter plate 190 are both protruded from the plastic package body 150, so that a groove structure can be formed between the first adapter plate 170 and the second adapter plate 190, the groove structure is used for forming the buffer glue layer 180, and a buffer effect between the first adapter plate 170 and the second adapter plate 190 is achieved.
In this embodiment, the buffer adhesive layer 180 is made of a material having a thermal expansion coefficient and a young's modulus lower than those of the plastic package body 150, and can deform in preference to the plastic package body 150, so as to play a role in buffering, protect the solder ball pads on the first interposer 170 and the second interposer 190, and avoid solder cracks caused by the influence of stress on the first solder balls 171 and the second solder balls 191. Meanwhile, the buffer layer may be designed around the first interposer 170 and the second interposer 190, or may be arranged in four corner regions of the semiconductor device 130, or may be designed in a region with larger deformation after simulation data of stress of the semiconductor device 130, so as to reduce stress and deformation of the semiconductor device 130.
It should be noted that in this embodiment, the first interposer 170 and the second interposer 190 are both multiple, the multiple first interposer 170 and the multiple second interposer 190 are annularly disposed around the semiconductor device 130, and each first interposer 170 and each second interposer 190 are electrically connected to the semiconductor device 130, where the first interposer 170 and the second interposer 190 have the same structure and are disposed on two sides of the semiconductor device 130, so as to ensure that the product has sufficient signal output points. Of course, the specific number of the first adapter plate 170 and the second adapter plate 190 is not limited herein.
In the present embodiment, a side of the first interposer 170 close to the semiconductor device 130 is provided with a first transfer pad 173, a side of the second interposer 190 close to the semiconductor device 130 is provided with a second transfer pad 193, a side of the semiconductor device 130 away from the substrate carrier 110 is provided with a first conductive pad 131 and a second conductive pad 133, the first conductive pad 131 is connected with the first transfer pad 173, and the second conductive pad 133 is connected with the second transfer pad 193. Specifically, the first transfer board 170 is internally provided with a first circuit layer, the first transfer pad 173 is connected to the first circuit layer through a conductive trace, and the plurality of first solder balls 171 are connected to the first circuit layer, thereby implementing signal output. The second interposer 190 has a second circuit layer disposed therein, the second interposer pad 193 is connected to the second circuit layer through a conductive trace, and the plurality of second solder balls 191 are connected to the second circuit layer. The first transfer pad 173 and the first conductive pad 131 are both copper pads, and are connected by Cu — Cu welding; the second transfer pad 193 and the second conductive pad 133 are also both copper pads, which are also connected by Cu-Cu bonding. Meanwhile, the first interposer 170 and the second interposer 190 may adopt polyimide, benzocyclobutene, or the like as a dielectric layer, and perform wiring and ball-planting on the dielectric layer.
It should be noted that in the present embodiment, the semiconductor device 130 is a chip, and the first interposer 170 and the second interposer 190 are directly connected to pads on the chip, where a chip package may be implemented. In another preferred embodiment of the present invention, referring to fig. 1b, the semiconductor device 130 may also be a combination structure of a chip and a circuit layer 135, that is, the circuit layer 135 is disposed on the upper surface of the chip, and the first interposer 170 and the second interposer 190 are disposed on the circuit layer 135 of the chip, so that the packaging structure of the chip is changed, and the packaging manner of the chip is improved.
In this embodiment, a first adhesive layer 175 is disposed between the first transfer plate 170 and the semiconductor device 130, so that the first transfer plate 170 is attached to the surface of the semiconductor device 130; a second adhesive layer 195 is disposed between the second interposer 190 and the semiconductor device 130, so that the second interposer 190 is attached to the surface of the semiconductor device 130. Specifically, the first adhesive layer 175 and the second adhesive layer 195 may be thermoplastic adhesive layers with lower melting points, so that the first adaptor plate 170 and the second adaptor plate 190 can be detached smoothly after heating, and convenient and fast detachment and installation can be realized. Meanwhile, by arranging the first adhesive layer 175 and the second adhesive layer 195, the bonding and fixing effects of the first adapter plate 170 and the second adapter plate 190 can be improved, and the reliability of the product can be improved.
In the present embodiment, the projection of the first transfer board 170 on the substrate carrier 110 at least partially overlaps with the projection of the semiconductor device 130 on the substrate carrier 110; the projection of the second interposer 190 on the substrate carrier 110 at least partially overlaps the projection of the semiconductor device 130 on the substrate carrier 110. Specifically, in the embodiment, the projected edges of the semiconductor devices 130 at the projected edges of the first interposer 170 on the substrate carrier 110 are overlapped, and the projected edges of the semiconductor devices 130 at the projected edges of the second interposer 190 on the substrate carrier 110 are overlapped, that is, the first interposer 170 is flush with one side of the semiconductor devices 130, and the second interposer 190 is flush with the other side of the semiconductor devices 130, so that the product structure with a smaller size can be conveniently cut in the subsequent cutting.
In this embodiment, the ball-planting sizes of the first solder balls 171 and the second solder balls 191 are the same and are both 10 μm to 20 μm, and since the first interposer 170 and the second interposer 190 adopt the advanced preparation process, the ball-planting sizes of the first solder balls 171 and the second solder balls 191 can be smaller, and more solder balls can be arranged in the same ball-planting region, so that the output ends are more, and the product performance is greatly improved. Meanwhile, under the requirement of the same number of output ends, the ball planting area can be smaller, and miniaturization of products is facilitated.
Referring to fig. 3 to 7 in combination, the present embodiment further provides a method for manufacturing a semiconductor package structure, which is used for manufacturing the semiconductor package structure 100 as described above, wherein the substrate carrier 110 is the carrier 200 that remains, i.e. the step of removing the carrier 200 is not required, and specifically, the method provided by the present embodiment includes the following steps:
s1 a: the semiconductor device 130 is mounted on the substrate carrier 110.
Referring to fig. 3, specifically, a carrier 200 is provided, and a film layer is disposed on the carrier 200, and then the semiconductor device 130 is mounted, wherein the first conductive pad 131 and the second conductive pad 133 on the semiconductor device 130 are both disposed upward, so that the back surface of the semiconductor device 130 is mounted on the film layer of the carrier 200.
S2 a: the plastic package body 150 is formed on the substrate carrier 110 to cover the semiconductor device 130.
Referring to fig. 4, specifically, after the mounting of the semiconductor device 130 is completed, a plastic package body 150 is formed by using a plastic package process, and the plastic package body 150 is wrapped outside the semiconductor device 130.
S3 a: a first groove 151 and a second groove 153 penetrating to the semiconductor device 130 are formed in the molding body 150.
Referring to fig. 5 in combination, specifically, after the plastic package body 150 is formed, a first groove 151 and a second groove 153 are formed on the plastic package body 150 at positions corresponding to the semiconductor device 130 through a laser grooving process, wherein the first groove 151 and the second groove 153 are spaced apart and correspond to the first conductive pad 131 and the second conductive pad 133 on the semiconductor device 130, respectively, and expose the first conductive pad 131 and the second conductive pad 133.
S4 a: a first interposer 170 is mounted in the first recess 151 and a second interposer 190 is mounted in the second recess 153.
Referring to fig. 6 in combination, specifically, the first interposer 170 and the second interposer 190 may be mounted at the same time, and before mounting, an adhesive may be applied to the bonding surfaces of the first interposer 170 and the second interposer 190, so as to form the first adhesive layer 175 and the second adhesive layer 195 after bonding. In mounting, the first transfer pad 173 on the first transfer board 170 and the first conductive pad 131 are connected by Cu-Cu soldering, and the second transfer pad 193 on the second transfer board 190 and the second conductive pad 133 are connected by Cu-Cu soldering.
Note that, here, the first interposer 170 and the second interposer 190 are prepared in advance, and the wiring and ball mounting are completed.
Referring to fig. 7 in combination, after the mounting of the first interposer 170 and the second interposer 190 is completed, a buffer glue layer 180 is further disposed between the first interposer 170 and the second interposer 190. Specifically, the first adapter plate 170 and the second adapter plate 190 are both protruded from the plastic package body 150, so that a groove structure can be formed between the first adapter plate 170 and the second adapter plate 190, and then the groove structure is filled by using a dispensing process, and the colloid is made of a material with a thermal expansion coefficient and a Young modulus lower than those of the plastic package body 150, deforms preferentially to the plastic package body 150, plays a role of a buffer layer, protects a solder ball pad at the bottom of the adapter plate, and is not affected by stress to cause solder ball welding cracks.
S5 a: the plastic package body 150 and the substrate carrier 110 are cut.
With continued reference to fig. 1, in particular, the plastic package body 150 and the substrate carrier 110 are cut along a cutting path, wherein the cutting path may be as close to the first interposer 170 and the second interposer 190 as possible, and preferably, the cutting path may be cut along the edges of the first interposer 170 and the second interposer 190, so as to ensure that the size of the cut product structure is further reduced, and the product preparation is completed after the cutting.
The present embodiment further provides another method for manufacturing a semiconductor package structure, which is used for manufacturing the semiconductor package structure 100 as described above, wherein the step of removing the carrier 200 is required for the plastic-encapsulated structure of the substrate carrier 110, and specifically, the method provided by the present embodiment includes the following steps:
s1 b: the semiconductor device 130 is mounted on the carrier 200.
With continued reference to fig. 3, specifically, a carrier 200 is provided, and a film layer is disposed on the carrier 200, and then the semiconductor device 130 is mounted, wherein the first conductive pad 131 and the second conductive pad 133 on the semiconductor device 130 are both disposed upward, so that the back surface of the semiconductor device 130 is mounted on the film layer of the carrier 200. The adhesive film layer is preferably a UV adhesive film layer, so that the subsequent stripping action is convenient.
S2 b: the carrier 200 is molded to form a molding body 150 covering the semiconductor device 130.
Referring to fig. 4, specifically, after the mounting of the semiconductor device 130 is completed, a plastic package body 150 is formed on the carrier 200 by using a plastic package process, and the plastic package body 150 is wrapped outside the semiconductor device 130.
S3 b: the carrier 200 is removed to expose the semiconductor device 130 on one side surface of the molding body 150.
Referring to fig. 8, in particular, the UV glue layer is peeled off by irradiating UV light, so that the peeling action of the carrier 200 is completed and the semiconductor device 130 is exposed.
S4 b: the substrate carrier 110 covering the semiconductor device 130 is formed on one side surface of the plastic package body 150.
Referring to fig. 9, specifically, after the carrier 200 is removed, the plastic package operation is performed again, and the substrate carrier plate 110 is formed on the surface of one side of the plastic package body 150 by plastic package, wherein the substrate carrier plate 110 is in a plastic package structure, and a plastic package material of the substrate carrier plate is the same as a material of the plastic package body 150.
The subsequent steps are identical to the above-mentioned steps S3a-S5a and will not be described in detail here.
In summary, the present embodiment provides a semiconductor package structure 100 and a method for manufacturing the same, in which a semiconductor device 130 is disposed on a substrate carrier 110, a plastic package body 150 is disposed to cover the semiconductor device 130, and then a first interposer 170 and a second interposer 190 are disposed on the semiconductor device 130, wherein a first groove 151 and a second groove 153 penetrating the semiconductor device 130 are formed in the plastic package body 150, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, a first solder ball 171 is disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, the semiconductor device 130 is electrically connected to the first interposer 170 and the second interposer 190 at the same time, a wiring structure is implemented by disposing the interposers, and only the interposers need to be processed during a later-stage product repair and replacement, is convenient and reliable. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product is reduced undoubtedly, and the miniaturization of the product is facilitated.
Second embodiment
Referring to fig. 10, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.
In the present embodiment, the semiconductor package structure 100 includes a substrate carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, wherein the semiconductor device 130 is disposed on the substrate carrier 110, the plastic package body 150 is disposed on the substrate carrier 110, and wraps outside the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, one side of the first interposer 170, which is far away from the semiconductor device 130, is provided with a plurality of first solder balls 171, one side of the second interposer 190, which is far away from the semiconductor device 130, is provided with second solder balls 191, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In this embodiment, the first interposer 170 and the second interposer 190 are disposed at an interval, and the buffer adhesive layer 180 is disposed between the first interposer 170 and the second interposer 190, and the buffer adhesive layer 180 is disposed on the surface of the plastic package body 150. Meanwhile, one end of the first adapter plate 170, which is far away from the second adapter plate 190, is also provided with a buffer adhesive layer 180, and one end of the second adapter plate 190, which is far away from the first adapter plate 170, is also provided with a buffer adhesive layer 180. Specifically, both sides of first keysets 170 and the both sides of second keysets 190 all are provided with buffering glue film 180, can play the buffering effect better.
Third embodiment
Referring to fig. 11, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.
In the embodiment, the semiconductor package structure 100 includes a substrate carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, wherein the semiconductor device 130 is disposed on the substrate carrier 110, the plastic package body 150 is disposed on the substrate carrier 110, and wraps outside the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, one side of the first interposer 170, which is far away from the semiconductor device 130, is provided with a plurality of first solder balls 171, one side of the second interposer 190, which is far away from the semiconductor device 130, is provided with second solder balls 191, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In the present embodiment, the first groove 151 and the second groove 153 communicate with each other, and the first adaptor plate 170 and the second adaptor plate 190 are integrally connected. Specifically, the first groove 151 and the second groove 153 are communicated into a whole, that is, the buffer glue layer 180 is not arranged between the first adapter plate 170 and the second adapter plate 190, and the first adapter plate 170 and the second adapter plate 190 are also connected into a whole, so that the whole adapter plate mounting structure can be conveniently formed, and the mounting of the adapter plate is more convenient. Meanwhile, the problems of unstable resistance of the semiconductor device 130, falling off of a welding layer and the like caused by oxidation of various chemical agents to the bonding pad of the semiconductor device 130 in the processes of manufacturing the traditional fan-out type semiconductor device 130, plasma etching, exposure, development and the like can be avoided.
Fourth embodiment
Referring to fig. 12, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.
The semiconductor package structure 100 provided by the present embodiment includes a substrate carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, wherein the semiconductor device 130 is disposed on the substrate carrier 110, the plastic package body 150 is disposed on the substrate carrier 110, and wraps outside the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, one side of the first interposer 170, which is far away from the semiconductor device 130, is provided with a plurality of first solder balls 171, one side of the second interposer 190, which is far away from the semiconductor device 130, is provided with second solder balls 191, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In the present embodiment, the projection of the first transfer board 170 on the substrate carrier 110 at least partially overlaps with the projection of the semiconductor device 130 on the substrate carrier 110; the projection of the second interposer 190 on the substrate carrier 110 at least partially overlaps the projection of the semiconductor device 130 on the substrate carrier 110. Specifically, the projection of the first interposer 170 exceeds the projection of the semiconductor device 130, and the projection of the second interposer 190 exceeds the projection of the semiconductor device 130, that is, the first interposer 170 extends outward from one side edge of the semiconductor device 130, and the second interposer 190 extends outward from the other side edge of the semiconductor device 130.
The semiconductor package structure 100 provided by this embodiment employs the first interposer 170 and the second interposer 190 with widened dimensions, so that the first interposer 170 and the second interposer 190 can fall outside the dimension of the semiconductor device 130, the number and density of the wires on the first interposer 170 and the second interposer 190 can be greatly increased, the output solder ball ends can be more dense, and the improvement of the product performance is facilitated.
Fifth embodiment
Referring to fig. 13, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.
The semiconductor package structure 100 provided by the present embodiment includes a substrate carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, wherein the semiconductor device 130 is disposed on the substrate carrier 110, the plastic package body 150 is disposed on the substrate carrier 110, and wraps outside the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating to the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, one side of the first interposer 170, which is far away from the semiconductor device 130, is provided with a plurality of first solder balls 171, one side of the second interposer 190, which is far away from the semiconductor device 130, is provided with second solder balls 191, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In this embodiment, the size of the first solder balls 171 on the first interposer 170 is smaller than the size of the second solder balls 191 on the second interposer 190, so that the first interposer 170 and the second interposer 190 can be applied to different output ports, and the solder balls with different sizes can be attached to different pad areas during subsequent board mounting, thereby realizing different pad areas and functional partitioning.
Referring to fig. 14, in practice, the semiconductor package 100 is mounted on a circuit board 300, wherein the first solder balls 171 and the second solder balls 191 are mounted on different areas of the circuit board 300, and the respective mounting for the areas with different heights can be realized, so as to further realize the functional partitioning of different pad areas.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A semiconductor package structure, comprising:
a substrate carrier;
a semiconductor device disposed on the substrate carrier;
the plastic package body is arranged on the substrate carrier plate and covers the semiconductor device;
a first interposer and a second interposer disposed on the semiconductor device;
the plastic package body is provided with a first groove and a second groove which penetrate through the semiconductor device, the first adapter plate and the second adapter plate are respectively attached in the first groove and the second groove, one side, far away from the semiconductor device, of the first adapter plate is provided with a plurality of first welding balls, one side, far away from the semiconductor device, of the second adapter plate is provided with a second welding ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
2. The semiconductor package structure according to claim 1, wherein the first interposer and the second interposer are spaced apart from each other, and a buffer adhesive layer is disposed at least between the first interposer and the second interposer, and the buffer adhesive layer is disposed on a surface of the plastic package body.
3. The semiconductor package structure according to claim 2, wherein an end of the first interposer remote from the second interposer is also provided with the buffer glue layer, and an end of the second interposer remote from the first interposer is also provided with the buffer glue layer.
4. The semiconductor package structure of claim 1, wherein the first recess and the second recess are in communication, and the first interposer board and the second interposer board are integrally connected.
5. The semiconductor package structure of claim 1, wherein a side of the first interposer board adjacent to the semiconductor device is provided with a first landing pad, a side of the second interposer board adjacent to the semiconductor device is provided with a second landing pad, a side of the semiconductor device away from the substrate carrier is provided with a first conductive pad and a second conductive pad, the first conductive pad is connected with the first landing pad, and the second conductive pad is connected with the second landing pad.
6. The semiconductor package structure according to claim 1, wherein a first adhesive layer is disposed between the first interposer and the semiconductor device, so that the first interposer is attached to a surface of the semiconductor device; and a second adhesive layer is arranged between the second adapter plate and the semiconductor device so that the second adapter plate is attached to the surface of the semiconductor device.
7. The semiconductor package structure of claim 1, wherein a projection of the first interposer board on the substrate carrier at least partially overlaps a projection of the semiconductor device on the substrate carrier; the projection of the second adapter plate on the substrate carrier plate is at least partially overlapped with the projection of the semiconductor device on the substrate carrier plate.
8. The semiconductor package structure of claim 1, wherein a size of the first solder ball is smaller than a size of the second solder ball.
9. A method for manufacturing a semiconductor package structure, for manufacturing the semiconductor package structure according to any one of claims 1 to 8, comprising:
mounting a semiconductor device on a substrate carrier;
plastic packaging is carried out on the substrate carrier plate to form a plastic packaging body which is wrapped outside the semiconductor device;
forming a first groove and a second groove which penetrate through the semiconductor device on the plastic package body in a groove mode;
mounting a first adapter plate in the first groove, and mounting a second adapter plate in the second groove;
cutting the plastic package body and the substrate carrier plate;
the semiconductor device comprises a first adapter plate, a second adapter plate and a semiconductor device, wherein one side of the first adapter plate, which is far away from the semiconductor device, is provided with a plurality of first solder balls, one side of the second adapter plate, which is far away from the semiconductor device, is provided with a second solder ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
10. A method for manufacturing a semiconductor package structure, for manufacturing the semiconductor package structure according to any one of claims 1 to 8, comprising:
mounting a semiconductor device on the carrier;
plastic packaging is carried out on the carrier to form a plastic packaging body which is coated outside the semiconductor device;
removing the carrier to expose the semiconductor device on one side surface of the plastic package body;
forming a substrate carrier plate covering the semiconductor device by plastic package on the surface of one side of the plastic package body;
forming a first groove and a second groove which penetrate through the semiconductor device on the surface of the other side of the plastic package body in a groove mode;
mounting a first adapter plate in the first groove, and mounting a second adapter plate in the second groove;
cutting the plastic package body and the substrate carrier plate;
the semiconductor device comprises a first adapter plate, a second adapter plate and a semiconductor device, wherein one side of the first adapter plate, which is far away from the semiconductor device, is provided with a plurality of first solder balls, one side of the second adapter plate, which is far away from the semiconductor device, is provided with a second solder ball, and the semiconductor device is simultaneously electrically connected with the first adapter plate and the second adapter plate.
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| CN202111500686.7A CN114256169A (en) | 2021-12-09 | 2021-12-09 | Semiconductor packaging structure and preparation method thereof |
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