CN114256147B - Method for preparing semiconductor structure - Google Patents
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- CN114256147B CN114256147B CN202011003762.9A CN202011003762A CN114256147B CN 114256147 B CN114256147 B CN 114256147B CN 202011003762 A CN202011003762 A CN 202011003762A CN 114256147 B CN114256147 B CN 114256147B
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 239000002184 metal Substances 0.000 claims abstract description 114
- 239000002070 nanowire Substances 0.000 claims abstract description 112
- 230000003197 catalytic effect Effects 0.000 claims abstract description 83
- 239000002243 precursor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 230000008018 melting Effects 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
- 239000000523 sample Substances 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 8
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N acetic acid Substances CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
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Abstract
The embodiment of the application provides a preparation method of a semiconductor structure, which relates to the technical field of microelectronics, and can form a P-type heavily doped nanowire or an N-type doped nanowire in a lower-temperature process environment, so that the cost is lower. The preparation method of the semiconductor structure comprises the following steps: forming a substrate layer, and forming at least one trench on a surface of the substrate layer; forming a catalytic metal in the trench; depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench, the doped amorphous precursor contacting the catalytic metal; and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor to enable the catalytic metal to move along the corresponding groove and absorb the doped amorphous precursor, so that the doped nanowire is formed along the way.
Description
Technical Field
The application relates to the technical field of microelectronics, in particular to a semiconductor structure preparation method.
Background
With the development of microelectronics technology, crystalline semiconductor nanowires are the mainstream choice of semiconductor processes because of their extremely low defect states and good charge transport capabilities, while being capable of being stacked and arranged. However, the current methods for doping nanowires, such as ion implantation, molecular diffusion, etc., all require high-temperature annealing (> 600 ℃) to activate the doping atoms, and have high cost.
Disclosure of Invention
The technical scheme of the application provides a preparation method of a semiconductor structure, which can form P-type heavily doped nanowire or N-type doped nanowire in a process environment with lower temperature and has lower cost.
In a first aspect, a technical solution of the present application provides a method for manufacturing a semiconductor structure, including: forming a substrate layer, and forming at least one trench on a surface of the substrate layer; forming a catalytic metal in the trench; depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench, the doped amorphous precursor contacting the catalytic metal; and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor to enable the catalytic metal to move along the corresponding groove and absorb the doped amorphous precursor, so that the doped nanowire is formed along the way.
In one possible embodiment, the process of forming the substrate layer and forming at least one trench on a surface of the substrate layer includes: forming a substrate layer, and forming at least one groove with depth d and width w on the surface of the substrate layer, wherein d is more than or equal to 50nm and less than or equal to 1 mu m, and w is more than or equal to 1 mu m and less than or equal to 100 mu m.
In one possible embodiment, the process of forming the catalytic metal in the trench includes: and depositing catalytic metal with the thickness of h1 in the groove, wherein h is more than or equal to 5nm and less than or equal to 200nm.
In one possible embodiment, after forming the catalytic metal in each trench, further comprising: the catalytic metal is treated with a plasma in an environment at a temperature above the melting point of the catalytic metal, so that the oxide layer on the surface of the catalytic metal is removed and the catalytic metal is converted into a discrete catalytic metal in a liquid state.
In one possible embodiment, the process of depositing the doped amorphous precursor at the locations including the trenches on the surface of the substrate layer comprises: and depositing a doped amorphous precursor with the thickness h1 at the position comprising the groove on the surface of the substrate layer in the environment below the melting point of the catalytic metal, wherein h2 is more than or equal to 10nm and less than or equal to 200nm.
In one possible embodiment, annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor to move the catalytic metal along the corresponding trench and absorb the doped amorphous precursor, forming the doped nanowire along the way includes:
and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor in a non-oxygen environment at a temperature above the melting point of the catalytic metal, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form the doped nanowire along the way.
In one possible embodiment, the catalytic metal is an alloy of one or more of the following metals: indium, tin, bismuth, gallium and aluminum.
In one possible embodiment, the doped amorphous precursor is a heterogeneous stack of one or more of the following: doped amorphous silicon, doped amorphous germanium, and doped amorphous carbon.
In one possible embodiment, the doping element in the doped amorphous precursor is phosphorus or boron.
In one possible embodiment, the doped nanowire is an N-type doped nanowire or a P-type heavily doped nanowire.
In one possible embodiment, the nanowire comprises two ends and a middle portion between the two ends, and after forming the doped nanowire, further comprises:
forming a source metal covering one end of the nanowire, the source metal being connected to one end of the nanowire, forming a drain metal covering the other end of the nanowire, the drain metal being connected to the other end of the nanowire;
forming a gate dielectric layer covering the middle portion of the nanowire;
after forming the gate dielectric layer, further comprising: a gate metal is formed overlying the intermediate portion of the nanowire, the gate dielectric layer being located between the nanowire and the gate metal.
By arranging the groove and depositing the catalytic metal and the doped amorphous precursor in the groove, and then annealing to enable the catalytic metal to move along the groove and absorb the doped amorphous precursor, the doped nanowire extending along the groove is grown, the N-type doped nanowire or the P-type heavily doped nanowire can be directly grown by the preparation method without doping process, the process temperature in the nanowire growth process is lower and can not exceed 600 ℃, so that the compatibility is higher, the cost is low, in addition, the growth direction of the nanowire can be controlled in the whole process because the nanowire grows along the groove, the shape of the nanowire is controlled, the doping atoms in the nanowire are uniformly distributed, and the method is suitable for high-performance semiconductor devices.
Drawings
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 2a is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure after a substrate layer is formed;
FIG. 2b is a schematic diagram of the structure of FIG. 2a after forming trenches;
FIG. 2c is a schematic diagram of the structure of FIG. 2b after deposition of catalytic metal;
FIG. 2d is a schematic diagram of the structure of FIG. 2c after plasma treatment;
FIG. 2e is a schematic diagram of the structure of FIG. 2d after depositing a doped amorphous precursor;
FIG. 2f is a schematic diagram of the structure of FIG. 2e after annealing to form doped nanowires;
FIG. 3 is a schematic cross-sectional view of the sequence of FIGS. 2 a-2 f;
FIG. 4 is a schematic view of another trench structure according to an embodiment of the present disclosure;
FIG. 5 is a flow chart of another method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 6a is a schematic diagram of the structure of FIG. 2f after depositing source metal and drain metal;
FIG. 6b is a schematic diagram of the structure of FIG. 6a after depositing a gate dielectric layer;
fig. 6c is a schematic diagram of the structure of fig. 6b after depositing gate metal.
Detailed Description
The terminology used in the description section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.
Prior to describing the embodiments of the present application, a description will be first given of a problem discovery process of the prior art. The process of doping the nanowires to form N-type and P-type structures can be achieved by a high temperature doping process, but for flexible electronic products, most of the substrates used are Polyimide (PI) materials, the highest temperature that PI materials can withstand is about 400 ℃, and the temperature required by the current doping process exceeds 600 ℃, resulting in poor compatibility of the method of forming doped nanowires by the doping process. Another method for obtaining the doped nanowire is to directly grow the doped nanowire, but the Vapor-liquid-solid (VLS) method is used for directly growing the doped nanowire, so that on one hand, the growth direction of the nanowire is difficult to control, and on the other hand, an amorphous layer is generated on the side wall of the nanowire, and the quality of the nanowire is affected. In addition, only the P-type lightly doped nanowire can be obtained through other growth modes, and the P-type heavily doped nanowire or the N-type doped nanowire cannot be obtained through growth. In order to solve the above-mentioned problems, the present inventors provide a technical solution of an embodiment of the present application, and the technical solution of the embodiment of the present application is described below.
The embodiment of the application provides a method for preparing a semiconductor structure, as shown in fig. 1, 2 a-2 f and 3, the method comprises the following steps:
the trench 11 may be formed on the surface of the base material layer 1 by using photolithography, etching, or the like.
the doped amorphous precursor 3 in the embodiment of the present application refers to an amorphous precursor 3 with a doping concentration other than 0. The doped amorphous precursor 3 may be, for example, amorphous silicon doped with phosphorus or boron, where the doped amorphous precursor 3 at least covers the trench 11 and the catalytic metal 2 in the trench 11, for example, an entire layer of doped amorphous precursor 3 may be formed on the surface of the substrate layer 1, and it should be noted that the order of the steps 102 and 103 is not limited in this embodiment, for example, the catalytic metal 2 may be deposited first and then the doped amorphous precursor 3 may be deposited; it is also possible to deposit the doped amorphous precursor 3 first and then deposit the catalytic metal 2 as long as the catalytic metal 2 contacts the doped amorphous precursor 3 in the trench 11.
The annealing process in step 104 may be performed in a non-oxygen environment, where the annealing temperature is above the melting point of the catalytic metal 2, for example, 300 ℃, and the catalytic metal 2 droplet melts and absorbs the nearby doped amorphous precursor 3, and when the concentration of silicon atoms reaches the supersaturated concentration, doped nanowires 4 are precipitated at the rear end of the catalytic metal 2 droplet, and the doped nanowires 4 grow along the trenches 11. It should be noted that, the cross-sectional views of fig. 2a to 2e in fig. 3 are schematic cross-sectional structures in the AA 'direction, and the cross-sectional view of fig. 2f in fig. 3 is a schematic cross-sectional structure in the BB' direction. Where the doping concentration and type of the nanowire 4 is related to the doping concentration and type of the amorphous precursor, for example, if an N-type doped amorphous precursor 3 is used, an N-type doped nanowire 4 may be grown, and if a P-type heavily doped amorphous precursor 3 is used, a P-type lightly doped nanowire 4 may be grown. It should be noted that in fig. 2f, only one nanowire 4 in each trench 11 is illustrated, and in fig. 3, two nanowires 4 in each trench 11 are illustrated, the number of nanowires 4 in one trench 11 is not limited in the embodiment of the present application, when the width of the trench 11 is large, two nanowires 4 may be formed along two sidewalls of the trench 11, and when the width of the trench 11 is small, only one nanowire 4 may be formed in one trench 11.
According to the preparation method of the semiconductor structure, the grooves are formed, the catalytic metal and the doped amorphous precursor are deposited in the grooves, then the catalytic metal moves along the grooves and absorbs the doped amorphous precursor, doped nanowires extending along the grooves are grown, N-type doped or P-type heavily doped nanowires can be directly grown by the preparation method, the doping process is not needed, the process temperature in the growth process of the nanowires is low and cannot exceed 600 ℃, so that the compatibility is higher, the cost is low, in addition, the growth direction of the nanowires can be controlled in the whole process due to the fact that the nanowires grow along the grooves, the shape of the nanowires is controlled, the doping atoms in the nanowires are distributed uniformly, and the preparation method is suitable for high-performance semiconductor devices.
It should be emphasized that by the semiconductor structure fabrication method according to the embodiment of the present application, the corresponding heavily doped nanowires can be grown by absorbing the amorphous precursor, whereas if the intrinsic amorphous precursor is used, although the nanowire can be grown by absorbing the catalytic metal, only lightly doped nanowires can be grown, so that the semiconductor structure fabrication method according to the embodiment of the present application has a higher compatibility and can be used for fabricating more types of nanowires.
In addition, if the doped amorphous precursor is changed to the intrinsic amorphous precursor during the above process, the P-type atoms In the catalytic metal such as In metal are absorbed during the growth of the nanowire, so that the formed nanowire is a P-type lightly doped nanowire, and on the basis of this, in order to obtain other doped nanowires, if the conventional VLS process is used, it is easy to think that the metal is doped In a gas atmosphere (such as P-doped PH 3 Atmosphere), but in a practical process, PH 3 And the InP is reflected by the catalytic metal to generate stable InP, so that the doping of the nanowire cannot be realized, and the growth of the nanowire is stopped.
In one possible embodiment, the forming the substrate layer 1 and forming the at least one trench 11 on the surface of the substrate layer 1 in the step 101 includes: the substrate layer 1 is formed, and at least one trench 11 having a depth d and a width w is formed on the surface of the substrate layer 1, wherein d is 50 nm.ltoreq.1 μm, and w is 1 μm.ltoreq.100 μm. For example, a trench 11 having a depth d of 100nm and a width w of 2 μm is formed on the surface of the base material layer 1 made of a silicon dioxide material by photolithography. The process of forming the trench 11 may be a dry etching process such as photolithography, inductively coupled plasma (Inductively Coupled Plasma, ICP) etching, reactive ion etching (Reactive Ion Etching, RIE) etching, or a wet etching process using an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), an acidic etching system such as hydrofluoric acid+nitric acid (hf+hno3), hydrofluoric acid+nitric acid+acetic acid (hf+hno3+ch3cooh), or a system such as ethylenediamine catechol (Ethylene Diamine Pyrocatechol).
In one possible embodiment, the process of forming the catalytic metal 2 in the trench 11 in step 102 includes: and depositing catalytic metal 2 with the thickness h1 in the groove 11, wherein h is more than or equal to 5nm and less than or equal to 200nm. For example, the location of the catalytic metal 2 to be deposited is first defined by a photolithographic process, and then a metal of, for example, 20nm is deposited at a certain location of the trench 11 using a thermal evaporation method.
In a possible embodiment, after the step 103 of forming the catalytic metal 2 in each trench 11, the method further includes: in an environment of a temperature higher than the melting point of the catalytic metal 2, the catalytic metal 2 is treated with plasma, so that an oxide layer on the surface of the catalytic metal 2 is removed, and the catalytic metal 2 is converted into a separate catalytic metal 2 in a liquid state. For example, after step 102, the substrate layer 1 with the deposited catalytic metal 2 is first placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus (Plasma Enhanced Chemical Vapor Deposition), and heated to a temperature above the melting point of the catalytic metal 2 (about 200deg.C), using H 2 The plasma treats the surface oxide layer of the catalytic metal 2 in the range of, for example, 3min to 20min and converts the catalytic metal 2 into discrete catalytic metal 2 droplets in, for example, 5 minutes and 30 seconds.
In one possible embodiment, the depositing the doped amorphous precursor 3 on the surface of the substrate layer 1 at the location including the trench 11 in the step 103 includes: in the environment of the temperature below the melting point of the catalytic metal 2, a doped amorphous precursor 3 with the thickness h1 is deposited at the position comprising the groove 11 on the surface of the substrate layer 1, wherein h2 is more than or equal to 10nm and less than or equal to 200nm. For example, at a temperature of around 100 ℃, a doped amorphous precursor 3, for example after 15nm, is deposited.
In one possible embodiment, the annealing treatment of the substrate layer 1 formed with the catalytic metal 2 and the doped amorphous precursor 3 in step 104, the process of moving the catalytic metal 2 along the corresponding trench and absorbing the doped amorphous precursor 3, and forming the doped nanowire 4 along the way includes: and annealing the substrate layer 1 formed with the catalytic metal 2 and the doped amorphous precursor 3 in a non-oxygen environment at a temperature higher than the melting point of the catalytic metal 2, so that the catalytic metal 2 moves along the corresponding groove 11 and absorbs the doped amorphous precursor 3 to form the doped nanowire 4 along the way.
In one possible embodiment, the catalytic metal 2 is an alloy of one or more of the following metals: indium, tin, bismuth, gallium and aluminum.
In one possible embodiment, the doped amorphous precursor 3 is a heterogeneous stack of one or more of the following: doped amorphous silicon, doped amorphous germanium, and doped amorphous carbon. For example, if the doped amorphous precursor 3 is doped amorphous silicon, the nanowire 4 prepared by the above method is a doped silicon nanowire; if the doped amorphous precursor 3 is doped amorphous germanium, the nanowire 4 prepared by the method is doped germanium nanowire 4; if the doped amorphous precursor 3 is a heterogeneous stack of doped amorphous germanium and doped amorphous silicon, the nanowire 4 prepared by the above method is a heterogeneous stack nanowire 4 of doped silicon and germanium.
In one possible embodiment, the doping element in the doped amorphous precursor 3 is phosphorus or boron, i.e. the doped amorphous precursor 3 may be an N-type doped amorphous precursor 3 to grow N-type doped nanowires 4; the doped amorphous precursor 3 may also be a P-type doped amorphous precursor 3 to grow P-type heavily doped nanowires 4.
In addition, it should be noted that, in the above embodiments, the trench 11 is of a linear structure, but the structure of the trench 11 is not limited to the embodiment of the present application, and the doped nanowire 4 grows along the trench 11, so the structure of the trench 11 determines the structure of the doped nanowire 4, as shown in fig. 4, and in other realizable embodiments, the trench 11 has a bent or curved structure, and correspondingly, the doped nanowire 4 grown along the trench 11 also has a corresponding bent or curved structure, so as to adapt to the requirements of the shape of the doped nanowire 4.
In the above examples, the process of growing a nanowire by the semiconductor structure fabrication method provided in the examples of the present application is described, and the process of fabricating a semiconductor device based on the semiconductor structure fabrication method provided in the examples of the present application is further described below, in one possible implementation, as shown in fig. 2f, 5 and 6a to 6c, the nanowire 4 includes two end portions 41 and a middle portion 42 located between the two end portions 41, and after forming the doped nanowire 4, further includes:
step 201, forming a source metal 51 covering one end 41 of the nanowire 4, wherein the source metal 51 is connected to one end 41 of the nanowire 4, forming a drain metal 52 covering the other end 41 of the nanowire 4, and the drain metal 52 is connected to the other end 41 of the nanowire 4;
Specifically, after step 203, to facilitate the top wiring of the overall structure, the gate dielectric layer 6 over the source metal 51 and the drain metal 52 may be further etched away by an etching process so as to expose the source metal 51 and the drain metal 52 on the upper surface of the overall structure, so as to facilitate electrical connection between the transistor and other devices. After steps 101 to 203, a transistor structure is formed, in which the doped nanowire 4 is used as a channel of the transistor, and the specific structure of the transistor is not limited in this embodiment of the present application, for example, the structure shown in fig. 6c is a transistor with a top gate structure, but in other realizable embodiments, the generated doped nanowire 4 may be used as a channel to form a transistor with a bottom gate structure or a transistor with another structure.
In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (8)
1. A method of fabricating a semiconductor structure, comprising:
forming a substrate layer, and forming at least one groove on the surface of the substrate layer;
forming a catalytic metal in the trench;
depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench, the doped amorphous precursor contacting the catalytic metal;
annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor to enable the catalytic metal to move along the corresponding groove and absorb the doped amorphous precursor, and forming a doped nanowire along the way;
the catalytic metal is an alloy of one or more of the following metals: indium, tin, bismuth, gallium and aluminum;
the doped amorphous precursor is a heterogeneous lamination of doped amorphous germanium and doped amorphous silicon;
the doped nanowire is a heterogeneous laminated nanowire of doped silicon and germanium;
the doped nanowire is a P-type heavily doped nanowire, and the doped amorphous precursor is a P-type doped amorphous precursor.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the process of forming a substrate layer and forming at least one trench on a surface of the substrate layer includes:
forming a substrate layer, and forming at least one groove with depth d and width w on the surface of the substrate layer, wherein d is more than or equal to 50nm and less than or equal to 1 mu m, and w is more than or equal to 1 mu m and less than or equal to 100 mu m.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the process of forming catalytic metal in the trench includes:
and depositing catalytic metal with the thickness of h1 in the groove, wherein h1 is more than or equal to 5nm and less than or equal to 200nm.
4. The method of claim 3, wherein the step of,
after forming the catalytic metal in each of the trenches, further comprising:
and treating the catalytic metal by using plasma in an environment of a temperature above the melting point of the catalytic metal, so that an oxide layer on the surface of the catalytic metal is removed, and the catalytic metal is converted into a discrete catalytic metal in a liquid state.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
the process of depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench includes:
and depositing a doped amorphous precursor with the thickness of h2 at the position comprising the groove on the surface of the substrate layer in the environment of the temperature below the melting point of the catalytic metal, wherein h2 is more than or equal to 10nm and less than or equal to 200nm.
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor, and the process of forming the doped nanowire along the way comprises the following steps:
and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor in a non-oxygen environment at a temperature above the melting point of the catalytic metal, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form the doped nanowire along the way.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the doping element in the doped amorphous precursor is phosphorus or boron.
8. The method according to any one of claims 1 to 6, wherein,
the nanowire includes two end portions and an intermediate portion between the two end portions, and after forming the doped nanowire, further includes:
forming a source metal covering one end of the nanowire, the source metal being connected to one end of the nanowire, forming a drain metal covering the other end of the nanowire, the drain metal being connected to the other end of the nanowire;
forming a gate dielectric layer covering the middle part of the nanowire;
after forming the gate dielectric layer, the method further comprises: and forming a gate metal covering the middle part of the nanowire, wherein the gate dielectric layer is positioned between the nanowire and the gate metal.
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