CN114220781A - Circuit substrate, preparation method and insulated gate bipolar transistor module - Google Patents
Circuit substrate, preparation method and insulated gate bipolar transistor module Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4882—Assembly of heatsink parts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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Abstract
The application relates to a circuit substrate, a preparation method of the circuit substrate and an insulated gate bipolar transistor module. The insulated gate bipolar transistor module comprises a circuit substrate and a power chip, wherein a solder layer is arranged between the circuit substrate and the power chip, the circuit substrate comprises a first heat conduction layer, a second heat conduction layer and a third heat conduction layer which are sequentially stacked along the direction far away from the power chip, and the power chip is connected with the first heat conduction layer through the solder layer; a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer; the first thermal diffusion angle is larger than the second thermal diffusion angle, and the thickness of the first heat conduction layer is larger than that of the third heat conduction layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer. The arrangement of the application improves the heat dissipation effect of the insulated gate bipolar transistor module, and reduces the probability of loosening and even cracking of each layer of material.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a circuit substrate, a preparation method of the circuit substrate and an insulated gate bipolar transistor module.
Background
Thermal degradation of an Insulated Gate Bipolar Transistor (IGBT) module is due to fatigue damage of the module caused by thermal stress impact. The factor rate causing the module degradation comprises various aspects of electricity, heat, machinery and the like, and the module mainly causes the module thermal degradation under the combined action of the gradual fatigue accumulation inside and the external working condition, so that the electrical degradation of electrical deviation and the mechanical degradation of cracks caused by the stress strength of a solder layer are induced. Therefore, the research on the thermal degradation mechanism of the IGBT module is of great significance.
The IGBT module includes a Copper-clad ceramic substrate (DBC for short), and in general, the DBC substrate includes a ceramic layer and Copper layers disposed on two sides of the ceramic layer, and the Copper layers on two sides of the ceramic layer have the same thickness.
Disclosure of Invention
The application aims to provide a circuit substrate, a preparation method of the circuit substrate and an insulated gate bipolar transistor module so as to solve the problem that the circuit substrate and the insulated gate bipolar transistor module are poor in heat dissipation effect.
Therefore, in a first aspect, the heat dissipation device comprises a circuit substrate and a power chip, wherein a solder layer is arranged between the circuit substrate and the power chip, the circuit substrate comprises a first heat conduction layer, a second heat conduction layer and a third heat conduction layer which are sequentially stacked along a direction far away from the power chip, and the power chip is connected with the first heat conduction layer through the solder layer; a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer; wherein the first thermal spread angle is greater than the second thermal spread angle, and the thickness of the first thermally conductive layer is greater than the thickness of the third thermally conductive layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer.
In a possible implementation manner, the second heat conduction layer includes a first substrate and a second substrate that are stacked and arranged at an interval, the third heat conduction layer includes a third substrate and a fourth substrate that are stacked and arranged at an interval, and the first substrate, the third substrate, the second substrate, and the fourth substrate are sequentially stacked and arranged along a direction of the first heat conduction layer away from the power chip; the first substrate and the third substrate form the second thermal diffusion angle therebetween, and the second substrate and the fourth substrate form the second thermal diffusion angle therebetween.
In a possible implementation manner, the thermal conductivity of the first substrate is equal to the thermal conductivity of the second substrate, the thermal conductivity of the third substrate, the thermal conductivity of the fourth substrate and the thermal conductivity of the first thermal conductive layer are the same, and the thermal conductivity of the solder layer is greater than or less than the thermal conductivity of the first substrate.
In one possible implementation, the first thermal diffusion angle is larger than the second thermal diffusion angle, the sum of the thicknesses of the circuit substrates is 0.8mm to 1.2mm, the sum of the thicknesses of the first substrate and the second substrate is 1/7 of the circuit substrate, and the sum of the thicknesses of the first heat conduction layer, the third substrate and the fourth substrate is 6/7 of the circuit substrate.
In one possible implementation manner, the first heat conduction layer, the third substrate and the fourth substrate are made of copper; and/or the first substrate and the second substrate are made of ceramics; and/or the material of the power chip comprises silicon; and/or the material of the solder layer comprises lead and tin.
In a possible implementation manner, the power chip further comprises a cooling plate, and the cooling plate is arranged on one side, far away from the power chip, of the circuit substrate.
In a second aspect, an embodiment of the present application provides a circuit substrate, configured to be electrically connected to a power chip of an insulated gate bipolar transistor module, where the circuit substrate includes a first heat conducting layer, a second heat conducting layer, and a third heat conducting layer arranged in a direction away from the power chip, and the power chip is connected to the first heat conducting layer through a solder layer; a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer; wherein the first thermal spread angle is greater than the second thermal spread angle, and the thickness of the first thermally conductive layer is greater than the thickness of the third thermally conductive layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer.
In a possible implementation manner, the second heat conduction layer includes a first substrate and a second substrate that are stacked and arranged at an interval, the third heat conduction layer includes a third substrate and a fourth substrate that are stacked and arranged at an interval, and the first substrate, the third substrate, the second substrate, and the fourth substrate are sequentially stacked and arranged along a direction of the first heat conduction layer away from the power chip; the first substrate and the third substrate form the second thermal diffusion angle therebetween, and the second substrate and the fourth substrate form the second thermal diffusion angle therebetween.
In a third aspect, an embodiment of the present application provides a method for manufacturing a circuit substrate, including cleaning oil components on surfaces of a first heat conduction layer and a third heat conduction layer with an alkaline solution, and cleaning oxide layers on surfaces of the first heat conduction layer and the third heat conduction layer with an acidic solution; cleaning the surface of the second heat conduction layer by using an alkaline solution; sequentially laminating and bonding the first heat conduction layer, the second heat conduction layer and the third heat conduction layer to form a substrate assembly; and placing the substrate assembly on a burning bearing plate for sintering treatment.
In a possible implementation manner, the second heat conduction layer includes a first substrate and a second substrate that are stacked and arranged at intervals, the third heat conduction layer includes a third substrate and a fourth substrate that are stacked and arranged at intervals, the first substrate, the third substrate, the second substrate and the fourth substrate are arranged along the direction of the first heat conduction layer deviating from the power chip is sequentially stacked and arranged, and the first heat conduction layer, the first substrate, the third substrate, the second substrate and the fourth substrate are sequentially stacked and attached to form a substrate assembly.
According to the insulated gate bipolar transistor module provided by the embodiment of the application, the insulated gate bipolar transistor module comprises a circuit substrate and a power chip, a solder layer is arranged between the circuit substrate and the power chip, the circuit substrate comprises a first heat conduction layer, a second heat conduction layer and a third heat conduction layer which are sequentially stacked along the direction far away from the power chip, and the power chip is connected with the first heat conduction layer through the solder layer; a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer; the first thermal diffusion angle is larger than the second thermal diffusion angle, and the thickness of the first heat conduction layer is larger than that of the third heat conduction layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer. This application is through the setting of first thermal diffusion angle and second thermal diffusion angle, the thickness of adjustment first heat-conducting layer and the thickness of third heat-conducting layer, for the setting of insulated gate bipolar transistor module among the prior art, the radiating effect of insulated gate bipolar transistor module has been improved in this application's setting, has reduced each layer material and has taken place the probability of lax or even crackle.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts. In addition, in the drawings, like parts are denoted by like reference numerals, and the drawings are not drawn to actual scale.
Fig. 1 shows a schematic partial structure diagram of an insulated gate bipolar transistor module according to an embodiment.
Description of reference numerals:
1. a circuit substrate; 11. a first thermally conductive layer; 12. a second thermally conductive layer; 121. a first substrate; 122. a second substrate; 13. a third heat conducting layer; 131. a third substrate; 132. a fourth substrate; 2. a power chip; 3. and a solder layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 shows a schematic partial structural diagram of an insulated gate bipolar transistor module according to an embodiment. The embodiment of the application provides an Insulated Gate Bipolar Transistor module, which is an Insulated Gate Bipolar Transistor (IGBT) module for short.
The IGBT module is bound to generate loss when bearing stress, and according to the thermal conductivity analysis of the IGBT module, each layer of the IGBT module has different thermal conductivity, and each layer of the IGBT module can bear thermal stress of different degrees, and the thermal stress can accelerate material degradation. In fact, for any material, any temperature will cause some thermal damage to the material itself. For most materials, thermal fatigue accumulates rapidly at high temperatures, and the state of thermal fatigue depends on the temperature-dependent accumulation of the intensity of thermal damage over time. Any temperature is unsafe for any given time, so that any material will continue to fatigue and degrade under the action of temperature. Under the variable-current working condition, high-temperature thermal damage and impact thermal damage continuously act on the IGBT module, so that the IGBT module becomes a typical thermal fatigue device. Under actual conditions, the environmental stress borne by the IGBT module is changed randomly, and the power intensity stress is changed circularly, so that the loss generated by the module and the junction temperature of a chip are changed.
The IGBT module includes a circuit substrate 1 and a power chip 2, and a solder layer 3 is provided between the circuit substrate 1 and the power chip 2.
The circuit board 1, the circuit board 1 may be a Copper ceramic substrate (DBC for short), the circuit board 1 includes a first heat conduction layer 11, a second heat conduction layer 12 and a third heat conduction layer 13 which are sequentially stacked along a direction away from the power chip 2, and the power chip 2 is connected with the first heat conduction layer 11 through a solder layer 3; a first thermal diffusion angle is formed between the solder layer 3 and the first heat conduction layer 11, and a second thermal diffusion angle is formed between the second heat conduction layer 12 and the third heat conduction layer 13; wherein the first thermal diffusion angle is larger than the second thermal diffusion angle, and the thickness of the first heat conduction layer 11 is larger than that of the third heat conduction layer 13; or the first thermal diffusion angle is smaller than the second thermal diffusion angle and the thickness of the first heat conducting layer 11 is smaller than the thickness of the third heat conducting layer 13.
It is to be understood that the thermal conduction affecting the IGBT module can be either vertical or lateral conduction. The heat dissipation capacity in the vertical direction is determined by thermal resistance, the thermal resistance is determined by the surface area and the thickness of a heat dissipation structure, and compared with the IGBT module in the prior art, the surface area and the thickness of the IGBT module are hardly changed, so that the heat conduction effect of the IGBT module is not changed in the vertical direction; the lateral heat transfer is measured by the thermal spread angle and is mainly represented by the thermal spread area S.
Neglecting the thermal diffusion angle between the power chip 2 and the solder layer 3, the thermal diffusion area S of the IGBT module is y1tanα1+dtanα2+y2tanα3When the heat diffusion area S is larger, the effect of the lateral heat conduction is better. Wherein, y1Is the thickness of the first heat conducting layer 11; d is the thickness of the second heat conducting layer 12; y is2Is the thickness of the third heat conducting layer 13; α is the thermal spread angle. The calculation formula of the thermal diffusion angle α is shown as follows: α ═ arctan (k)1/k2)(0<α<90)，k1And k2Respectively represent the last oneThe thermal expansion coefficient of the layer thermal conductive layer and the thermal expansion coefficient of the current material layer, for example: first thermal diffusion angle α1Second thermal spread angle α ═ arctan (coefficient of thermal expansion of solder layer 3/coefficient of thermal expansion of first thermally conductive layer 11), second thermal spread angle α2Third thermal spread angle α ═ arctan (coefficient of thermal expansion of second layer 12/coefficient of thermal expansion of third layer 13)3Arctan (coefficient of thermal expansion of the first heat conducting layer 11/coefficient of thermal expansion of the second heat conducting layer 12).
First thermal diffusion angle α1Greater than the second thermal spread angle alpha2(ii) a When the heat conduction structure is applied, heat conduction is carried out between the power chip 2 and the solder layer 3, heat conduction is carried out between the solder layer 3 and the first heat conduction layer 11, heat conduction is carried out between the first heat conduction layer 11 and the second heat conduction layer 12, and heat conduction is carried out between the second heat conduction layer 12 and the third heat conduction layer 13. When the thicknesses of the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 are kept constant, the first heat diffusion angle alpha is constant1Greater than the second thermal spread angle alpha2Compared to the first thermal diffusion angle α1Less than or equal to the second thermal diffusion angle alpha2And the heat transfer from the power chip 2 to the first heat conducting layer 11 is better, so that the heat transfer rate from the power chip 2 to the circuit substrate 1 is increased, the heat dissipation effect of the IGBT module is improved, and the probability of loosening and even cracking of each layer of material is reduced.
Further, the first thermal diffusion angle α1Greater than the second thermal spread angle alpha2The thickness of the first heat conduction layer 11 is greater than the thickness of the third heat conduction layer 13, and according to the calculation formula of the heat diffusion area S of the IGBT module, compared with the thickness of the first heat conduction layer 11 which is less than or equal to the thickness of the third heat conduction layer 13, the heat dissipation effect of the power chip 2, the solder layer 3 and the circuit substrate 1 is improved, that is, the heat dissipation effect of the IGBT module is improved.
Further, the first thermal diffusion angle α1Less than the second thermal spread angle alpha2The thickness of the first heat conduction layer 11 is smaller than that of the third heat conduction layer 13, and according to a calculation formula of the heat diffusion area S of the IGBT module, compared with the case that the thickness of the first heat conduction layer 11 is larger than or equal to that of the third heat conduction layer 13, the power chip 2 is improved, and welding is conductedThe heat dissipation effect of the material layer 3 and the circuit substrate 1 is improved, namely, the heat dissipation effect of the IGBT module is improved.
In one embodiment, in an optional example, the second heat conduction layer 12 includes a first substrate 121 and a second substrate 122 stacked and spaced apart, the third heat conduction layer 13 includes a third substrate 131 and a fourth substrate 132 stacked and spaced apart, and the first substrate 121, the third substrate 131, the second substrate 122 and the fourth substrate 132 are sequentially stacked and disposed along a direction of the first heat conduction layer 11 away from the power chip 2; the second thermal diffusion angle is formed between the first substrate 121 and the third substrate 131, and the second thermal diffusion angle is formed between the second substrate 122 and the fourth substrate 132.
The sum of the thicknesses of the second heat conduction layer 12 is equal to the sum of the thicknesses of the first substrate 121 and the second substrate 122, and the sum of the thicknesses of the third heat conduction layer 13 is equal to the sum of the thicknesses of the third substrate 131 and the fourth substrate 132. The first substrate 121 and the second substrate 122 are disposed at an interval, and the third substrate 131 and the fourth substrate 132 are disposed at an interval, that is, the third substrate 131 is disposed between the first substrate 121 and the second substrate 122, and the second substrate 122 is disposed between the third substrate 131 and the fourth substrate 132. Since the second thermal diffusion angle is formed between the second heat conduction layer 12 and the third heat conduction layer 13, the diffusion angle formed between the first substrate 121 and the third substrate 131 is the second thermal diffusion angle, and the diffusion angle formed between the second substrate 122 and the fourth substrate 132 is also the second thermal diffusion angle.
In one embodiment, the thermal conductivity of the first substrate 121 is equal to the thermal conductivity of the second substrate 122, the thermal conductivity of the third substrate 131, the thermal conductivity of the fourth substrate 132 and the thermal conductivity of the first heat conducting layer 11 are the same, and the thermal conductivity of the solder layer 3 is greater than or less than the thermal conductivity of the first substrate 121.
The calculation formula according to the thermal diffusion angle alpha is shown as follows: α ═ arctan (k)1/k2)(0<α<90)，k1And k2Respectively representing the thermal expansion coefficient of the previous thermal conduction layer and the current thermal expansion coefficient of the material layer, and calculating a first thermal diffusion angle alpha1Second thermal diffusion angle alpha2And a third angle of divergence alpha3First thermal spread angle α1Greater than the second heat diffusionAngle alpha2. When the thermal conductivity of the solder layer 3 is greater than that of the first substrate 121, the first thermal diffusion angle α1Is larger than the second thermal diffusion angle, and when the thermal conductivity of the solder layer 3 is smaller than that of the first substrate 121, the first thermal diffusion angle α1Less than the second thermal spread angle alpha2。
In one embodiment, when the first thermal diffusion angle is larger than the second thermal diffusion angle, the sum of the thicknesses of the circuit substrate 1 is 0.8mm to 1.2mm, the thicknesses of the first substrate 121 and the second substrate 122 are 1/7 of the circuit substrate 1, and the sum of the thicknesses of the first heat conduction layer 11, the third substrate 131 and the fourth substrate 132 is 6/7 of the circuit substrate 1. The total thickness of the circuit substrate 1 of the present application is the same as that of the circuit substrate 1 in the related art; therefore, the sum of the total thicknesses of the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 is the same as the total thickness of the circuit substrate 1 in the related art. When the sum of the thicknesses of the circuit substrate 1 is 1mm, the thicknesses of the first substrate 121 and the second substrate 122 are 1/7mm, and the sum of the thicknesses of the first heat conduction layer 11, the third substrate 131, and the fourth substrate 132 is 6/7 mm.
In one embodiment, the materials of the first heat conduction layer 11 and the third and fourth substrates 131 and 132 include copper; and/or the materials of the first substrate 121 and the second substrate 122 include ceramics; and/or the material of the power chip 2 comprises silicon; and/or, the material of the solder layer 3 comprises lead and tin.
It should be understood that the first heat conduction layer 11, the third substrate 131 and the fourth substrate 132 are electrically conductive layers, and the first heat conduction layer 11 is used for connecting external components, such as power chips, pins and the like; the first heat conducting layer 11 may be made of an electrically conductive metal, such as copper, copper-manganese alloy, copper-zinc alloy, copper-aluminum alloy, copper-magnesium alloy, copper-zirconium alloy, or copper-nickel-magnesium alloy. The first substrate 121 and the second substrate 122 are insulating layers, and a ceramic material, such as aluminum oxide, aluminum nitride, beryllium oxide, or silicon carbide, may be selected. The material of the power chip 2 may be monocrystalline silicon, quartz, graphite, or the like. The material of the solder layer 3 can be a mixture of lead and tin in any proportion.
In one example, the first layer 11 and the third layer 13 are made of copper, which has a high current carrying capacity, reduces the size of the cut-off medium, and improves the power capacity. The material of the second heat conduction layer 12 is generally ceramic, and aluminum nitride in the ceramic is selected, the aluminum nitride material is non-toxic, the dielectric constant is moderate, the heat conductivity is far higher than that of aluminum oxide and beryllium oxide, the thermal expansion coefficient is close to that of silicon, various silicon chips and high-power devices can be directly attached to the aluminum nitride substrate without using other transition layers, although the cost is high, the application prospect in the circuit substrate 1 technology is good at present.
The materials of the first heat conduction layer 11, the third substrate 131 and the fourth substrate 132 are selected from copper, that is, the thermal expansion coefficient of the first heat conduction layer 11, the third substrate 131 and the fourth substrate 132 is 17.5 x 10-6m/K; the first substrate 121 and the second substrate 122 are made of ceramic and have a thermal expansion coefficient of 7 × 10-6m/K; the power chip 2 is a silicon plate and has a thermal expansion coefficient of 3 x 10-6m/K, the solder 3 is a mixture of lead and tin and has a coefficient of thermal expansion of 28 x 10-6m/K. Calculating a first thermal diffusion angle alpha by a calculation formula of the thermal diffusion angle1Is 58 degrees and has a second thermal diffusion angle alpha2Is 22 degrees and a third diffusion angle alpha3Is 68 degrees, i.e. the first thermal diffusion angle alpha1Greater than the second thermal spread angle alpha2。
In one example, the thicknesses of the first substrate 121 and the second substrate 122 are equal to 1/14mm, the sum of the thicknesses of the first substrate 121 and the second substrate 122 is 1/7mm, the thicknesses of the third substrate 131 and the fourth substrate 132 are 1/7mm, the sum of the thicknesses of the third substrate 131 and the fourth substrate 132 is 2/7mm, the thickness of the first heat conduction layer 11 is 4/7mm, and the heat diffusion area S ═ y in the present application is calculated to be1tanα1+dtanα2+y2tanα3Equal to 64.418, compared with 23.927 of the heat diffusion area in the prior art, the IGBT module of the present application has a larger lateral heat diffusion area and higher heat dissipation efficiency.
The areas of the first heat conduction layer 11 and the third heat conduction layer 13 are smaller than the area of the second heat conduction layer 12, that is, the areas of the first heat conduction layer 11, the third substrate 131 and the fourth substrate 132 are smaller than the area of the first substrate 121 or the area of the second substrate 122, when the first substrate 121, the third substrate 131, the second substrate 122 and the fourth substrate 132 are sequentially stacked along the direction of the first heat conduction layer 11 deviating from the power chip 2, that is, the first heat conduction layer 11 and the third heat conduction layer 13 are arranged in a crossed manner, and compared with the case that the areas of the first heat conduction layer 11, the third heat conduction layer 13 and the second heat conduction layer 12 are the same, the heat dissipation effect of the IGBT module is further improved.
In an optional example, the IGBT module further includes a cooling plate disposed on a side of the circuit substrate 1 away from the power chip 2. The cooling plate may be made of an insulating material, so that heat of the circuit board 1 is transferred, and the heat dissipation effect of the circuit board 1 is improved.
In an alternative example, as shown in fig. 1, a method for manufacturing a circuit substrate 1 includes cleaning an oily component on the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 with an alkaline solution, and cleaning an oxide layer on the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 with an acidic solution; cleaning the surface of the second heat conducting layer 12 with an alkaline solution; sequentially laminating and attaching the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 to form a substrate assembly; and placing the substrate assembly on a burning bearing plate for sintering treatment.
It is to be understood that the first layer 11 and the third layer 13 may be cleaned simultaneously during the manufacturing process.
When the first heat conduction layer 11 and the third heat conduction layer 13 are cleaned, the first step is to treat the first heat conduction layer 11 and the third heat conduction layer 13 with an alkaline solution, the first heat conduction layer 11 and the third heat conduction layer 13 can be immersed in the alkaline solution or the grease on the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 can be cleaned by a smearing test, and the common alkaline solution can be sodium hydroxide solution or other alkaline solutions. And secondly, after the grease on the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 is cleaned, cleaning the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 by using an acid solution, wherein the oxide layers on the surfaces of the first heat conduction layer 11 and the third heat conduction layer 13 can be cleaned by putting the first heat conduction layer 11 and the third heat conduction layer 13 into the acid solution for immersion cleaning or by a smearing test mode, and the common acid solution can be a hydrochloric acid solution or other acid solutions.
The second layer 12 can be rinsed by immersing the second layer 12 in an acidic solution or by wiping the surface of the second layer 12.
After the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 are cleaned, they are stacked to form a substrate assembly, and then the substrate assembly is placed on a burning plate for sintering treatment.
The circuit substrate 1 is formed after sintering, the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 have enough adhesion strength, and the adhesion strength of the first heat conduction layer 11, the second heat conduction layer 12 and the third heat conduction layer 13 in the circuit substrate 1 with good connection is close to the thick film metallization degree.
In an alternative example, the second heat conduction layer 12 includes a first substrate 121 and a second substrate 122 stacked and spaced apart from each other, the third heat conduction layer 13 includes a third substrate 131 and a fourth substrate 132 stacked and spaced apart from each other, the first substrate 121, the third substrate 131, the second substrate 122, and the fourth substrate 132 are sequentially stacked and disposed along a direction of the first heat conduction layer 11 away from the power chip 2, and the first substrate 121, the third substrate 131, the second substrate 122, and the fourth substrate 132 are sequentially stacked and bonded to form a substrate assembly.
It should be understood that when the substrate assembly is assembled, the first substrate 121 and the second substrate 122 of the second heat conducting layer 12 are spaced apart, and the third substrate 131 and the fourth substrate 132 of the third heat conducting layer 13 are spaced apart, i.e. the first heat conducting layer 11, the second heat conducting layer 12 and the third heat conducting layer 13 are stacked in this order. When the IGBT module is manufactured, the power chip 2 is soldered to the surface of the first heat conduction layer 11 away from the second heat conduction layer 12 through the solder layer 3.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
It should be readily understood that "on … …", "above … …" and "above … …" in this disclosure should be interpreted in its broadest sense such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" includes not only the meaning of "above something" or "above" but also includes the meaning of "above something" or "above" with no intervening features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's illustrated relationship to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The insulated gate bipolar transistor module is characterized by comprising a circuit substrate and a power chip, wherein a solder layer is arranged between the circuit substrate and the power chip, the circuit substrate comprises a first heat conduction layer, a second heat conduction layer and a third heat conduction layer which are sequentially stacked along the direction far away from the power chip, and the power chip is connected with the first heat conduction layer through the solder layer;
a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer;
wherein the first thermal spread angle is greater than the second thermal spread angle, and the thickness of the first thermally conductive layer is greater than the thickness of the third thermally conductive layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer.
2. The IGBT module as recited in claim 1, wherein the second heat conduction layer comprises a first substrate and a second substrate which are stacked and spaced apart, the third heat conduction layer comprises a third substrate and a fourth substrate which are stacked and spaced apart, and the first substrate, the third substrate, the second substrate and the fourth substrate are sequentially stacked in a direction away from the power chip along the first heat conduction layer;
the first substrate and the third substrate form the second thermal diffusion angle therebetween, and the second substrate and the fourth substrate form the second thermal diffusion angle therebetween.
3. The igbt module of claim 2, wherein the first substrate has a thermal conductivity equal to that of the second substrate, the third substrate, the fourth substrate, and the first thermally conductive layer have the same thermal conductivity, and the solder layer has a thermal conductivity greater than or less than that of the first substrate.
4. The igbt module of claim 2, wherein the first thermal spreading angle is greater than the second thermal spreading angle, the sum of the thicknesses of the circuit substrates is 0.8mm to 1.2mm, the sum of the thicknesses of the first and second substrates is 1/7 for the circuit substrate, and the sum of the thicknesses of the first thermally conductive layer, the third substrate, and the fourth substrate is 6/7 for the circuit substrate.
5. The igbt module of claim 2, wherein the first thermally conductive layer, the third substrate, and the fourth substrate are comprised of copper;
and/or the first substrate and the second substrate are made of ceramics;
and/or the material of the power chip comprises silicon;
and/or the material of the solder layer comprises lead and tin.
6. The igbt module of claim 1, further comprising a cooling plate disposed on a side of the circuit substrate away from the power chip.
7. A circuit substrate is used for being electrically connected with a power chip of an insulated gate bipolar transistor module and is characterized by comprising a first heat conduction layer, a second heat conduction layer and a third heat conduction layer which are arranged along the direction far away from the power chip, wherein the power chip is connected with the first heat conduction layer through a welding flux layer;
a first thermal diffusion angle is formed between the solder layer and the first heat conduction layer, and a second thermal diffusion angle is formed between the second heat conduction layer and the third heat conduction layer;
wherein the first thermal spread angle is greater than the second thermal spread angle, and the thickness of the first thermally conductive layer is greater than the thickness of the third thermally conductive layer; or the first thermal diffusion angle is smaller than the second thermal diffusion angle, and the thickness of the first heat conduction layer is smaller than that of the third heat conduction layer.
8. The circuit substrate of claim 7, wherein the second thermal conductive layer comprises a first substrate and a second substrate that are stacked and spaced apart, the third thermal conductive layer comprises a third substrate and a fourth substrate that are stacked and spaced apart, and the first substrate, the third substrate, the second substrate, and the fourth substrate are sequentially stacked in a direction away from the power chip along the first thermal conductive layer;
the first substrate and the third substrate form the second thermal diffusion angle therebetween, and the second substrate and the fourth substrate form the second thermal diffusion angle therebetween.
9. A method for producing a circuit substrate according to claim 7 or 8, comprising:
cleaning oily components on the surfaces of the first heat conduction layer and the third heat conduction layer by adopting an alkaline solution, and cleaning oxide layers on the surfaces of the first heat conduction layer and the third heat conduction layer by adopting an acidic solution;
cleaning the surface of the second heat conduction layer by using an alkaline solution;
sequentially laminating and bonding the first heat conduction layer, the second heat conduction layer and the third heat conduction layer to form a substrate assembly;
and placing the substrate assembly on a burning bearing plate for sintering treatment.
10. The method for manufacturing a circuit substrate according to claim 9, wherein the second heat conduction layer includes a first substrate and a second substrate that are stacked and spaced apart, the third heat conduction layer includes a third substrate and a fourth substrate that are stacked and spaced apart, the first substrate, the third substrate, the second substrate, and the fourth substrate are sequentially stacked and disposed along a direction of the first heat conduction layer away from the power chip, and the first heat conduction layer, the first substrate, the third substrate, the second substrate, and the fourth substrate are sequentially stacked and bonded to form a substrate assembly.
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| CN202111582705.5A CN114220781A (en) | 2021-12-22 | 2021-12-22 | Circuit substrate, preparation method and insulated gate bipolar transistor module |
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| CN202111582705.5A CN114220781A (en) | 2021-12-22 | 2021-12-22 | Circuit substrate, preparation method and insulated gate bipolar transistor module |
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