CN114203253A

CN114203253A - Chip memory fault repair device and chip

Info

Publication number: CN114203253A
Application number: CN202111448187.8A
Authority: CN
Inventors: 徐勤江; 任艳颖; 王超; 吴振杰
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-18

Abstract

The application provides a memory fault repairing device of a chip and the chip, which are used for solving the problem that the fault repairing of the chip fails due to fuse faults of a hardware circuit. When fault detection and repair are carried out on a chip memory, a processor is adopted to read first repair information in a flash, if fault detection is carried out on the chip based on the first repair information, a detection instruction is sent to a register, a detection module acquires the detection instruction in the register, fault detection is carried out on the memory, a detection result is generated, repair data are generated by the repair module based on the detection result and sent to the register, then the processor updates the first repair information based on the repair data of each memory to obtain second repair information, the repair data of each memory are written into the flash for backup, finally, if the chip is determined to be repaired, a repair instruction is sent to the register, and the repair module receives the repair instruction and repairs the memory.

Description

Chip memory fault repair device and chip

Technical Field

The application relates to the technical field of chip detection, in particular to a chip and a device for repairing a fault of a memory of the chip.

Background

At present, when the chip diagnoses and repairs the memory, the one-time programmable fuse memory repair is generally adopted. For a chip, a fuse macro and a control circuit need to be added, and the area and the cost of the chip are increased. Meanwhile, in the conventional chip storage and repair, a hardware circuit is required to be added to control the functions of reading and writing repair data, starting reset after repair and the like, and once the hardware circuit fails, the chip repair cannot be completed, and the hardware failure causes a large risk. In addition, the existing scheme adopts fuse storage and repair data, and the data can be read and written only once, so that the risk of failure of chip repair is increased.

Disclosure of Invention

The application aims to provide a chip memory fault repairing device and a chip, which are used for solving the problem that the fault repairing of the chip fails due to the fuse fault of a hardware circuit.

In a first aspect, the present application provides a device for repairing a chip failure, the device comprising:

treater, nonvolatile memory flash, register, chip, including a plurality of memories in the chip, every memory corresponds a detection module respectively, includes test module and repair module in every detection module, wherein:

the processor is used for reading first repair information in the flash; if the chip is determined to be subjected to fault detection based on the first repair information, sending a detection instruction to the register;

the test module of the memory is used for carrying out fault detection on the memory and sending a detection result to the repair module of the memory when the detection instruction is obtained from the register;

the repair module of the memory is used for generating repair data based on the detection result and sending the repair data to the register;

the processor is further configured to update the first repair information based on the repair data of each memory to obtain second repair information, write the repair data of each memory into the flash for backup, and send a repair instruction to the register if it is determined that the chip is repaired based on the second repair information;

the repair module is further configured to perform a repair operation on the memory based on the repair data of the memory if the repair instruction is received from the register.

In some embodiments, the processor is specifically configured to determine whether to fault detect the chip based on:

and if the first repair information indicates that the chip is not subjected to fault detection, determining to perform fault detection on the chip.

If the first repair information indicates that the chip is subjected to fault detection and the test is passed without repair, determining that the chip is not required to be subjected to fault detection;

if the repair information indicates that the chip has performed fault detection and the chip has a fault but can be repaired, determining that the chip does not need to perform fault detection;

if the repair information indicates that the chip is subjected to fault test and the test failure chip is a bad chip, determining that the chip is not required to be subjected to fault detection;

and if the repair information indicates other conditions except the four types, determining that the chip is required to perform fault detection.

In some embodiments, performing the fault detection on the memory, the test module is specifically configured to:

sending a test stimulus to the memory, and acquiring response information of the test stimulus;

and generating a detection result of the memory based on a comparison result of the response information and a preset value.

In some embodiments, the memory includes a plurality of sections, each section includes a plurality of rows and columns, the detection result includes a fault code, and the fault code includes: first data, second data, and third data, wherein:

the first data is used for indicating a row/column where a fault bit is located;

the second data is used for indicating the chip area identification where the bit with the fault exists, and if the first data indicates that a plurality of rows/columns have faults, the second data is used for indicating the chip area where the lowest column/row of the rows/columns with the faults exists;

the third data is used for indicating the total number of the chips of the chip area where the fault row/column is located.

And/or the detection result further comprises a first detection signal, a second detection signal and a third detection signal, wherein,

the first detection signal is used for indicating whether the memory is tested or not;

the second detection signal is used for indicating whether the memory passes the test;

the third detection signal is used for indicating whether the memory is repairable or not.

In some embodiments, the repair module includes a first unit, a second unit, and a third unit, wherein,

the first unit is used for receiving the first detection signal and storing the fault code;

the second unit is used for analyzing the fault code to generate the repair data and generating an analysis completion signal after the repair data is generated;

the third unit is configured to acquire the analysis completion signal, send the repair data to a register if the analysis completion signal is on a rising edge of the analysis completion signal, and generate a sending completion signal to the register, where the sending completion signal is used to indicate that the sending of the repair data by the register is completed.

In some embodiments, the analyzing the fault code to generate the repair data is performed, and the second unit is specifically configured to:

if the memory includes redundant cells, generating the repair data based on:

if the first data indicate that no fault row/column exists, generating repair data which are used for indicating no fault and do not need to be repaired according to the data format of the repair data;

if the first data indicate that at most n rows/columns have faults and the third data indicate that the faulty rows/columns can be repaired by adopting the redundant units, generating repair data which are used for indicating faults and can be repaired according to the data format of the repair data; wherein n is the number of redundant units of the memory;

if the first data indicate that at most n rows/columns have faults and the third data indicate that the faulty rows/columns cannot be repaired by adopting the redundant units, generating repair data for indicating that the faults and the columns cannot be repaired according to the data format of the repair data;

and if the first data indicate that at least m rows/columns have faults, generating repair data for indicating faults and being incapable of repairing according to a data format of the repair data, wherein m is larger than n.

In some embodiments, the apparatus further includes a peripheral bus APB module to transfer data between the flash and the register in response to the scheduling of the processor.

In some embodiments, the apparatus further includes a Serial Peripheral Interface (SPI) module, and the processor is specifically configured to perform read and write operations on the flash through the SPI module.

In some embodiments, the processor is further configured to;

and if the repair information of the register and the repair module is lost, returning to the step of reading the first repair information in the flash.

In some embodiments, the processor is further configured to detect whether a plurality of regions in the flash fail based on:

writing random data in any target area in the plurality of areas;

reading the random data, and comparing the read value with the random data;

if the read value is consistent with the random data, writing a fault-free mark in the target area;

if the read value is inconsistent with the random data, writing a fault mark in the target area;

the non-fault mark is used for indicating the processor to write second repair information and repair data of each memory in the target area;

the fault mark is used for indicating the processor to prohibit data reading and writing in the target area.

In a second aspect, the present application provides a chip comprising any of the devices as provided in the first aspect of the present application.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

based on the chip fault repairing device and the chip, the chip is repaired by using the board-level flash, fault repairing of a chip memory is completed under the condition that a small amount of extra hardware circuits are added, such as a clock, increase of chip area and cost is avoided, the repairing data is read and written in a software mode, the reading and writing data and a reset circuit are not added, and risks caused by hardware circuit faults are reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application. On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the application.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a chip fault repairing apparatus according to an embodiment of the present disclosure;

FIG. 2 is a flowchart illustrating a process of determining whether to perform a fault detection on a chip memory by a processor according to an embodiment of the present application;

FIG. 3 is a schematic flow chart illustrating a test module performing fault detection on a memory according to an embodiment of the present disclosure;

fig. 4 is a schematic format diagram of a redundant element interface according to an embodiment of the present application;

FIG. 5 is a flow chart illustrating a repair process for a failed memory according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart of a fault detection performed by a flash module according to an embodiment of the present application;

fig. 7 is a schematic overall working flow diagram of a chip failure recovery apparatus according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. The embodiments described are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Also, in the description of the embodiments of the present application, "/" indicates an inclusive meaning unless otherwise specified, for example, a/B may indicate a or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: three cases of a alone, a and B both, and B alone exist, and in addition, "a plurality" means two or more than two in the description of the embodiments of the present application.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the features, and in the description of embodiments of the application, unless stated otherwise, "plurality" means two or more.

The following describes a chip fault repairing apparatus and a chip provided by the present application with reference to embodiments.

The method and the device are mainly used for solving the problem that the fault repair of the chip is failed due to fuse faults of the hardware circuit. The inventive concept of the present application can be summarized as follows: when the fault detection and repair of the chip memory are executed, the processor is adopted to read the first repair information in the flash, if the fault detection is determined to be carried out on the chip based on the first repair information, sending a detection instruction to a register, acquiring the detection instruction in the register by a detection module, fault detection is carried out on the corresponding memory, the detection result is sent to a repair module of the memory, the repair module generates repair data based on the detection result and sends the repair data to a register, then, the processor updates the first repair information based on the repair data of each memory to obtain second repair information, and writing the repair data of each memory into the flash for backup, and finally, if the chip is determined to be repaired based on the second repair information, and sending a repair instruction to the register, and receiving the repair instruction by the repair module to complete the repair operation of the memory. In summary, in the embodiment of the present application, the board level flash is used to repair the chip, and in the case of adding a small amount of additional hardware circuits, such as a clock, the added small amount of hardware devices are not shown in fig. 1, so as to complete fault detection and fault repair of the chip memory, avoid increase of chip area and cost, and adopt a software mode to read and write repair data, without adding read-write data and a reset circuit, so as to reduce risks caused by hardware circuit faults. In addition, the flash that this application adopted supports to burn the same position many times, even flash target location breaks down, but also the software is nimble with repairing data storage to other positions, adopts outside flash to replace piece fuse, solves in case fuse can't the problem of replacement in case the fuse breaks down, has better provided the fault tolerance of whole device. A chip fault repairing device is provided for a user, and user experience is improved.

The device for repairing the memory fault of the chip can be used in a chip test scene before terminal equipment leaves a factory. For example, before a chip built in a smart television leaves a factory, the fault detection and repair of the chip can be completed through the fault repair device provided by the application.

After the main inventive concepts of the embodiments of the present application are introduced, some simple descriptions are provided below for application scenarios to which the technical solutions of the embodiments of the present application can be applied, and it should be noted that the application scenarios described below are only used for describing the embodiments of the present application and are not limited. In specific implementation, the technical scheme provided by the embodiment of the application can be flexibly applied according to actual needs.

Based on the above description, an embodiment of the present application provides a chip failure repairing apparatus, as shown in fig. 1, the apparatus includes: the chip comprises a processor 101, a memory 108, a nonvolatile memory 103, a flash103, a register 105 and a chip, wherein the chip comprises a plurality of memories 108, each memory 108 corresponds to a detection module respectively, each detection module comprises a test module 106 and a repair module 107, and the following steps:

the processor 101 corresponds to the CPU in fig. 1, and is configured to read first repair information in the nonvolatile memory flash of the memory 108; if it is determined to perform the fault detection on the chip based on the first repair information, a detection instruction is sent to the register 105.

In some embodiments, the processor 101 determines whether to perform the failure detection on the chip memory 108 based on the following method, as can be implemented in fig. 2:

in step 201, if the first repair information indicates that the chip memory 108 is not performing fault detection, it is determined that the chip is performing fault detection. For example, if the first repair information repair _ data0 is FFxxxxxx, it indicates that failure detection is not performed, and a first flag bit boot _ mode is generated as 0, and failure detection is determined for the chip based on the first flag bit, and the processor 101 sends a detection instruction to the register 105to trigger the building of each memory 108.

In step 202, if the first repair information indicates that the chip memory 108 has performed fault detection and the test passes the non-repair requirement, it is determined that the chip does not need to perform fault detection. For example, if the first repair information repair _ data0 is 80xxxxxx, a second flag bit boot _ mode is generated as 1, which indicates that the chip memory 108 has performed fault detection and the test passes the test and does not need repair, and it is determined that the chip does not need to perform fault detection based on the second flag bit.

In step 203, if the first repair information indicates that the chip has performed fault detection and the chip has a fault but can be repaired, it is determined that the chip does not need to perform fault detection. For example, the first repair information repair _ dataO is C0xxxxxx, and a third flag bit boot _ mode ═ 2 is generated, which indicates that the chip has performed fault detection and the chip has a fault but can be repaired, and it is determined that the chip does not need to perform fault detection based on the third flag bit.

In step 204, if the first repair information indicates that the chip has performed the fault test and the test-failed chip is a bad chip, it is determined that the chip does not need to perform the fault detection. For example, the first repair information repair _ dataO is A0xxxxxx, and a fourth flag bit boot _ mode is generated to be 3, which indicates that the chip has performed the fault test and the chip failed in the test is a bad chip, and it is determined that the chip does not need to perform the fault detection based on the fourth flag bit.

In step 205, if the first repair information indicates that the four types are excluded, a first flag is generated, that is, the chip memory 108 is determined to be fault-detected according to the first type processing.

The operation of each memory 108 and its corresponding test mode is the same, and for ease of understanding, how to test the memory 108 is described below in the context of one memory 108.

The test module 106 of the memory 108, corresponding to the BIST module in fig. 1, is configured to obtain the detection instruction sent by the processor 101 in the register 105TOP _ REG, perform fault detection on the memory 108, and send the detection result to the repair module 107 of the memory 108, that is, the reparidatagenen module in fig. 1.

In some embodiments, the test module 106 performs fault detection on the memory 108, configures the module by the processor 101 into a BIST MODE (test MODE) in which a corresponding test stimulus is issued to the chip memory 108, waits for the chip memory 108 to respond and output a result, then compares the result with an expected value, and if the result matches the expected value, indicates that the chip memory 108 is not faulty, otherwise indicates that the chip memory 108 is faulty. Specifically, as shown in fig. 3, the following steps can be implemented:

in step 301, processor 101 configures BIST module enable.

In step 302, the BIST module performs different types of fault detection in order.

In step 303, the stimulus is transmitted to the memory 108mem and the response of the memory 108mem is read and compared with the expected value.

In step 304, a fault detection result is generated.

Memory 108 includes a plurality of tiles, each tile including a plurality of rows and columns, such as shown in Table 1 below:

TABLE 1

1	1	1	1
				1	1	1	1
1	1	1	1
				1	1	1	1
1	1	1	1
				1	1	1	1

Assuming that the array of bits 6x4 in table 3 is divided into one partition every two rows, the array of each partition is 2x4, which includes 2 rows and 4 columns.

The detection result comprises a fault code, and the fault code comprises: first data, second data, and third data, wherein:

the first data is used for indicating a row/column where a bit with a fault is positioned;

the third data is used to indicate the total number of tiles in the tile area where the row/column with the fault is located. For example, table 2 below is the first data, the second data, and the third data:

TABLE 2

dataO

data1

data2

Taking the memory 108 of 8192 × 64 as an example, the memory 108 includes a column redundancy unit. The first data0 has 64 bits wide and respectively corresponds to 64 bits of the output Q, and a value of 1 indicates that the corresponding bit of the output Q is faulty, for example, 10001 indicates that the 0 th bit and the 4 th bit of the output Q are faulty. The second data1 indicates which column the failed Q is located in, which is the slice area where the failed bit is located, for example, the 8192 row of the memory 108 of 8192x64 is divided into four columns. If a plurality of bits of the output Q fail, only a chip area where the lowest row of the failed row of the output Q is located is recorded for the memory 108 including the row redundancy unit, or only a chip area where the lowest column of the failed column of the output Q is located is recorded for the memory 108 including the column redundancy unit. The third data2 indicates whether the failure corresponds to the presence of a failure in a plurality of columns.

It should be noted that, in the case that the memory 108 includes 1 redundancy unit, if the memory 108 has 2 redundancy units, the data0 needs to be split into data0_ H and data0_ L, the data0_ H corresponds to the upper 32 bits, i.e., 32 to 63 bits, of the 8192x64 memory 108, the data0_ L corresponds to the lower 32 bits, i.e., 0 to 31 bits, of the 8192x64 memory 108, and the corresponding data1 and data2 need to be split based on the same principle. As shown in table 3 below:

TABLE 3

data0_H

data0_L

data1_H

data1_L

data2_H

data2_L

Taking the memory 108 of 8192 × 64 as an example, it is assumed that the memory 108 includes 2 column redundancy units. The bit width of the first data0_ H is 32 bits, the bit width of the data0_ L is 32 bits, the data correspond to 64 bits of the output Q one by one, a value of 1 indicates that the corresponding bit of the output Q fails, if the data0_ H value is 10001, the data0_ L value is 10001, which indicates that the 0 th bit and the 4 th bit of the output Q fail. Based on the same working mechanism, the second data1_ H and data1_ L indicate which column the failed Q is located in, the column is the slice area where the failed bit is located, for example, 8192 rows of the memory 108 of 8192x64 are divided into four columns. If a plurality of bits of the output Q fail, for the memory 108 including the row redundancy unit, only the chip area where the lowermost column of the failed row of the output Q is located is recorded, and the third data2_ H and data2_ L indicate whether there is a failure corresponding to a plurality of columns.

Besides, in addition to the first data, the second data and the third data, the test module 106 also has other signals as status outputs, so that the detection result further includes a first detection signal, a second detection signal and a third detection signal, wherein:

the first detection signal bist _ done is used to indicate whether the memory 108 has been tested;

the second detection signal bist _ pass is used for indicating whether the memory 108 passes the test, and when the memory 108 has no fault, the signal value is 1, otherwise, the signal value is 0;

the third detection signal bist _ repairable is used to indicate whether the memory 108 is repairable or not.

In summary, the detection result of the memory 108 may include: a first detection signal bist _ done, a second detection signal bist _ pass, a third detection signal bist _ repairable, and a fault code.

After the failure detection of the memory 108 is completed, the repair module 107 of the memory 108 generates repair data based on the detection result and transmits the repair data to the register 105, that is, the reparidatagenen module in fig. 1 generates repair data based on the detection result generated by the BIST module and transmits the repair data to the register 105.

In some embodiments, as shown in fig. 1, the repair module 107 includes a first unit, a second unit, and a third unit, wherein:

the first unit FaultCapture is used for receiving the first detection signal and storing the fault code, and specifically, the main task of the FaultCapture is to receive a BIST _ done signal of the BIST module and latch the fault code, so as to ensure that the BIST module completes fault detection at the moment, and the fault code is the final fault code at the moment.

In some embodiments, the second unit retrievalcular is configured to analyze the fault code to generate repair data, and generate an analysis completion signal after generating the repair data, where the specific details are as follows:

if the memory 108 includes redundant cells, repair data is generated based on the following method:

if the first data indicates that at most n rows/columns have faults and the third data indicates that the faulty rows/columns can be repaired by using the redundant units, generating repair data which indicates faults and can be repaired according to the data format of the repair data; where n is the number of redundant units of the memory 108;

if the first data indicate that at most n rows/columns have faults and the third data indicate that the faulty rows/columns cannot be repaired by adopting the redundant units, generating repair data for indicating that the fault exists and the fault cannot be repaired according to the data format of the repair data;

if the first data indicates that at least m rows/columns have faults, generating repair data indicating faults and unable to repair according to a data format of the repair data, wherein m is larger than n.

Taking the example that the memory 108 includes one redundancy unit, for the column redundancy unit, the row redundancy unit generates the repair data based on the following method:

if the first data indicate that no fault bit exists, generating repair data which are used for indicating no fault and do not need to be repaired according to the data format of the repair data;

if the first data indicate that 1 column of bits have faults and the third data indicate that the bits with faults are in one partition, generating repair data which are used for indicating faults and can be repaired according to the data format of the repair data; if the redundancy unit is row redundancy, one fragment area is a plurality of rows, and if the redundancy unit is column redundancy, one fragment area is a plurality of rows;

if the first data indicate that 1 column of bits have faults and the third data indicate that the faulty bits are in a plurality of areas, generating repair data for indicating that the faults and the repair cannot be performed according to the data format of the repair data;

and if the first data indicate that a plurality of columns of bits have faults, generating repair data for indicating the faults and being incapable of repairing according to the data format of the repair data.

For the row redundancy unit, based on the same working principle, repair data is generated:

if the first data indicate that 1 row of bits have faults and the third data indicate that the bits with the faults are in one partition, generating repair data which are used for indicating the faults and can be repaired according to the data format of the repair data; wherein, if the redundant unit is a row redundant one chip area is a plurality of rows;

if the first data indicate that 1 row of bits have faults and the third data indicate that the faulty bits are in a plurality of areas, generating repair data for indicating that the faults and the repair cannot be performed according to the data format of the repair data;

and if the first data indicate that a plurality of rows of bits have faults, generating repair data for indicating that the faults and the repair cannot be performed according to the data format of the repair data.

Analyzing the fault codes to generate repair data, wherein the step is mainly divided into 2 steps:

the first step, whether the redundant unit can be repaired is judged according to the condition that the bit corresponding to each redundant unit has only 1 row or 1 column to have a fault, and the chip area column where the fault bit is located has only 1. Corresponding first data0, or data0_ H and data0_ L, only 1 bit is 1, while satisfying data2 as 0, or data2_ H and data2_ L as 0.

For example, for a memory 108 that includes one redundancy cell, both row redundancy cells and column redundancy cells may be suitable. If the dataO is all 0, the mem has no fault and does not need to be repaired; if only 1 bit of dataO is 1 and data2 is 0, it indicates that 1 bit fault exists in the memory 108 and is located in 1 sector column, and the memory can be repaired; if only 1 bit of the dataO is 1, and the data2 is 1, it indicates that 1 bit of the mem has a fault, but is located in multiple columns, and cannot be repaired; if the dataO has a plurality of bits as 1, it indicates that the plurality of bits of the memory 108 have a fault and cannot be repaired.

For the memory 108 including 2 column redundancy units, taking the memory 108 of 8192x64 as an example, assuming that the memory 108 includes 2 column redundancy units, data0 needs to be split into data0_ H and data0_ L, data0_ H corresponds to the upper 32 bits, i.e. 32 to 63 bits, of the memory 108 of 8192x64, dataO _ L corresponds to the lower 32 bits, i.e. 0 to 31 bits, of the memory 108 of 8192x64, and corresponding datal and data2 need to be split based on the same principle. If the data0_ H and the data o _ L are both 0, the mem has no fault, and there is no need to repair if only 1 bit of the data0_ H is 1, and the data2_ H is 0, which indicates that 1 bit fault exists in the upper 32 bits of the memory 108, and is located in 1 tile area column, and can be repaired, and further, if only 1 bit of the data0_ L is 1, and the data2_ L is 0, which indicates that 1 bit fault exists in the lower 32 bits of the memory 108, and is located in 1 tile area column, and can be repaired; if only 1 bit of the data0_ H is 1 and the data2_ H is 1, it indicates that 1 bit of the high-order 32 bits of the memory 108 has a fault, but is located in multiple columns and cannot be repaired; if only 1 bit of the data0_ L is 1 and the data2_ L is 1, it indicates that 1 bit of the low 32 bits of the memory 108 has a fault, but the data cannot be repaired when the data is located in a plurality of columns. If a plurality of bits of the data0_ H and the data0_ L are 1, the data0_ H and the data0_ L indicate that a plurality of bits of the upper 32 bits and the lower 32 bits of the memory 108 have faults and cannot be repaired. The entire memory 108 can only be repaired if the failed bits of the upper 32 bits and the lower 32 bits of the memory 108 can be repaired.

Then, a bist _ reproducible signal is generated based on the determination result. A value of 1 for this signal indicates that repair is possible, otherwise it is 0.

Second, repair data repair _ data is generated. The unit converts data0 and data1 into repair data repairdata, generates an analysis complete signal update after the repair data is generated, and sends this signal to the third unit updatereparata.

The redundancy unit interface of the redundant memory 108 is generally in a fixed format, for example, the ARM memory is repaired by 64 bits for the output Q, and the format is shown in fig. 4. For a memory containing two columns of redundant cells, the specific meanings are as follows:

columnsegment (Right) indicates that the redundant cell is at the far right;

shiftiorarange: q [ 31: 0] indicates bits 0 to 31 of the right redundancy repairable Q;

FuseSet { FuseMap. } indicates the right FuseMap [ 4: 0] and Q [ 31: 0], the concrete corresponding relation is shown in FIG. 4;

PinMap { readirenable: CRE1 indicates that the enable signal for the right redundant cell is CRE 1;

FuseMap [0 ]: FCA1[0] indicates that FCA1[0] corresponds to the right FuseMap [0 ];

FuseMap [1 ]: FCA1[0] indicates that FCA1[1] corresponds to the right FuseMap [1 ];

FuseMap [2 ]: FCA1[0] indicates that FCA1[2] corresponds to the right FuseMap [2 ];

FuseMap [3 ]: FCA1[0] indicates that FCA1[3] corresponds to the right FuseMap [3 ];

FuseMap [4 ]: FCA1[0] indicates that FCA1[4] corresponds to the right FuseMap [4 ];

column (left) indicates that the redundant cell is located at the far left;

shiftiorarange: q [ 63: 32] bits 63 to 32 indicating the left redundancy repairable Q;

FuseSet { FuseMap. } indicates that the left FuseMap is similar to Q [ 63: 32], please refer to fig. 4 for the concrete relationship;

PinMap { readirenable: CRE2 indicates enable signal CRE2 for the left redundant cell;

FuseMap [0 ]: FCA1[0] indicates that FCA1[0] corresponds to the left FuseMap [0 ];

FuseMap [1 ]: FCA1[0] indicates that FCA1[1] corresponds to the left FuseMap [1 ];

FuseMap [2 ]: FCA1[0] indicates that FCA1[2] corresponds to the left FuseMap [2 ];

FuseMap [3 ]: FCA1[0] indicates that FCA1[3] corresponds to the left FuseMap [3 ];

FuseMap [4 ]: FCA1[0] indicates that FCA1[4] corresponds to the left FuseMap [4 ].

Interface signals are CRE1/FCA1[ 4: 0] and CRE2/FCA2[ 4: 0]. Where CRE1 controls whether the first block redundancy cell is used, a CRE1 value of 1 indicates that the defective cell is replaced with a redundancy cell and a value of 0 indicates that the redundancy cell is not used. FCA1[ 4: 0 represents a Bit for which the first block redundancy unit can repair Q. As shown in fig. 4, as FCA1[ 4: 0 ═ 0 indicates that the 32 th bit of Q has failed, and the 32 th bit of Q can be repaired with a redundant cell. The same is true for CRE2 and FCA 2. In this example CRE1 can repair bits 0-31 of Q and CRE2 can repair bits 32-63 of Q, i.e., all bits of Q of the memory 108 can be repaired.

In some embodiments, the third unit updatereparidat converts data0 and data1 into repair data repairda, generating repair data, the format of which is as follows in table 4:

TABLE 4

CRE2

FCA2[4]

FCA2[3]

FCA2[2]

FCA2[1]

FCA2[0]

CRE1

FCA1[4]

FCA1[3]

FCA1[2]

FCA1[1]

FCA1[0]

Both CRE1 and CRE2 include two states in the table, namely a value of 1 or 0, with 1 indicating repair is enabled and 0 indicating repair is not enabled. While FCA1[ 4: 0] and FCA2[ 4: 0] corresponds to output bits 0-31 and 32-63, respectively, with the same value of 1 or 0, FCA1[ 4: 0] and FCA2[ 4: 0] in the 5 positions of Table 4, which are 5-bit binary values, this value indicates the value of CRE1, FCA1[ 4: 0], CRE2 and FCA2[ 4: 0] these 12 interface signals correspond to a 12-bit binary, which is the repair data for the corresponding memory 108.

A third unit, updaterepariatdata, configured to acquire an analysis completion signal, send the repair data to the register 105 if a rising edge of the analysis completion signal is acquired, and generate a sending completion signal, repair _ done, to the register 105, where the sending completion signal is used to indicate that sending of the repair data by the register 105 is completed.

At this point, the replairdatagen module completes the judgment of repairability, the generation of repair data and the transmission and latching of the repair data. The replairdatagen basically generates a transmission completion signal repair _ done, a repairable signal repair _ pass, and repair data repairda, and then transmits the two signals and repair data to the register 105.

The above describes a process of detecting and repairing data of the memory 108.

In some embodiments, after completing the fault detection on the memories 108 and generating the repair data, the processor 101 is further configured to update the first repair information based on the repair data of each memory 108 to obtain second repair information, for example, when a value of the first repair information repair _ data0 is FFxxxxxx, the CPU sends an instruction to the test module 106 to complete the fault detection and generate the repair data, collects and reads the repair data from the register 105, updates the first repair information repair _ data0 to obtain the second repair information 80xxxxxx if it is determined that the memory 108 does not have a fault based on the repair data, and writes the repair data of each memory 108 into a flash for backup. If it is determined to repair the memory 108 based on the second repair information. The step of repairing the failing memory 108 may be implemented as shown in FIG. 5 as:

in step 501, the processor 101 sends a repair instruction to the register 105.

In step 502, the repair module 107 performs a repair operation on the memory 108 based on the repair data of the memory 108 when receiving the repair instruction from the register 105. The repair data is configured by repair _ data _ gen to the repair interface of the memory 108, e.g., CRE1/FCA1/CRE2/FCA 2.

The repair of the memory 108 is performed by adding redundant cells, and replacing the cells with failures, including row redundant cells and column redundant cells, with normal ones of the redundant cells.

Row redundancy unit: for example, mem of 8192 × 64, 2 redundancy units are added at the top and bottom, and there are actually 8194 64-bit data, corresponding to [ 8193: 0]. The middle 8192 64 bits are used normally, i.e., [ 8192: 1] x [ 63: 0]. If the Nth bit of the address A1 breaks down, the data reading and writing of the bit is abnormal, after the data is repaired, the address A1 is skipped, and the storage unit is divided into a left part and a right part 2. Assuming that address a1 is located on the right side, the address range of the repaired memory mem is { [ 8193: a1+1], [ a 1-1: 1] } x [ 63: 0] if address a1 is located on the left side, the address range of the repaired memory mem is { [ 8192: a1+1], [ a 1-1: 0] } x [ 63: 0].

Column redundancy unit: the memory mem of 8192x64, which is mainly repaired for the output Q, is actually 8192x66, and normally uses [ 8191: 0] x [ 64: 1] use after repair [ 8191: 0] x { [ 65: a1+1], [ a 1-1: 1] } or [ 8191: 0] x { [ 64: a1+1], [ a 1-1: 0]}. Both redundancy modes exist for the actual project. Column redundancy cells are more widely used and the present application is directed to memories 108 with column redundancy cells.

It should be added that the apparatus provided in the embodiment of the present application further includes a peripheral bus APB module 102, which is configured to respond to the scheduling of the processor 101 to transmit data between the flash and the register 105, and mainly cooperate with the CPU to complete the transfer of the repair data, mainly including the transfer from the TOP _ REG to the CPU, and the transfer of the repair data from the CPU to the TOP _ REG.

The device also comprises a Serial Peripheral Interface (SPI) module 103, and the processor 101 carries out read-write operation on the flash through the SPI module. The SPI module has the chip self-function, and the existing SPI reading and writing programs are utilized, so that the repeated development of chip software is reduced.

In some embodiments, if the entire apparatus is powered off, the repair information of the register 105 and the repair module 107 is lost, but the flash still stores the repair data, the processor 101 may read the data in the flash, and return to the step of reading the first repair information in the flash.

In some embodiments, the flash module is a memory unit and belongs to a board level device. Typically 2-3 repair blocks are allocated, the first repair block being the default, 2 nd and 3 rd being alternative, the processor 101 is further configured to detect whether multiple areas in the flash fail based on the following method, as shown in fig. 6:

in step 601, random data is written in a target area of any one of a plurality of areas in the flash.

In step 602, random data is read and the read value is compared to the random data.

In step 603, if the read value matches the random data, a non-failure flag is written in the target area, and the non-failure flag instructs the processor 101 to write the second repair information and the repair data of each memory 108 in the target area. For example, if the read value is consistent with the random data, the procedure returns to step 601, and the test is repeated 20 times, and if the test passes 20 times, the number FF of non-failure flags is written in the first byte of the area.

In step 604, if the read value does not match the random data, a failure flag is written in the target area, and the failure flag instructs the processor 101 to prohibit writing of the second repair information and the repair data of each memory 108 in the target area. For example, if the read value is not consistent with the random data, indicating that the area is faulty, the first byte of the area is written with the fault flag 00, the next block of the candidate area is replaced, and step 601 and step 603 are repeated.

In some embodiments, the overall work flow of the chip fault repairing apparatus provided by the present application may be implemented as follows in fig. 7:

in step 701, the chip is reset, i.e. the chip is powered on, and starts to operate.

In step 702, the CPU reads data information in the flash.

In step 703, it is determined whether the value of the highest 8bit of the first repair data in the exclusive data information is FF, that is, whether the first repair information repair _ data0 is ffxxxxxxxx, and whether the chip performs fault detection.

In step 704, if the highest 8bit value of the first repair data is FF, the CPU issues an instruction to configure the repair interface of the memory 108 in an invalid state, so as to avoid the influence of data information in the flash on the repair interface, and configure the clock and rst of the memory 108 to be in a working state.

In step 705, the CPU configures the test module 106BIST, issues a failure detection start signal of the memory 108, and issues a read-write command.

In step 706, the test module 106 performs fault detection on the corresponding memory 108 to obtain a fault result. Since a chip usually has N memories 108, each memory 108 is given a corresponding number N, which results in N bist _ done, bist _ pass, bist _ replay.

In step 707, the repair module 107 corresponding to the memory 108 analyzes the failure result of the memory 108, generates repair data, and transmits the repair data to the register 105. Since N failure results will be generated in step 706, bist _ done, bist _ pass, and bist _ reparable, then N repair _ done/prearrable/repair _ data will be generated. For convenience of explanation, hereinafter referred to as repair _ done _ n, repable _ n, repair _ n.

In step 708, the CPU collects and reads the repair data from the register 105, and if it is determined that there is no failure in the memory 108 based on the repair data, updates the first repair information repair _ data0 to obtain the second repair information 80xxxxxx, and reads and writes the values of repair _ data1-repair _ data254 to be all 0.

In step 709, the CPU writes the repair data to the flash for backup.

In step 710, if the CPU determines that the memory 108 has a failure based on the repair data and determines that the memory 108 is repairable, the first repair information repair _ data0 is updated by writing to obtain the second repair information C0 xxxxxxxx, and the value of repair _ data254 is read from the TOP _ REG.

In step 711, the CPU writes the repair data to the flash for backup and repairs the failed memory 108.

In step 712, if the CPU determines that the memory 108 has a failure based on the repair data and determines that the memory 108 is not repairable, the CPU updates the first repair information repair _ data0 to obtain second repair information A0 xxxxxxxx and determines that the memory 108 is a defective. The steps really realize the repair of the chip by using the board-level flash, and under the condition of not increasing an additional hardware circuit, the fault repair of the chip memory 108 is completed, so that the increase of the area and the cost of the chip is avoided, the repair data is read and written by adopting a software mode, the read-write data and the reset circuit are not increased, and the risk brought by the fault of the hardware circuit is reduced. The chip fault repairing device and the chip are provided for a user, and user experience is improved.

Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

The embodiments provided in the present application are only a few examples of the general concept of the present application, and do not limit the scope of the present application. Any other embodiments extended according to the scheme of the present application without inventive efforts will be within the scope of protection of the present application for a person skilled in the art.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. An apparatus for memory fail repair of a chip, the apparatus comprising:

2. The apparatus of claim 1, wherein the processor is specifically configured to determine whether to fault detect the chip based on:

if the first repair information indicates that the chip is not subjected to fault detection, determining to perform fault detection on the chip;

if the first repair information indicates that the chip has been subjected to fault detection and the chip has a fault but can be repaired, determining that the chip is not required to be subjected to fault detection;

if the first repair information indicates that the chip has been subjected to the fault test and the test failure chip is a bad chip, determining that the chip is not required to be subjected to the fault detection;

and if the first repair information indicates other conditions except the four conditions, determining that the chip is required to perform fault detection.

3. The apparatus of claim 1, wherein performing the failure detection on the memory, the test module is specifically configured to:

4. The apparatus of claim 1 or 3, wherein the memory comprises a plurality of tiles, each tile comprising a plurality of rows and columns, and wherein the detection result comprises a fault code, and wherein the fault code comprises: first data, second data, and third data, wherein:

the third data is used for indicating the total number of the chips of the chip area where the fault row/column is located;

5. The apparatus of claim 4, wherein the repair module comprises a first unit, a second unit, and a third unit, wherein,

6. The apparatus of claim 5, wherein the analyzing the fault code to generate the repair data is performed, and wherein the second unit is specifically configured to:

if the memory includes redundant cells, generating the repair data based on:

7. The apparatus of claim 1, further comprising a peripheral bus APB module to transfer data between the flash and the register in response to a schedule of the processor.

8. The apparatus of claim 1, wherein the processor is further configured to;

9. The apparatus of claim 1, wherein the processor is further configured to detect whether a plurality of regions in the flash fail based on:

writing random data in any target area in the plurality of areas;

reading the random data, and comparing the read value with the random data;

10. A chip comprising the device of any one of claims 1-9.