CN114122018A - Thin film structure and manufacturing method thereof - Google Patents
Thin film structure and manufacturing method thereof Download PDFInfo
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- CN114122018A CN114122018A CN202111370693.XA CN202111370693A CN114122018A CN 114122018 A CN114122018 A CN 114122018A CN 202111370693 A CN202111370693 A CN 202111370693A CN 114122018 A CN114122018 A CN 114122018A
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- 239000010409 thin film Substances 0.000 title claims abstract description 217
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 73
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 374
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 374
- 239000010408 film Substances 0.000 claims description 111
- 239000000463 material Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 230000005527 interface trap Effects 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 6
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 349
- 230000008569 process Effects 0.000 description 15
- 239000000758 substrate Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Thin Film Transistor (AREA)
Abstract
The embodiment of the application provides a thin film structure and a manufacturing method of the thin film structure, and relates to the technical field of display. The first metal oxide thin film transistor and the second metal oxide thin film transistor which adopt different metal oxide layers as active layers have different subcritical slope values, and can be used in a pixel driving circuit of a current-driven light-emitting element to meet the requirements of the thin film transistors with different functions on the subcritical slope values. Compared with the thin film structure manufactured by adopting the thin film transistors of different types, the thin film structure manufactured by adopting the thin film transistors of the same type can simplify the manufacturing process flow and reduce the manufacturing cost. In addition, the thin film structure has lower power consumption compared with a thin film structure consisting of an amorphous silicon thin film transistor, and has better uniformity compared with a thin film structure consisting of a low-temperature polycrystalline silicon thin film transistor.
Description
Technical Field
The application relates to the technical field of display, in particular to a thin film structure and a manufacturing method of the thin film structure.
Background
In a pixel driving circuit that drives a light emitting element with a current, such as a pixel driving circuit of an AMOLED, a driving thin film transistor needs to have a characteristic in which a drain current gently rises with respect to a gate voltage (having a large sub-critical Slope value) in order to facilitate switching of a pixel gray scale, and a switching thin film transistor needs to have a characteristic in which a drain current steeply rises with respect to a gate voltage (having a small sub-critical Slope value). Therefore, in the process of fabricating the thin film transistor of the array driving layer, how to fabricate the thin film transistor with different sub-critical slope values is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In order to overcome the technical problems mentioned in the above technical background, embodiments of the present application provide a thin film structure and a method for manufacturing the thin film structure.
In a first aspect of the present application, there is provided a thin film structure comprising: a first metal oxide thin film transistor and a second metal oxide thin film transistor;
the first metal oxide thin film transistor comprises a first metal oxide layer, a first gate electrode, a first source electrode, a first drain electrode and a first gate insulating layer, wherein the first metal oxide layer comprises a first source region, a first channel region and a first drain region, the first source electrode is connected with the first source region, the first drain electrode is connected with the first drain region, the first gate insulating layer is positioned on one side of the first channel region, and the first gate electrode is positioned on one side of the first gate insulating layer, which is far away from the first channel region;
the second metal oxide thin film transistor comprises a second metal oxide layer, a second gate electrode, a second source electrode, a second drain electrode and a second gate insulating layer, the second metal oxide layer comprises a second source region, a second channel region and a second drain region, the second source electrode is connected with the second source region, the second drain electrode is connected with the second drain region, the second gate insulating layer is positioned on one side of the second channel region, and the second gate electrode is positioned on one side, far away from the second channel region, of the second gate insulating layer;
the subcritical slope value of the first metal oxide thin film transistor is different from the subcritical slope value of the second metal oxide thin film transistor.
In the above structure, the first metal oxide thin film transistor and the second metal oxide thin film transistor which adopt different metal oxide layers as active layers have different subcritical slope values, and can be used in a pixel driving circuit of a current-driven light emitting element to meet the requirements of different functional thin film transistors on the subcritical slope values. Compared with the thin film structure manufactured by adopting the thin film transistors of different types, the thin film structure manufactured by adopting the thin film transistors of the same type can simplify the manufacturing process flow and reduce the manufacturing cost. In addition, the thin film structure has lower power consumption compared with a thin film structure consisting of an amorphous silicon thin film transistor, and has better uniformity compared with a thin film structure consisting of a low-temperature polycrystalline silicon thin film transistor.
In one possible embodiment of the present application, the first metal oxide thin film transistor is a switching thin film transistor, and the second metal oxide thin film transistor is a driving thin film transistor;
the subcritical slope value of the second metal oxide thin film transistor is larger than that of the first metal oxide thin film transistor.
In one possible embodiment of the present application, the first metal oxide layer and the second metal oxide layer include at least one metal oxide film layer structure;
the first metal oxide layer comprises a first metal oxide film layer structure in contact with the first grid insulating layer, and the second metal oxide layer comprises a second metal oxide film layer structure in contact with the second grid insulating layer;
the interface trap of the first metal oxide film layer structure is smaller than that of the second metal oxide film layer structure;
the difference between the subcritical slope value of the second metal oxide thin film transistor and the subcritical slope value of the first metal oxide thin film transistor is greater than or equal to 0.2V/dec.
In one possible embodiment of the present application, the first metal oxide film layer structure is a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure composed of at least two elements of indium, gallium, and zinc, and oxygen;
the second metal oxide film layer structure is a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure formed by combining rare earth elements with one or two of indium elements, gallium elements and zinc elements and oxygen elements.
In one possible embodiment of the present application, the first metal oxide layer and the second metal oxide layer are located in the same layer, the first gate electrode and the second gate electrode are made of the same metal layer, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are made of the same metal layer; or
The first metal oxide layer and the second metal oxide layer are located on different layers, the first gate electrode and the second gate electrode are made of different metal layers, and the metal layers for making the first source electrode and the first drain electrode and the metal layers for making the second source electrode and the second drain electrode are different metal layers.
In a second aspect of the present application, there is provided a method for fabricating a thin film structure, the method comprising:
respectively manufacturing a first metal oxide layer and a second metal oxide layer by adopting a first metal oxide material and a second metal oxide material, wherein the first metal oxide layer comprises a first source electrode region, a first channel region and a first drain electrode region, and the second metal oxide layer comprises a second source electrode region, a second channel region and a second drain electrode region;
manufacturing a grid electrode insulating layer on the first metal oxide layer and the second metal oxide layer;
forming a first gate electrode and a second gate electrode in regions of the gate insulating layer corresponding to the first channel region and the second channel region, respectively;
manufacturing dielectric layers on the gate insulating layer, the first gate electrode and the second gate electrode, and manufacturing film layer through holes respectively corresponding to the first source region, the first drain region, the second source region and the second drain region on the dielectric layers and the gate insulating layer;
and manufacturing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on one side of the dielectric layer far away from the gate insulation layer, and respectively connecting the first source electrode area, the first drain electrode area, the second source electrode area and the second drain electrode area through the film layer through hole to obtain a first metal oxide thin film transistor and a second metal oxide thin film transistor.
In one possible embodiment of the present application, the step of respectively forming the first metal oxide layer and the second metal oxide layer by using the first metal oxide material and the second metal oxide material includes:
manufacturing a first metal oxide film layer by adopting a first metal oxide material, and patterning the first metal oxide film layer to obtain the first metal oxide layer;
and manufacturing a second metal oxide film layer by adopting a second metal oxide material, and patterning the second metal oxide film layer to obtain the second metal oxide layer.
In one possible embodiment of the present application, the step of respectively forming the first metal oxide layer and the second metal oxide layer by using the first metal oxide material and the second metal oxide material includes:
manufacturing a first metal oxide film layer by adopting a first metal oxide material;
manufacturing a second metal oxide film layer on the first metal oxide film layer by adopting a second metal oxide material;
and forming the first metal oxide layer and the second metal oxide layer by patterning, wherein the first metal oxide layer comprises the first metal oxide film layer, and the second metal oxide layer comprises the first metal oxide film layer and the second metal oxide film layer which are stacked.
In a third aspect of the present application, there is provided a method for fabricating a thin film structure, the method comprising:
manufacturing a first metal oxide layer, wherein the first metal oxide layer comprises a first source region, a first channel region and a first drain region;
manufacturing a first grid electrode insulating layer on the first metal oxide layer;
forming a first gate electrode in a region of the first gate insulating layer corresponding to the first channel region;
manufacturing a first dielectric layer on the first gate insulating layer and the first gate electrode, and manufacturing first film layer through holes corresponding to the first source electrode region and the first drain electrode region respectively on the first dielectric layer and the first gate insulating layer;
manufacturing a first source electrode and a first drain electrode on one side of the first dielectric layer far away from the first gate insulation layer, and respectively connecting the first source electrode and the first drain electrode with the corresponding first source electrode area and the corresponding first drain electrode area through the first film layer through hole to obtain a first metal oxide thin film transistor;
manufacturing a buffer layer on one side of the first dielectric layer far away from the first grid insulation layer;
manufacturing a second metal oxide layer on one side of the buffer layer, which is far away from the first dielectric layer, wherein the second metal oxide layer comprises a second source electrode region, a second channel region and a second drain electrode region;
manufacturing a second grid electrode insulating layer on the second metal oxide layer;
forming a second gate electrode in a region of the second gate insulating layer corresponding to the second channel region;
manufacturing a second dielectric layer on the second gate insulating layer and the second gate electrode, and manufacturing second film layer through holes corresponding to the second source electrode region and the second drain electrode region respectively on the second dielectric layer and the second gate insulating layer;
and manufacturing a second source electrode and a second drain electrode on one side of the second dielectric layer far away from the second gate insulating layer, and respectively connecting the second source electrode area and the second drain electrode area through the second film layer through hole to obtain a second metal oxide thin film transistor.
In one possible embodiment of the present application, an interface trap of a first metal oxide material is larger than an interface trap of a second metal oxide material, and when the first metal oxide material is used to fabricate the first metal oxide layer and the second metal oxide layer is made of the second metal oxide material, the second metal oxide thin film transistor is a driving thin film transistor, and the first metal oxide thin film transistor is a switching thin film transistor; or the like, or, alternatively,
when the first metal oxide layer is made of the second metal oxide material and the second metal oxide layer is made of the first metal oxide material, the first metal oxide thin film transistor is a driving thin film transistor, and the second metal oxide thin film transistor is a switch thin film transistor.
Compared with the prior art, the thin film structure and the thin film structure manufacturing method provided by the embodiment of the application have the advantages that the first metal oxide thin film transistor and the second metal oxide thin film transistor which adopt different metal oxide layers as active layers have different subcritical slope values, and can be used in a pixel driving circuit of a current-driven light-emitting element to meet the requirements of the thin film transistors with different functions on the subcritical slope values. In addition, compared with the thin film structure manufactured by adopting the thin film transistors of different types, the thin film structure manufactured by adopting the thin film transistors of the same type can simplify the manufacturing process flow and reduce the manufacturing cost. In addition, the thin film structure has lower power consumption compared with a thin film structure consisting of an amorphous silicon thin film transistor, and has better uniformity compared with a thin film structure consisting of a low-temperature polycrystalline silicon thin film transistor.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic diagram of a pixel driving circuit;
FIG. 2 is a schematic diagram of a partial film structure of a thin film structure according to an embodiment of the present disclosure;
FIG. 3 is a second schematic diagram of a partial film structure of a thin film structure according to an embodiment of the present disclosure;
fig. 4 is a third schematic view of a partial film structure of a thin film structure according to an embodiment of the present disclosure;
FIG. 5 is a fourth schematic view of a partial film structure of a thin film structure provided in an embodiment of the present application;
FIG. 6 is a schematic flow chart illustrating a method for fabricating a thin film structure according to an embodiment of the present disclosure;
FIG. 7 is a process diagram corresponding to FIG. 6;
FIG. 8 is a process diagram for fabricating a first metal oxide layer and a second metal oxide layer according to an embodiment of the present disclosure;
FIG. 9 is a diagram illustrating another process for forming a first metal oxide layer and a second metal oxide layer according to an embodiment of the present disclosure;
FIG. 10 is a second flowchart illustrating a method for fabricating a thin film structure according to an embodiment of the present disclosure;
FIGS. 11a and 11b are process diagrams corresponding to FIG. 10;
fig. 12 is a fifth schematic view of a partial film structure of a film structure according to an embodiment of the present application.
Prime notation
1-a thin film structure; 10-a first metal oxide thin film transistor; 101-a first metal oxide layer; 1011-a first source region; 1012-first channel region; 1013-a first drain region; 102-a first gate electrode; 103-a first source electrode; 104-a first drain electrode; 105-a first gate insulation layer; 20-a second metal oxide thin film transistor; 201-a second metal oxide layer; 2011-second source region; 2012-a second channel region; 2013-a second drain region; 202-a second gate electrode; 203-a second source electrode; 204 — a second drain electrode; 205-a second gate insulation layer; 30-a substrate layer; 40-a buffer layer; 401 — a first buffer layer; 402-a second buffer layer; 50-a dielectric layer; 501-a first dielectric layer; 502-a second dielectric layer; 60-a planarization layer; 70-an anode film layer; 80-a pixel defining layer; 90-a layer of luminescent material.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, are only used for convenience of description and simplification of description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
It should be noted that, in case of conflict, different features in the embodiments of the present application may be combined with each other.
In order to solve the technical problems in the background art, a possible solution provided by the prior art is to use different types of TFTs as thin film transistors with different functions, for example, in the pixel driving circuit shown in fig. 1, a low temperature polysilicon thin film transistor (LTPS TFT) may be used as a driving thin film transistor (M2 in the figure), a metal oxide thin film transistor (e.g., an indium gallium zinc oxide thin film transistor (IGZO TFT)) may be used as a switching thin film transistor (M1, M3 to M7 in the figure), and the respective functional thin film transistors are manufactured according to the subcritical slope value characteristics of the different types of thin film transistors.
However, the inventor has found that in the above solution, due to the difference in the manufacturing processes of the different types of thin film transistors, a large number of masks are required to be used in the manufacturing process, which increases the manufacturing cost of the thin film structure and the complexity of the manufacturing process flow. In addition, the problems of difficult uniformity control and high cost exist in the process of manufacturing a thin film structure by adopting the low-temperature polycrystalline silicon thin film transistor.
The inventor provides a solution for adjusting the subcritical slope value of the metal oxide thin film transistor with different functions by adopting the metal oxide thin film transistor to form a thin film structure and realizing different requirements of the driving thin film transistor and the switching thin film transistor on the subcritical slope value through different interface defects of an active layer (metal oxide layer) in the metal oxide thin film transistor. Specific implementations of the present application will be described in detail below with reference to the accompanying drawings.
It should be noted that the above prior art solutions have defects which are the results of practical and careful study by the inventor, therefore, the discovery process of the above technical problems and the solutions proposed by the following embodiments of the present application for the above problems should be the contribution of the inventor to the present application in the course of the invention creation process, and should not be understood as technical contents known by those skilled in the art.
To better describe the technical solution provided by the embodiment of the present application, please refer to fig. 2, and fig. 2 shows one of the schematic views of the partial film structure of the thin film structure provided by the embodiment of the present application.
The thin film structure 1 provided in this embodiment may include a first metal oxide thin film transistor 10 and a second metal oxide thin film transistor 20.
The first metal oxide thin film transistor 10 may include a first metal oxide layer 101 (made of a metal oxide material Mo-1), a first gate electrode 102, a first source electrode 103, a first drain electrode 104, and a first gate insulating layer 105. The first metal oxide layer 101 may include a first source region 1011, a first channel region 1012, and a first drain region 1013. The first source electrode 103 is connected to the first source region 1011, and the first drain electrode 104 is connected to the first drain region 1013. The first gate insulation layer 105 is located on a side of the first channel region 1012, and the first gate electrode 102 is located on a side of the first gate insulation layer 105 away from the first channel region 1012.
The second metal oxide thin film transistor 20 may include a second metal oxide layer 201 (made of a metal oxide material Mo-2), a second gate electrode 202, a second source electrode 203, a second drain electrode 204, and a second gate insulating layer 205. The second metal oxide layer 201 may include a second source region 2011, a second channel region 2012, and a second drain region 2013. The second source electrode 203 is connected to the second source region 2012, and the second drain electrode 204 is connected to the second drain region 2013. The second gate insulating layer 205 is located on a side of the second channel region 2012, and the second gate electrode 202 is located on a side of the second gate insulating layer 205 away from the second channel region 2012.
In the embodiment of the present application, the first metal oxide thin film transistor 10 and the second metal oxide thin film transistor 20 may have a top gate structure or a bottom gate structure. The first gate insulating layer 105 and the second gate insulating layer 205 may be the same layer or different layers. For example, when the first metal oxide thin film transistor 10 and the second metal oxide thin film transistor 20 are both of a top gate structure and the first metal oxide layer 101 and the second metal oxide layer 201 are located at the same layer, the first gate insulating layer 105 and the second gate insulating layer 205 may be at the same layer (for example, fig. 2); when the first metal oxide layer 101 and the second metal oxide layer 201 are located on the same layer, and the first metal oxide thin film transistor 10 is a top gate structure, and the second metal oxide thin film transistor 20 is a bottom gate structure, the first gate insulating layer 105 and the second gate insulating layer 205 may be different layers. In the present embodiment, the first metal oxide layer 101 and the second metal oxide layer 201 are located on the same layer, which means that the first metal oxide layer 101 and the second metal oxide layer 201 are fabricated on the same side of the same layer (e.g., a buffer layer).
In the embodiment of the present application, the sub-critical slope value of the first metal oxide thin film transistor 10 is different from the sub-critical slope value of the second metal oxide thin film transistor 20.
In the above structure, the first metal oxide thin film transistor 10 and the second metal oxide thin film transistor 20, which use different metal oxide layers as active layers, have different subcritical slope values, and can be used in a pixel driving circuit of a current-driven light emitting element to meet the requirements of different functional thin film transistors on the subcritical slope values. Meanwhile, compared with the thin film structure manufactured by adopting the thin film transistors of different types, the thin film structure manufactured by adopting the thin film transistors of the same type can simplify the manufacturing process flow and reduce the manufacturing cost. In addition, the thin film structure has lower power consumption compared with a thin film structure consisting of an amorphous silicon thin film transistor, and has better uniformity compared with a thin film structure consisting of a low-temperature polycrystalline silicon thin film transistor.
Referring to fig. 3, in the embodiment of the present disclosure, the thin film structure 1 may further include a substrate layer 30, a buffer layer 40, a dielectric layer 50, a planarization layer 60, an anode film layer 70, a pixel defining layer 80, a light emitting material layer 90, and the like.
The substrate layer 30 may be a glass substrate or a resin substrate. Functionally, the substrate layer 30 may be a hard substrate or a flexible substrate, and this embodiment is not particularly limited. The buffer layer 40 is located on the substrate layer 30, and the first metal oxide layer 101 and the second metal oxide layer 201 may be located on a side of the buffer layer 40 away from the substrate layer 30. The dielectric layer 50 may be located on a side of the first gate insulating layer 105 and/or the second gate insulating layer 205 away from the buffer layer 40, the planarization layer 60 is located on a side of the dielectric layer 50 away from the first gate insulating layer 105, and the planarization layer 60 is provided with a planarization via. The anode film layer 70 on the side of the planarization layer 60 away from the dielectric layer 50 may be connected to the drain of the metal oxide thin film transistor through a planarization via, and the pixel defining layer 80 is on the side of the planarization layer 60 away from the dielectric layer 50 and defines a pixel opening for evaporating the light emitting material layer 90 on the anode film layer 70.
Further, the first metal oxide thin film transistor 10 may be a switching thin film transistor, and the second metal oxide thin film transistor 20 may be a driving thin film transistor. Accordingly, the subcritical slope value of the second metal oxide thin film transistor 20 is greater than the subcritical slope value of the first metal oxide thin film transistor 10.
The first metal oxide thin film transistor 10 is used as a switching thin film transistor, and the second metal oxide thin film transistor 20 is used as a driving thin film transistor.
In the embodiment of the present application, the first metal oxide layer 101 and the second metal oxide layer 201 include at least one metal oxide film layer structure. The first metal oxide layer 101 and the second metal oxide layer 102 may have a single-film structure or a multi-film structure. For example, the first metal oxide layer 101 and the second metal oxide layer 102 may have the same number of films or different numbers of films. For example, as shown in fig. 4, as an example, the first metal oxide layer 101 has a one-layer structure, and the second metal oxide layer 201 has a two-layer structure. In fig. 4, the first metal oxide layer 101 may include a first metal oxide film layer structure 101A in contact with the first gate insulating layer 105, and the second metal oxide layer 201 may include a second metal oxide film layer structure 201A in contact with the second gate insulating layer 205 and a metal oxide film layer structure located under the second metal oxide film layer structure 201A, wherein an interface trap of the first metal oxide film layer structure 101A is smaller than an interface trap of the second metal oxide film layer structure 201A, wherein a higher interface trap corresponds to a larger subcritical slope value. The difference between the sub-threshold slope value of the second metal oxide thin film transistor 20 and the sub-threshold slope value of the first metal oxide thin film transistor 10 is greater than or equal to 0.2V/dec.
Further, in the embodiment of the present application, in order to make the interface trap of the first metal oxide film layer structure 101A smaller than the interface trap of the second metal oxide film layer structure 201A. The first metal oxide film layer structure 101A may be a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure composed of at least two elements of indium, gallium, and zinc, and oxygen. The second metal oxide film layer structure 201A may be a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure formed by combining one or two of rare earth elements, indium element, gallium element and zinc element, and oxygen element.
Referring to fig. 3 again, in an implementation manner of the embodiment of the present disclosure, the first metal oxide layer 101 and the second metal oxide layer 201 may be located on the same layer, the first gate electrode 102 and the second gate electrode 202 may be formed by the same metal layer (e.g., the first metal layer M1 in the thin film structure), and the first source electrode 103, the first drain electrode 104, the second source electrode 203, and the second drain electrode 204 may be formed by the same metal layer (e.g., the third metal layer M3 in the thin film structure). Referring to fig. 5, in another implementation manner of the embodiment of the present application, the first metal oxide layer 101 and the second metal oxide layer 201 are located at different layers, and the first gate electrode 102 and the second gate electrode 202 are made of different metal layers, wherein the first gate electrode 102 may be made of a first metal layer M1, the second gate electrode 202 may be made of a fifth metal layer M5, the first source electrode 103 and the first drain electrode 104 may be made of a third metal layer M3, and the second source electrode 203 and the second drain electrode 204 may be made of a sixth metal layer M6.
Fig. 6 and 7 are shown, fig. 6 shows a schematic flow chart of steps of the thin film structure manufacturing method provided in the embodiment of the present application, fig. 7 shows a process diagram corresponding to the thin film structure manufacturing method of fig. 6, and the thin film structure manufacturing method provided in the embodiment of the present application is described in detail below with reference to fig. 6 and 7.
Step S101, a first metal oxide layer 101 and a second metal oxide layer 201 are respectively manufactured by using a first metal oxide material Mo-1 and a second metal oxide material Mo-1.
The first metal oxide layer 101 includes a first source region, a first channel region, and a first drain region, the second metal oxide layer includes a second source region, a second channel region, and a second drain region, and an interface trap of the first metal oxide layer 101 is different from an interface trap of the second metal oxide layer 201.
In this step, the first metal oxide layer 101 and the second metal oxide layer 201 may be formed on the buffer layer 40, and before this step, the method for forming a thin film structure may further include a step of forming the buffer layer 40 on the provided substrate layer 30.
In step S102, a gate insulating layer 105(205) is formed on the first metal oxide layer 101 and the second metal oxide layer 201.
In step S103, a first gate electrode 102 and a second gate electrode 202 are formed in regions of the gate insulating layer 105(205) corresponding to the first channel region and the second channel region, respectively.
Step S104 is to form a dielectric layer 50 on the gate insulating layer 105(205), the first gate electrode 102 and the second gate electrode 202, and form film vias on the dielectric layer 50 and the gate insulating layer 105(205) corresponding to the first source region, the first drain region, the second source region and the second drain region, respectively.
Step S105, a first source electrode 103, a first drain electrode 104, a second source electrode 203, and a second drain electrode 204 are formed on a side of the dielectric layer 50 away from the gate insulating layer 105(205), so that the first source electrode 103, the first drain electrode 104, the second source electrode 203, and the second drain electrode 204 are respectively connected to the corresponding first source region, the corresponding first drain region, the corresponding second source region, and the corresponding second drain region through the film vias, thereby obtaining a first metal oxide thin film transistor and a second metal oxide thin film transistor.
In an implementation manner of the embodiment of the present disclosure, the first metal oxide layer 101 and the second metal oxide layer 201 may be single-layer films, referring to fig. 8, fig. 8 illustrates a process diagram corresponding to step S101, and the following method may be implemented in combination with step S101 corresponding to fig. 8.
First, a first metal oxide film layer is made of a first metal oxide material MO-1, and the first metal oxide film layer is patterned (for example, patterning is performed by an etching process) to obtain a first metal oxide layer 101.
Then, a second metal oxide film layer is made of a second metal oxide material MO-2, and the second metal oxide film layer is patterned to obtain a second metal oxide layer 201.
Specifically, the first metal oxide layer 101 may be shielded by a mask when the second metal oxide layer is manufactured, so that the second metal oxide material MO-2 may not form a film on the first metal oxide layer, and in addition, when the second metal oxide layer is etched by using the etching liquid, the etching liquid used for etching the second metal oxide layer may not etch the first metal oxide layer 101.
It is understood that, in the above process, the second metal oxide layer 201 may be formed first, and then the first metal oxide layer 101 may be formed.
In an implementation manner of the embodiment of the present application, the first metal oxide layer 101 and the second metal oxide layer 201 may have at least one film structure, and the first metal oxide layer 101 is a one-layer film structure, and the second metal oxide layer 201 is a two-layer film structure, as an example, please refer to fig. 9, in which fig. 9 illustrates a process diagram corresponding to step S101, and the step S101 corresponding to fig. 9 can be implemented in the following manner.
Firstly, a first metal oxide film layer is made of a first metal oxide material MO-1.
And then, manufacturing a second metal oxide film layer on the first metal oxide film layer by adopting a second metal oxide material MO-2.
Finally, the first metal oxide layer 101 and the second metal oxide layer 201 are formed by patterning.
Specifically, in the patterning process, a multi-layer gray-tone mask may be used to control the etching speed of different regions, and the first metal oxide layer 101 and the second metal oxide layer 201 are formed by one-step etching, where the first metal oxide layer 101 includes a first metal oxide film layer, and the second metal oxide layer 201 includes a first metal oxide film layer and a second metal oxide film layer that are stacked.
An embodiment of the present invention further provides a method for manufacturing a thin film structure in which metal oxide layers of a first metal oxide thin film transistor 10 and a second metal oxide thin film transistor 20 are located at different layers, please refer to fig. 10, and fig. 11a and 11b, where fig. 10 shows a schematic flow chart of steps of the method for manufacturing a thin film structure provided in the embodiment of the present invention, fig. 11a and 11b show process diagrams corresponding to the method for manufacturing a thin film structure of fig. 10, and the method for manufacturing a thin film structure is described in detail below with reference to fig. 11a and 11 b.
In step S201, a first metal oxide layer 101 is fabricated, wherein the first metal oxide layer 101 includes a first source region, a first channel region and a first drain region.
In this step, the first metal oxide layer 101 may be made of the first metal oxide material Mo-1 or the second metal oxide material Mo-2, and specifically, the first metal oxide layer 101 may be made on the first buffer layer 401, and before this step, the thin film structure making method may further include a step of making the first buffer layer 401 on the provided substrate layer 30.
In step S202, a first gate insulating layer 105 is formed on the first metal oxide layer 101.
In step S203, a first gate electrode 102 is formed in a region of the first gate insulating layer 105 corresponding to the first channel region.
In step S204, a first dielectric layer 501 is formed on the first gate insulating layer 105 and the first gate electrode 102, and first film vias corresponding to the first source region and the first drain region are formed on the first dielectric layer 501 and the first gate insulating layer 105, respectively.
Step S205, a first source electrode 103 and a first drain electrode 104 are formed on a side of the first dielectric layer 501 away from the first gate insulating layer 105, so that the first source electrode 103 and the first drain electrode 104 are respectively connected to the corresponding first source region and the corresponding first drain region through the first film via hole, thereby obtaining a first metal oxide thin film transistor.
In step S206, a second buffer layer 402 is formed on the first dielectric layer 501 at a side away from the first gate insulating layer 105.
In step S207, a second metal oxide layer 202 is formed on a side of the second buffer layer 402 away from the first dielectric layer 501, wherein the second metal oxide layer 202 includes a second source region, a second channel region, and a second drain region.
In this step, the second metal oxide layer 202 may be made of a metal oxide material different from that of step S201, for example, if the first metal oxide layer 101 is made of the first metal oxide material Mo-1 in step S201, the second metal oxide layer 201 is made of the second metal oxide material Mo-2 in step S207; for another example, if the first metal oxide layer 101 is formed using the second metal oxide material Mo-2 in step S201, the second metal oxide layer 201 is formed using the first metal oxide material Mo-1 in step S207.
In step S208, a second gate insulating layer 205 is formed on the second metal oxide layer 202.
In step S209, a second gate electrode 202 is formed in a region of the second gate insulating layer 205 corresponding to the second channel region.
Step S210 is to fabricate a second dielectric layer 502 on the second gate insulating layer 205 and the second gate electrode 202, and fabricate second film vias corresponding to the second source region and the second drain region respectively on the second dielectric layer 502 and the second gate insulating layer 205.
Step S211, a second source electrode 203 and a second drain electrode 204 are formed on a side of the second dielectric layer 502 away from the second gate insulating layer 205, so that the second source electrode 203 and the second drain electrode 204 are respectively connected to the second source region and the second drain region through the second film via hole, thereby obtaining a second metal oxide thin film transistor.
In an embodiment of the present application, when the first metal oxide layer 101 is made of the metal oxide material MO-1 and the second metal oxide layer 201 is made of the metal oxide material MO-2, the first metal oxide thin film transistor 10 is a switching thin film transistor and the second metal oxide thin film transistor 20 is a driving thin film transistor, please refer to fig. 5 again, the drain of the second metal oxide thin film transistor 20 may be connected to the anode film layer for controlling the pixel light emitting unit to emit light.
In one implementation manner of the embodiment of the present application, when the first metal oxide layer 101 is made of the metal oxide material MO-2 and the second metal oxide layer 201 is made of the metal oxide material MO-1, the first metal oxide thin film transistor 10 is a driving thin film transistor and the second metal oxide thin film transistor 20 is a switching thin film transistor. Referring to fig. 12, the drain of the first metal oxide thin film transistor 10 can be connected to the anode film layer for controlling the pixel light emitting unit to emit light.
In summary, the thin film structure and the method for manufacturing the thin film structure provided in the embodiment of the present application, the first metal oxide thin film transistor and the second metal oxide thin film transistor which use different metal oxide layers as active layers have different sub-critical slope values, and can be used in a pixel driving circuit of a current-driven light emitting device to meet the requirements of the different functional thin film transistors on the sub-critical slope values. Meanwhile, compared with the thin film structure manufactured by adopting the thin film transistors of different types, the thin film structure manufactured by adopting the thin film transistors of the same type can simplify the manufacturing process flow and reduce the manufacturing cost. In addition, the thin film structure has lower power consumption compared with a thin film structure consisting of an amorphous silicon thin film transistor, and has better uniformity compared with a thin film structure consisting of a low-temperature polycrystalline silicon thin film transistor.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A film structure, comprising: a first metal oxide thin film transistor and a second metal oxide thin film transistor;
the first metal oxide thin film transistor comprises a first metal oxide layer, a first gate electrode, a first source electrode, a first drain electrode and a first gate insulating layer, wherein the first metal oxide layer comprises a first source region, a first channel region and a first drain region, the first source electrode is connected with the first source region, the first drain electrode is connected with the first drain region, the first gate insulating layer is positioned on one side of the first channel region, and the first gate electrode is positioned on one side of the first gate insulating layer, which is far away from the first channel region;
the second metal oxide thin film transistor comprises a second metal oxide layer, a second gate electrode, a second source electrode, a second drain electrode and a second gate insulating layer, the second metal oxide layer comprises a second source region, a second channel region and a second drain region, the second source electrode is connected with the second source region, the second drain electrode is connected with the second drain region, the second gate insulating layer is positioned on one side of the second channel region, and the second gate electrode is positioned on one side, far away from the second channel region, of the second gate insulating layer;
the subcritical slope value of the first metal oxide thin film transistor is different from the subcritical slope value of the second metal oxide thin film transistor.
2. The thin film structure of claim 1, wherein the first metal oxide thin film transistor is a switching thin film transistor and the second metal oxide thin film transistor is a driving thin film transistor;
the subcritical slope value of the second metal oxide thin film transistor is larger than that of the first metal oxide thin film transistor.
3. The film structure of claim 2, wherein the first metal oxide layer and the second metal oxide layer comprise at least one metal oxide film layer structure;
the first metal oxide layer comprises a first metal oxide film layer structure in contact with the first grid insulating layer, and the second metal oxide layer comprises a second metal oxide film layer structure in contact with the second grid insulating layer;
the interface trap of the first metal oxide film layer structure is smaller than that of the second metal oxide film layer structure;
the difference between the subcritical slope value of the second metal oxide thin film transistor and the subcritical slope value of the first metal oxide thin film transistor is greater than or equal to 0.2V/dec.
4. The film structure of claim 3, wherein the first metal oxide film layer structure is a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure composed of at least two of indium, gallium, and zinc, and oxygen;
the second metal oxide film layer structure is a ternary metal oxide film layer structure or a quaternary metal oxide film layer structure formed by combining rare earth elements with one or two of indium elements, gallium elements and zinc elements and oxygen elements.
5. The film structure of claim 1, wherein the first metal oxide layer and the second metal oxide layer are in the same layer, the first gate electrode and the second gate electrode are made of the same metal layer, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are made of the same metal layer; or
The first metal oxide layer and the second metal oxide layer are located on different layers, the first gate electrode and the second gate electrode are made of different metal layers, and the metal layers for making the first source electrode and the first drain electrode and the metal layers for making the second source electrode and the second drain electrode are different metal layers.
6. A method of fabricating a thin film structure, the method comprising:
respectively manufacturing a first metal oxide layer and a second metal oxide layer by adopting a first metal oxide material and a second metal oxide material, wherein the first metal oxide layer comprises a first source electrode region, a first channel region and a first drain electrode region, and the second metal oxide layer comprises a second source electrode region, a second channel region and a second drain electrode region;
manufacturing a grid electrode insulating layer on the first metal oxide layer and the second metal oxide layer;
forming a first gate electrode and a second gate electrode in regions of the gate insulating layer corresponding to the first channel region and the second channel region, respectively;
manufacturing dielectric layers on the gate insulating layer, the first gate electrode and the second gate electrode, and manufacturing film layer through holes respectively corresponding to the first source region, the first drain region, the second source region and the second drain region on the dielectric layers and the gate insulating layer;
and manufacturing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on one side of the dielectric layer far away from the gate insulation layer, and respectively connecting the first source electrode area, the first drain electrode area, the second source electrode area and the second drain electrode area through the film layer through hole to obtain a first metal oxide thin film transistor and a second metal oxide thin film transistor.
7. The method of claim 6, wherein the step of forming the first metal oxide layer and the second metal oxide layer by using the first metal oxide material and the second metal oxide material respectively comprises:
manufacturing a first metal oxide film layer by adopting a first metal oxide material, and patterning the first metal oxide film layer to obtain the first metal oxide layer;
and manufacturing a second metal oxide film layer by adopting a second metal oxide material, and patterning the second metal oxide film layer to obtain the second metal oxide layer.
8. The method of claim 6, wherein the step of forming the first metal oxide layer and the second metal oxide layer by using the first metal oxide material and the second metal oxide material respectively comprises:
manufacturing a first metal oxide film layer by adopting a first metal oxide material;
manufacturing a second metal oxide film layer on the first metal oxide film layer by adopting a second metal oxide material;
and forming the first metal oxide layer and the second metal oxide layer by patterning, wherein the first metal oxide layer comprises the first metal oxide film layer, and the second metal oxide layer comprises the first metal oxide film layer and the second metal oxide film layer which are stacked.
9. A method of fabricating a thin film structure, the method comprising:
manufacturing a first metal oxide layer, wherein the first metal oxide layer comprises a first source region, a first channel region and a first drain region;
manufacturing a first grid electrode insulating layer on the first metal oxide layer;
forming a first gate electrode in a region of the first gate insulating layer corresponding to the first channel region;
manufacturing a first dielectric layer on the first gate insulating layer and the first gate electrode, and manufacturing first film layer through holes corresponding to the first source electrode region and the first drain electrode region respectively on the first dielectric layer and the first gate insulating layer;
manufacturing a first source electrode and a first drain electrode on one side of the first dielectric layer far away from the first gate insulation layer, and respectively connecting the first source electrode and the first drain electrode with the corresponding first source electrode area and the corresponding first drain electrode area through the first film layer through hole to obtain a first metal oxide thin film transistor;
manufacturing a buffer layer on one side of the first dielectric layer far away from the first grid insulation layer;
manufacturing a second metal oxide layer on one side of the buffer layer, which is far away from the first dielectric layer, wherein the second metal oxide layer comprises a second source electrode region, a second channel region and a second drain electrode region;
manufacturing a second grid electrode insulating layer on the second metal oxide layer;
forming a second gate electrode in a region of the second gate insulating layer corresponding to the second channel region;
manufacturing a second dielectric layer on the second gate insulating layer and the second gate electrode, and manufacturing second film layer through holes corresponding to the second source electrode region and the second drain electrode region respectively on the second dielectric layer and the second gate insulating layer;
and manufacturing a second source electrode and a second drain electrode on one side of the second dielectric layer far away from the second gate insulating layer, and respectively connecting the second source electrode area and the second drain electrode area through the second film layer through hole to obtain a second metal oxide thin film transistor.
10. The method of fabricating a thin film structure according to claim 9, wherein an interface trap of a first metal oxide material is larger than an interface trap of a second metal oxide material, and when the first metal oxide material is used to fabricate the first metal oxide layer and the second metal oxide material is used to fabricate the second metal oxide layer, the second metal oxide thin film transistor is a driving thin film transistor, and the first metal oxide thin film transistor is a switching thin film transistor; or the like, or, alternatively,
when the first metal oxide layer is made of the second metal oxide material and the second metal oxide layer is made of the first metal oxide material, the first metal oxide thin film transistor is a driving thin film transistor, and the second metal oxide thin film transistor is a switch thin film transistor.
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| CN101847654A (en) * | 2010-04-22 | 2010-09-29 | 友达光电股份有限公司 | Pixel structure of organic light-emitting diode display and manufacturing method thereof |
| CN102244090A (en) * | 2011-05-24 | 2011-11-16 | 友达光电股份有限公司 | Semiconductor structure and organic electroluminescent element |
| CN110323230A (en) * | 2018-03-29 | 2019-10-11 | 三星显示有限公司 | Show equipment |
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| CN101847654A (en) * | 2010-04-22 | 2010-09-29 | 友达光电股份有限公司 | Pixel structure of organic light-emitting diode display and manufacturing method thereof |
| CN102244090A (en) * | 2011-05-24 | 2011-11-16 | 友达光电股份有限公司 | Semiconductor structure and organic electroluminescent element |
| CN110323230A (en) * | 2018-03-29 | 2019-10-11 | 三星显示有限公司 | Show equipment |
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