CN114014259B - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN114014259B CN114014259B CN202111296963.7A CN202111296963A CN114014259B CN 114014259 B CN114014259 B CN 114014259B CN 202111296963 A CN202111296963 A CN 202111296963A CN 114014259 B CN114014259 B CN 114014259B
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- substrate
- layer
- barrier layer
- cavity
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 83
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000002346 layers by function Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000002131 composite material Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00182—Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00539—Wet etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
- H10N30/082—Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Micromachines (AREA)
- Weting (AREA)
Abstract
The application discloses a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate with an annular groove; forming a barrier layer on the upper surface of the substrate, wherein the annular groove is filled with the barrier layer; forming a functional layer over the barrier layer; the lower surface of the substrate is etched to form a cavity, until the functional layer is reached, the etching is stopped. The upper vertex angle of the cavity which can be obtained based on the method is close to 90 degrees, so that the consistency of the functional layer above the cavity is maintained. In addition, the cavity sizes of the middle area and the edge area of the wafer are relatively consistent, so that the consistency of each semiconductor structure of the wafer is improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor structure.
Background
The basic structure of the piezoelectric microphone comprises a vibration composite membrane layer and a cavity below the vibration composite membrane layer. The size of the cavity affects the sensitivity and resonant frequency of the piezoelectric microphone. In the actual process, the difference in the process uniformity in the wafer surface causes the difference in the cavity size at the middle area and the edge area of the wafer, so that the uniformity of the whole device of the wafer is seriously affected, and the later detection cost of the device of the wafer is greatly increased.
Disclosure of Invention
Aiming at the problems in the related art, the application provides a manufacturing method of a semiconductor structure, which can obtain cavities with uniform size and is beneficial to improving the uniformity of the whole device of a wafer.
The technical scheme of the application is realized as follows:
According to one aspect of the present application, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a substrate with an annular groove;
forming a barrier layer on the upper surface of the substrate, wherein the annular groove is filled with the barrier layer;
Forming a functional layer over the barrier layer;
the lower surface of the substrate is etched to form a cavity, until the functional layer is reached, the etching is stopped.
Wherein the method of forming the barrier layer comprises: the substrate is thermally oxidized to form the barrier layer.
The material of the substrate comprises silicon, and the material forming the barrier layer after thermal oxidation comprises silicon oxide.
Wherein the thickness of the silicon oxide is 0.1um to 3um.
Wherein the step of forming the barrier layer comprises: and forming a metal layer on the upper surface of the substrate, wherein the metal layer fills the annular groove.
Wherein the material of the metal layer comprises aluminum, tungsten, copper and gold.
Wherein the step of forming a functional layer over the barrier layer comprises:
and a supporting layer, a first electrode layer, a piezoelectric layer and a second electrode layer are sequentially formed above the barrier layer.
Wherein the step of etching the lower surface of the substrate to form a cavity comprises:
photoetching and deep silicon etching until the lower surface of the exposed barrier layer is flush with the upper surface of the substrate;
the functional layer is further wet etched until the functional layer is exposed, thereby forming the cavity.
Wherein the sidewalls of the barrier layer are exposed within the cavity.
The application utilizes the materials of the barrier layer and the substrate to have different etching selection ratios, and the upper vertex angle of the cavity which can be obtained after photoetching, deep silicon etching and wet etching is close to 90 degrees, thereby being beneficial to keeping the consistency of the functional layer above the cavity. In addition, the cavity sizes of the middle area and the edge area of the wafer are relatively consistent, so that the consistency of each semiconductor structure of the wafer is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1-5 illustrate schematic diagrams of intermediate stages of a method of manufacturing a semiconductor structure provided in accordance with some embodiments.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the application, fall within the scope of protection of the application.
Referring to fig. 1, according to an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, which can form cavities 12 with regular shapes, specifically, each upper apex angle of the cavities 12 is close to 90 degrees, so as to facilitate the uniformity of a functional layer above the cavities 12. The semiconductor structure includes a MEMS (Micro-Electro-MECHANICAL SYSTEM, i.e., microelectromechanical system) structure having a cavity 12, such as a piezoelectric MEMS microphone, piezoelectric MEMS speaker, or other MEMS sensor or actuator. The method of fabricating the semiconductor structure will be described in detail below.
Referring to fig. 1, a substrate 10 having an annular groove 11 is provided at step S101. The substrate 10 comprises silicon or any suitable silicon-based compound or derivative (e.g., silicon wafer, SOI, polysilicon on SiO 2/Si). The annular groove 11 may be formed by an etching step.
Referring to fig. 2, a barrier layer 20 is formed on the upper surface of the substrate 10, and the barrier layer 20 fills the annular groove 11 at step S102. In some embodiments, silicon oxide may be formed by thermally oxidizing the silicon material of the substrate 10, which acts as the barrier layer 20. The thickness of the silicon oxide is 0.1um to 3um. Preferably, the thickness of the silicon oxide is 0.5um to 2um. In some embodiments, a metal layer may be formed on the upper surface of the substrate 10, the metal layer filling the annular groove 11. The metal layer serves as a barrier layer 20. The material of the metal layer comprises aluminum, tungsten, copper and gold. Methods of forming the metal layer include deposition, sputtering, or other suitable methods.
Referring to fig. 3, step S103, a functional layer is formed over the barrier layer 20. The functional layers include a support layer 30, a first electrode layer 40, a piezoelectric layer 50, and a second electrode layer 60. The specific method for forming the functional layer is as follows:
A support layer 30 is formed over the substrate 10. The support layer 30 comprises a single-layer or multi-layer composite film structure of silicon nitride (Si 3N 4), silicon oxide, single crystal silicon, polysilicon, or other suitable support material. Preferably, the thickness of the support layer 30 is 0.4um to 3um.
A first electrode layer 40 is formed over the support layer 30.
A piezoelectric layer 50 is formed over the first electrode layer 40.
A second electrode layer 60 is formed over the piezoelectric layer 50. The piezoelectric layer 50 may convert the applied pressure into a voltage, and the first electrode layer 40 and the second electrode layer 60 may transmit the generated voltage to other integrated circuit devices. In some embodiments, piezoelectric layer 50 includes zinc oxide, aluminum nitride, an organic piezoelectric film, lead zirconate titanate (PZT), a perovskite-type piezoelectric film, or other suitable material. The first electrode layer 40 and the second electrode layer 60 comprise a composite film of aluminum, gold, platinum, molybdenum, titanium, chromium, or other suitable material. Preferably, the thickness of the first electrode layer 40 is 0.05um to 0.5um, the thickness of the piezoelectric layer 50 is 0.4um to 3um, and the thickness of the second electrode layer 60 is 0.05um to 0.5um.
Referring to fig. 4, the lower surface of the substrate 10 is etched to form the cavity 12 until the etching is stopped when the functional layer is reached at step S104. Specifically, the step S104 includes:
photolithography and deep silicon etching until the lower surface of the exposed barrier layer 20 is flush with the upper surface of the substrate 10; referring to fig. 5, the wet etching is further performed until the functional layer, specifically the support layer 30, is exposed, thereby forming the cavity 12.
Notably, the sidewalls of the annular barrier 20 are exposed within the cavity 12. When the barrier layer 20 is not used in the method of manufacturing a semiconductor structure, the upper top corner of the cavity 12 (i.e., the junction between the cavity 12 and the functional layer) obtained after deep silicon etching is generally acute or obtuse, which is not beneficial to obtaining a functional layer with good uniformity. In addition, the cavities 12 at the middle region and the edge region of the wafer are also prone to non-uniformity in the size of the cavities 12 at the middle region and the edge region due to the different etch rates. The present application utilizes the different etch selectivity of the barrier layer 20 and the material of the substrate, and the top corner of the cavity 12 that can be obtained after photolithography, deep silicon etching and wet etching is close to 90 degrees, thereby facilitating the maintenance of the uniformity of the functional layer over the cavity 12. Moreover, the cavity 12 in the middle and edge regions of the wafer are relatively uniform in size, which is advantageous for improving the uniformity of the individual semiconductor structures of the wafer.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the application.
Claims (6)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate with an annular groove;
forming a barrier layer on the upper surface of the substrate, wherein the barrier layer fills the annular groove and comprises the following steps: thermally oxidizing the substrate to form the barrier layer, wherein the material of the substrate comprises silicon, and the material forming the barrier layer after thermal oxidation comprises silicon oxide;
Forming a functional layer over the barrier layer;
Etching the lower surface of the substrate to form a cavity until reaching the functional layer, comprising: photoetching and deep silicon etching until the lower surface of the exposed barrier layer is flush with the upper surface of the substrate; and further wet etching until the functional layer is exposed, so that a cavity with an upper apex angle close to 90 degrees is formed by using different etching selectivity ratios of the materials of the barrier layer and the substrate.
2. The method of claim 1, wherein the silicon oxide has a thickness of 0.1um to 3um.
3. A method of fabricating a semiconductor structure, comprising:
providing a substrate with an annular groove;
Forming a barrier layer on the upper surface of the substrate, wherein the barrier layer fills the annular groove and comprises the following steps: forming a metal layer on the upper surface of the substrate, wherein the metal layer fills the annular groove;
Forming a functional layer over the barrier layer;
Etching the lower surface of the substrate to form a cavity until reaching the functional layer, comprising: photoetching and deep silicon etching until the lower surface of the exposed barrier layer is flush with the upper surface of the substrate; and further wet etching until the functional layer is exposed, so that a cavity with an upper apex angle close to 90 degrees is formed by using different etching selectivity ratios of the materials of the barrier layer and the substrate.
4. A method of fabricating a semiconductor structure according to claim 3, wherein the material of the metal layer comprises aluminum, tungsten, copper, gold.
5. A method of fabricating a semiconductor structure according to claim 1 or 3, wherein the step of forming a functional layer over the barrier layer comprises:
and a supporting layer, a first electrode layer, a piezoelectric layer and a second electrode layer are sequentially formed above the barrier layer.
6. A method of fabricating a semiconductor structure according to claim 1 or 3, wherein the sidewalls of the barrier layer are exposed within the cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111296963.7A CN114014259B (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111296963.7A CN114014259B (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
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| Publication Number | Publication Date |
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| CN114014259A CN114014259A (en) | 2022-02-08 |
| CN114014259B true CN114014259B (en) | 2024-07-19 |
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| CN202111296963.7A Active CN114014259B (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117641215B (en) * | 2024-01-25 | 2024-04-16 | 镭友芯科技(苏州)有限公司 | Microphone sensor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896518A (en) * | 2019-12-17 | 2020-03-20 | 安徽奥飞声学科技有限公司 | Manufacturing method of MEMS structure |
| CN111620300A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Device with back cavity structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080061309A1 (en) * | 2006-07-21 | 2008-03-13 | Young Sir Chung | Semiconductor device with under-filled heat extractor |
| US10651081B2 (en) * | 2018-09-21 | 2020-05-12 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| CN110113703B (en) * | 2019-05-18 | 2021-01-12 | 安徽奥飞声学科技有限公司 | Preparation method of MEMS structure |
| CN110460942B (en) * | 2019-08-06 | 2024-03-15 | 安徽奥飞声学科技有限公司 | MEMS structure and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896518A (en) * | 2019-12-17 | 2020-03-20 | 安徽奥飞声学科技有限公司 | Manufacturing method of MEMS structure |
| CN111620300A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Device with back cavity structure and forming method thereof |
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| CN114014259A (en) | 2022-02-08 |
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