CN103985723A

CN103985723A - Packaging method and packaging structures

Info

Publication number: CN103985723A
Application number: CN201410214061.8A
Authority: CN
Inventors: 王之奇; 喻琼; 王蔚
Original assignee: China Wafer Level CSP Co Ltd
Current assignee: China Wafer Level CSP Co Ltd
Priority date: 2014-05-20
Filing date: 2014-05-20
Publication date: 2014-08-13
Anticipated expiration: 2034-05-20
Also published as: CN103985723B

Abstract

The invention discloses a packaging method and packaging structures. The packaging method includes the steps of providing a plurality of individual image sensing chips, wherein each image sensing chip is provided with an image sensing area and a bonding pad surrounding the image sensing area; providing a PCB substrate, wherein a metal layer is formed on the surface of the PCB substrate; reversedly arranging the image sensing chips on the PCB substrate, wherein the bonding pads are electrically connected with the metal layer; forming a plastic sealing layer which covers the surface of the metal layer and the surfaces of the image sensing chips; forming a through hole, exposed out of the surface of the metal layer, in the plastic sealing layer; forming a welding protrusion which fully fills the through hole, wherein the top of the welding protrusion is higher than the surface of the plastic sealing layer; cutting the PCB substrate along the area of cutting lines to form the multiple single packaging structures. The packaging process is simple, the packaging structures have good packaging performance and high reliability, the packaging process can be partly conducted through the PCB manufacturing technology, and packaging process difficulty and packaging cost are reduced.

Description

Method for packing and encapsulating structure

Technical field

The present invention relates to semiconductor packaging, particularly a kind of method for packing and encapsulating structure.

Background technology

Image sensor is a kind of transducer that can experience extraneous light and convert thereof into the signal of telecommunication.After image sensor dice completes, then by image sensor dice is carried out to a series of packaging technologies, thereby form packaged image sensor, for the various electronic equipments such as digital camera, Digital Video etc.

Traditional image sensor package method normally adopts Bonding (Wire Bonding) to encapsulate, but the develop rapidly along with integrated circuit, longer lead-in wire makes product size cannot reach desirable requirement, therefore, wafer-level packaging (WLP:Wafer Level Package) replaces wire bond package gradually becomes a kind of comparatively conventional method for packing.

As shown in Figure 1, Fig. 1 is a kind of encapsulating structure, comprising: substrate 101; Be positioned at the embankment structure 102 on substrate 101 surfaces; The image sensing chip 100 of upside-down mounting above substrate 101, image sensing chip 100 fronts have video sensing district 103 and around the pad 104 in described video sensing district 103, and described pad 104 upper surfaces contact with embankment structure 102 surfaces; Be positioned at the through hole of described image sensing chip 100, described through hole exposes pad 104 lower surfaces; Be positioned at the protective layer 105 at through-hole side wall and image sensing chip 100 back sides, and expose pad 104 lower surfaces of via bottoms; Be positioned at the metal redistribution layer 106 at through-hole side wall and image sensing chip 100 back sides; Be positioned at the insulating barrier 107 on described metal redistribution layer surface; Be positioned at the opening of described insulating barrier 107, and described opening exposes metal redistribution layer 106; Be positioned at the solder-bump 108 of described opening.

Yet the encapsulation performance of above-mentioned encapsulating structure needs further to be improved, and it is comparatively complicated to form the packaging technology of above-mentioned encapsulating structure.

Summary of the invention

The problem that the present invention solves is to provide a kind of method for packing and encapsulating structure, improves encapsulation performance and reliability.

For addressing the above problem, the invention provides a kind of method for packing, comprising: some single image sensing chips are provided, and described image sensing chip has video sensing district and around the pad in described video sensing district; PCB substrate is provided, and described PCB substrate comprises some functional areas and the Cutting Road region between adjacent functional district, and surface, described PCB functional substrate district is formed with metal level; Described image sensing flip-chip is placed in to the top in PCB functional substrate district, and described pad and metal level electrical connection; Formation is covered in the plastic packaging layer of described layer on surface of metal and image sensing chip surface; In described plastic packaging layer, form through hole, described via bottoms exposes layer on surface of metal; Form the solder-bump of filling full described through hole, and described solder-bump top is higher than plastic packaging layer surface; Along described Cutting Road region, cut described PCB substrate, form some single encapsulating structures.

Optionally, in described PCB substrate, form the hole that runs through PCB substrate, and video sensing district is positioned at above hole after pad and metal level electrical connection.

Optionally, adopt punching press or bore process to form described hole.

Optionally, after forming described metal level, at PCB substrate back, form adhesive tape layer, adhesive tape layer sealing described hole one end.

Optionally, the material of described adhesive tape layer is UV dispergation rubber belt material, pyrolysis glue rubber belt material, IR glass or AR glass.

Optionally, described metal level is covered in PCB functional substrate district and Cutting Road area surfaces.

Optionally, described plastic packaging layer is covered in the metal level sidewall surfaces of same functional areas.

Optionally, the material of described metal level is Cu, Al, W, Sn, Au or Sn-Au alloy.

Optionally, the formation step of described some single image sensing chips comprises: wafer to be wrapped is provided, has some video sensings district and around the pad in described video sensing district in described wafer to be wrapped; Cut described wafer to be wrapped, form some single image sensing chips.

Optionally, before the described wafer to be wrapped of cutting, also comprise step: described wafer to be wrapped is carried out to reduction processing.

Optionally, also comprise step: in described bond pad surface or layer on surface of metal, form metal coupling, described pad and metal level are electrically connected to by metal coupling.

Optionally, the material of described metal coupling is tin, gold or ashbury metal.

Optionally, adopt solder bonds technique that pad is connected with metal level, wherein, solder bonds technique is eutectic bonding, ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding.

Optionally, the material of described plastic packaging layer is epoxy resin or acrylic resin.

Optionally, the processing step that forms solder-bump comprises: form the metal material of filling full described through hole, adopt reflux technique, form described solder-bump.

Optionally, the distance at described solder-bump top to plastic packaging layer top is 20 μ m to 100 μ m.

Optionally, adopt etching or laser drilling technique to form described through hole.

Accordingly, the present invention also provides a kind of encapsulating structure, comprising: PCB substrate; Be positioned at the metal level of described PCB substrate surface; The image sensing chip of upside-down mounting above PCB substrate, described image sensing chip has video sensing district and around the pad in described video sensing district, and described pad and metal level are electrically connected to; Be positioned at the plastic packaging layer of described layer on surface of metal and image sensing chip surface; Be positioned at the through hole of described plastic packaging layer, and described through hole exposes layer on surface of metal; Fill the solder-bump of full described through hole, described solder-bump top is higher than plastic packaging layer surface.

Optionally, in described PCB substrate, there is the hole that runs through PCB substrate, and video sensing district is positioned at hole top.

Optionally, the width of described hole is more than or equal to the width in video sensing district.

Optionally, also comprise: metal coupling, described metal coupling, between pad and metal level, is electrically connected to described pad and metal level by described metal coupling.

Optionally, described metal level sidewall flushes with PCB substrate sidewall.

Optionally, described plastic packaging layer is covered in metal level sidewall surfaces.

Optionally, described PCB substrate back is formed with adhesive tape layer, one end of adhesive tape layer sealing described hole.

The present invention also provides a kind of method for packing, comprising: some single image sensing chips are provided, and described image sensing chip has video sensing district and around the pad in described video sensing district; PCB substrate is provided, and described PCB substrate comprises some functional areas and the Cutting Road region between adjacent functional district, and surface, described PCB functional substrate district is formed with metal level; Described image sensing flip-chip is placed in to the top in PCB functional substrate district, and described pad and metal level electrical connection; At described layer on surface of metal, form solder-bump, and described solder-bump top is higher than image sensing chip surface; Along described Cutting Road region, cut described PCB substrate, form some single encapsulating structures.

Optionally, also comprise step: form the some glue-line that is covered in described image sensing chip side wall surface.

Optionally, the some glue-line of formation is also covered in metal coupling sidewall surfaces.

Optionally, form the hole run through PCB substrate in described PCB substrate, after image sensing flip-chip being placed in above PCB functional substrate district, video sensing district is positioned at hole top.

Accordingly, the present invention also provides a kind of encapsulating structure, comprising: PCB substrate; Be positioned at the metal level of described PCB substrate surface; The image sensing chip of upside-down mounting above PCB substrate, described image sensing chip has video sensing district and around the pad in described video sensing district, and described pad and metal level are electrically connected to; Be positioned at the solder-bump of described layer on surface of metal, and described solder-bump top is higher than image sensing chip surface.

Optionally, also comprise: also comprise: metal coupling, described metal coupling, between pad and metal level, is electrically connected to described pad and metal level by described metal coupling.

Optionally, also comprise: the some glue-line that is covered in described image sensing chip side wall surface and metal coupling sidewall surfaces.

Optionally, in described PCB substrate, have the hole that runs through described PCB substrate, video sensing district is positioned at hole top.

Compared with prior art, technical scheme provided by the invention has the following advantages:

The embodiment of the present invention provides a kind of method for packing, and packaging technology is simple, and some single image sensing chips are provided; PCB substrate is provided, and surface, described PCB functional substrate district is formed with some discrete metal levels; Described image sensing flip-chip is placed in to the top of PCB substrate, and described pad is connected with metal level; Formation is covered in the plastic packaging layer of described layer on surface of metal and image sensing chip surface; In described plastic packaging layer, form through hole, described via bottoms exposes layer on surface of metal; Form the solder-bump of filling full through hole, and solder-bump top is higher than plastic packaging layer surface; Along described Cutting Road region, cut described PCB substrate, form some single encapsulating structures.The present invention is by forming the metal level being connected with pad at PCB substrate surface, in plastic packaging layer, form the through hole that exposes metal level, the solder-bump that the metal level that formation exposes with described through hole is electrically connected to, by described solder-bump, encapsulating structure territory external circuit is electrically connected to, therefore, embodiment of the present invention packaging technology is simple, and act on encapsulation procedure on image sensing chip seldom, make image sensing chip keep preferably performance, thereby the encapsulation yield that improves the encapsulating structure forming, encapsulation performance and reliability effectively improve.

Meanwhile, because the present embodiment forms encapsulating structure on the basis of PCB substrate, therefore, part packaging technology can adopt PCB making technology to carry out, and for example, adopts PCB making technology to form metal level on PCB substrate, adopt PCB making technology to form plastic packaging layer, thereby reduce packaging cost; And cheap due to PCB substrate, can further effectively reduce packaging cost.

And in the embodiment of the present invention, PCB substrate can have very large area, therefore it is more that upside-down mounting is placed in the quantity of image sensing chip of PCB substrate top, a packaging technology in the cycle, and can the very large encapsulating structure of quantity of formation, effectively improve packaging efficiency, shorten packaging time.

Further, in the embodiment of the present invention, in PCB substrate, form the hole that runs through described PCB substrate, and after pad is connected with metal level, video sensing district is positioned at the top of hole, and extraneous light is transmitted to video sensing district by described hole, and encapsulating structure is converted into electrical signal by light signal.

Further, in the embodiment of the present invention, at PCB substrate back, form adhesive tape layer, one end of described adhesive tape layer sealing described hole, therefore when image sensing flip-chip is placed in behind PCB substrate top, video sensing district is positioned at the cavity forming between PCB substrate and adhesive tape layer, can avoid follow-up packaging technology to cause harmful effect to video sensing district, further improves the encapsulation performance of encapsulating structure.The material of described adhesive tape layer is UV dispergation adhesive tape or pyrolysis glue adhesive tape, and follow-up after forming single encapsulating structure, the mode of being irradiated or being heated by UV, can be separated with encapsulating structure by adhesive tape layer, and packaging technology is simple.

Further, in the embodiment of the present invention, before cutting wafer to be wrapped, also comprise step: the second face to wafer to be wrapped carries out reduction processing, makes the thinner thickness of image sensing chip, and, due to after forming single image sensing chip, the encapsulation procedure that image sensing chip is carried out is few, image sensing chip need to not keep relatively thick thickness in order to have compared with strong mechanical strength, therefore, compared with prior art, after embodiment of the present invention attenuate wafer to be wrapped, the thickness of the wafer to be wrapped after attenuate is significantly less than the thickness of wafer to be wrapped in prior art, the thickness of the encapsulating structure forming is on this basis significantly less than the thickness of the encapsulating structure of prior art formation, be conducive to meet semiconductor miniaturization, microminiaturized development trend.

Further, at layer on surface of metal, form metal coupling, avoid forming in bond pad surface the harmful effect that metal coupling may cause image sensing chip, further reduced the encapsulation procedure of image sensing chip experience itself, make image sensing chip keep preferably performance, thereby further improve the encapsulation performance of encapsulating structure.

Further, form the metal material of filling full described through hole, adopt reflux technique, form described solder-bump, not only further reduced packaging technology step, make packaging technology simpler; And solder-bump top is very little to the distance on plastic packaging layer surface, be 20 μ m to 100 μ m, the solder-bump sidewall surfaces forming is almost all covered by plastic packaging layer, reduce solder-bump and be exposed to the area in external environment, thereby reduced greatly the possibility that solder-bump is oxidized or damages by external environment, effectively improve the reliability and stability of encapsulating structure, and can further reduce the thickness of encapsulating structure.

Further again, plastic packaging layer is positioned at metal level sidewall surfaces, be that plastic packaging layer is covered in metal level sidewall surfaces, after Cutting Road region cutting PCB substrate, form in encapsulating structure, metal level sidewall surfaces is covered by plastic packaging layer, prevent that metal level and external circuit from unnecessary being electrically connected to occurring, prevent that external environment from causing oxidation equivalent damage to metal level simultaneously, improve the reliability and stability of encapsulating structure.

The embodiment of the present invention also provides the encapsulating structure that a kind of structural behaviour is superior, comprises the image sensing chip of upside-down mounting above PCB substrate, and the metal level of pad and PCB substrate surface is electrically connected to; Be positioned at the plastic packaging layer of described layer on surface of metal and image sensing chip surface; Be positioned at the through hole of described plastic packaging layer, and described through hole exposes layer on surface of metal; Fill the solder-bump of full described through hole.In encapsulating structure, through hole is positioned at plastic packaging layer, and via bottoms exposes layer on surface of metal, the metal level exposing with via bottoms by solder-bump is connected, encapsulating structure is electrically connected to external circuit, reduced damage and pollution that image sensing chip is subject to, therefore, the encapsulation performance of the encapsulating structure that the embodiment of the present invention provides is superior.

Further, solder-bump is filled full described through hole, and the top of described solder-bump is very little to the distance on plastic packaging layer surface, be 20 μ m to 100 μ m, the most of sidewall surfaces of therefore described solder-bump is enveloped by plastic packaging layer, reduce solder-bump and be exposed to the area in external environment, thereby reduced the possibility that solder-bump is caused oxidation or pollutes by external environment, improved stability and the reliability of encapsulating structure; And because solder-bump top is very little to the distance on plastic packaging layer surface, so the encapsulating structure that the embodiment of the present invention provides has thinner thickness, meet semiconductor miniaturization, microminiaturized development trend.

Further again, described plastic packaging layer is covered in metal level sidewall surfaces, prevents that metal level sidewall is exposed in external environment, avoids metal level and external environment that unnecessary being electrically connected to occurs, prevent that metal level is by external environmental simultaneously, further improve stability and the reliability of encapsulating structure.

Further, in PCB substrate, there is the hole that runs through described PCB substrate, described video sensing district is positioned at hole top, make video sensing district receive extraneous light by described hole, and hole width is greater than video sensing sector width, improve the utilance of video sensing district to light, thereby improve the performance of encapsulating structure.

The embodiment of the present invention also provides a kind of method for packing, after image sensing flip-chip being placed in above PCB substrate, at layer on surface of metal, form solder-bump, by described solder-bump, image sensing chip is electrically connected to external circuit, packaging technology is simple, and the encapsulation procedure of image sensing chip experience itself is few, makes image sensing chip have higher performance, the encapsulation performance of the encapsulating structure therefore forming is good, reliability is high.

Further, the embodiment of the present invention forms the some glue-line that is covered in image sensing chip side wall surface, and described some glue-line prevents that external environment from causing harmful effect to image sensing chip, further improves the reliability of the encapsulating structure forming.

The embodiment of the present invention also provides a kind of simple in structure and well behaved encapsulating structure, comprising: PCB substrate; Be positioned at the metal level of described PCB substrate surface; The image sensing chip of upside-down mounting above PCB substrate, described image sensing chip has video sensing district and around the pad in described video sensing district, and described pad and metal level are electrically connected to; Be positioned at the solder-bump of described layer on surface of metal, and described solder-bump top is higher than image sensing chip surface.By solder-bump, encapsulating structure is electrically connected to external circuit, has reduced damage and pollution that image sensing chip is subject to, therefore, the encapsulation performance of the encapsulating structure that the embodiment of the present invention provides is superior.

Accompanying drawing explanation

Fig. 1 is the cross-sectional view of prior art encapsulating structure;

The structural representation of the encapsulating structure forming process that Fig. 2 to Figure 15 provides for one embodiment of the invention;

The structural representation of the encapsulating structure forming process that Figure 16 to Figure 20 provides for another embodiment of the present invention;

Figure 21 to Figure 23 is the cross-sectional view of further embodiment of this invention image sensor package process.

Embodiment

From background technology, encapsulation performance and the reliability of the encapsulating structure that prior art provides have much room for improvement, and the technique that forms above-mentioned encapsulating structure is comparatively complicated, and packaging cost is higher.

Find after deliberation, the reason that the encapsulation performance of encapsulating structure and reliability have much room for improvement is:

First; the packaging technology that forms aforementioned encapsulating structure is very complicated; and in encapsulation process; image sensing chip experience attenuate, etching form through hole, form protective layer, form metal level, form the multiple tracks encapsulation procedures such as insulating barrier; described encapsulation procedure causes harmful effect to the performance of image sensing chip, causes the encapsulating structure performance of formation to be difficult to reach optimum state.

Secondly, because image sensing chip need to experience etching, form through hole, form the multiple tracks encapsulation procedures such as metal level, described image sensing chip must have higher mechanical strength, prevents that image sensing chip from breaking in described encapsulation procedure process; For guaranteeing the mechanical strength of image sensing chip, image sensing chip need to keep thicker thickness, thereby causes the encapsulating structure thickness of formation partially thick, is unfavorable for the development trend of semiconductor device miniaturization, microminiaturization.

And, image sensing chip yield level in wafer differs, while adopting packaging technology to form above-mentioned encapsulating structure, that monoblock wafer is encapsulated to the encapsulating structure that rear cutting crystal wafer forms, the encapsulation yield of the encapsulating structure forming on the basis of the poor image sensing chip of yield does not obviously meet technological standards yet, causes the waste of packaging cost.

For this reason, the invention provides a kind of method for packing and encapsulating structure, some single image sensing chips are provided, described image sensing chip has video sensing district and around the pad in described video sensing district; PCB substrate is provided, and PCB substrate surface is formed with metal level; Image sensing flip-chip is placed in to the top of PCB substrate, and pad and metal level electrical connection; Formation is covered in the plastic packaging layer of layer on surface of metal and image sensing chip surface; In plastic packaging layer, form the through hole that exposes layer on surface of metal; Form the solder-bump of filling full described through hole, and described solder-bump top is higher than plastic packaging layer surface; Along Cutting Road region cutting PCB substrate, form some single encapsulating structures.Packaging technology of the present invention is simple, and the encapsulation procedure of image sensing chip experience itself is few, makes encapsulating structure have good encapsulation performance and reliability, and the thinner thickness of encapsulating structure.

For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.

The structural representation of the encapsulation process that Fig. 2 to Figure 18 provides for the embodiment of the present invention.

Please refer to Fig. 2 and Fig. 3, Fig. 3 is that Fig. 2 is along the cut-away section structural representation of line of cut AA1 direction, wafer to be wrapped 200 is provided, described wafer to be wrapped 200 have first surface with relative with described first surface second, the first surface of described wafer to be wrapped 200 is formed with some video sensings district 201 and around the pad 202 in described video sensing district 201.

In this enforcement, described wafer to be wrapped 200 comprises the some chip area 210 of matrix arrangement and the first Cutting Road regions 220 between chip area 210 of being, described chip area 210 is used to form image sensor dice, follow-uply along 220 pairs, the first Cutting Road region wafer to be wrapped 200, cut and form several discrete crystal grain, each crystal grain is corresponding forms an image sensing chip.

Chip area 210 first surfaces of described wafer to be wrapped 200 have video sensing district 201 and around the pad 202 in described video sensing district 201, described chip area 210 is also formed with the metal interconnect structure (not shown) of video sensing district 201 and pad 202 electrical connections, in described video sensing district 201, be formed with image sensor unit and the associated circuit being connected with image sensor unit, video sensing district 201 receives and converts to electrical signal by extraneous light, and by described electrical signal by metal interconnect structure and pad 201, and the metal level of follow-up formation, send external circuit to.

In the present embodiment, as shown in Figure 4, Fig. 4 is the plan structure schematic diagram in one single chip region 210, for the ease of wiring, video sensing district 201 is positioned at the centre position in one single chip region 210, pad 202 is positioned at the marginal position of chip area 210, and described pad 202 is positioned at four sides in video sensing district 201, rectangular distribution, each side is formed with several pads 202 (quantity of pad 202 depends on the type of chip), follow-up pad 202 is connected with metal level, by metal level, image sensor dice is connected with external circuit.

It should be noted that, in other embodiments, the position in pad 202He video sensing district 201 can be adjusted flexibly according to the requirement of actual process, for example, in the present embodiment, pad is positioned at four sides in video sensing district 201, in other embodiments, pad and the side, both sides or three sides that are positioned at video sensing district, and the quantity of the pad of each side can be adjusted flexibly according to the requirement of actual process.

In the present embodiment, the pad 202 of different chip areas 210 is independent setting; In other embodiments, in adjacent chip area, can form the pad being connected, the pad forming is crossed over the first Cutting Road region, due to follow-up cutting wafer to be wrapped after, the pad in described leap the first Cutting Road region can be cut to be held, and therefore can not affect the electric property of image sensing chip.

Please refer to Fig. 5, on described pad 202 surfaces, form metal coupling 203.

The top of described metal coupling 203 is higher than the top of video sensing district 201 interior photo-sensitive cells.

Acting as of described metal coupling 203: on the one hand, by described metal coupling 203, pad 202 is electrically connected to the metal level of follow-up formation; On the other hand; by the top of described metal coupling 203 being set higher than the top in video sensing district 201, follow-up when pad 202 is electrically connected to metal level, prevent that the surface of metal level from encountering video sensing district 201; play the effect in protection video sensing district 201, thereby improve encapsulation yield.

Being shaped as of described metal coupling 203 is square or spherical.The present embodiment take that being shaped as of described metal coupling 203 is square does exemplary illustrated as example, and the formation technique of described metal coupling 203 is screen printing technique.

As an embodiment, employing screen printing technique forms the concrete process of described metal coupling 203 and is: provide tool meshed web plate, described mesh corresponding with the position of metal coupling 203 (that is, the position of described network interface card is corresponding with the position of pad 202); By the first surface laminating of web plate and wafer to be wrapped 200, make mesh in web plate expose the surface of pad 202, in mesh, brush into materials such as gold, tin or ashbury metals, remove the meshed half tone of described tool, on pad 202 surfaces, form metal couplings 203.

The material of described metal coupling 203 can be gold, tin or ashbury metal, and described ashbury metal can be plumbous for tin silver, tin, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony etc.

In other embodiments, being shaped as when spherical of metal coupling, the formation technique of described metal coupling is: plant ball technique or screen printing and reflux technique.

It should be noted that, in the present embodiment, before being carried out to reduction processing, wafer to be wrapped 200 second faces form described metal coupling 203, because the thicker wafer to be wrapped 200 that makes of thickness of wafer to be wrapped 200 has extraordinary mechanical strength, thereby avoid the technical process that forms metal coupling 203 to cause wafer to be wrapped 200 to occur the problem of breaking; And, before attenuate wafer to be wrapped 200, form metal coupling 203, the encapsulation procedure of wafer to be wrapped 200 experience after attenuate is tailed off, therefore, can further reduce the thickness that the rear wafer to be wrapped 200 of follow-up attenuate wafer to be wrapped 200 has, make the thickness of encapsulating structure of follow-up formation thinner, be more conducive to meet semiconductor miniaturization, microminiaturized development trend.

In another embodiment of the present invention, also can carry out after reduction processing wafer to be wrapped the second face, in bond pad surface, form metal coupling.

Please refer to Fig. 6, the second face of described wafer to be wrapped 200 is carried out to reduction processing.

Concrete, the back side of grinding described wafer to be wrapped 200, until the thickness of wafer to be wrapped 200 is to predetermined thickness, described grinding can be mechanical lapping or cmp.

For example, because second of wafer to be wrapped 200 (is not generally formed with function element, pad and video sensing district), therefore, the second face to wafer to be wrapped 200 carries out attenuate to a certain degree, both the performance that had guaranteed wafer to be wrapped 200 interior function element is not affected, and can make the thinner thickness of the encapsulating structure of follow-up formation yet.

And, follow-uply in the present embodiment can not carry out the technique that etching forms through hole to wafer to be wrapped 200 the image sensing chip of single (arbitrarily), the follow-up manufacturing process that image sensing chip is carried out itself is less, therefore, image sensing chip does not need to have very high mechanical strength, after attenuate wafer to be wrapped 200, image sensing chip can have less predetermined thickness, makes the thickness of encapsulating structure of follow-up formation thin as much as possible.

And in prior art, after attenuate wafer to be wrapped, rear extended meeting etching wafer to be wrapped is to form the through hole that exposes pad, therefore, the wafer to be wrapped after attenuate need to have larger predetermined thickness, so that wafer to be wrapped has enough mechanical strengths, prevent the problem of image sensing chip rupture, therefore, prior art is after packaging technology completes, and the image sensing chip-packaging structure of formation has thicker thickness.

Please refer to Fig. 7, along the described wafer to be wrapped 200 of described the first Cutting Road region 220 cutting, form some single image sensing chips 230.

Described cutting technique is laser cutting or slicer cutting.Because laser cutting parameter has less kerf width, therefore, in the present embodiment, adopt laser cutting parameter to cut described wafer to be wrapped 200, form some single image sensing chips 230.

In wafer to be wrapped 200, there is the image sensing chip 230 that some matrixes are arranged, in these image sensing chips 230, may there is the poor image sensing chip 230 of some yields, the performance of the image sensing chip 230 that described yield is poor does not reach design requirement, if the image sensing chip 230 poor to these yields encapsulates, the encapsulating structure forming is also difficult to drop in practical application, therefore, the image sensing chip 230 poor to yield encapsulates the waste that both can cause packaging cost, also can cause packaging efficiency low.

And in the present embodiment, at cutting wafer to be wrapped 200, form after some single image sensing chips 220, selecting the image sensing chip 230 that yield meets technological standards carries out follow-up packaging technology, avoids the waste of packaging cost and improves packaging efficiency.

Please refer to Fig. 8, PCB substrate 204 is provided, described PCB substrate 204 comprises some functional areas 240 and the second Cutting Road region 250 between adjacent functional district 240.

Follow-up above described PCB substrate 204 functional areas 240 upside-down mounting image sensing chip 230 is set, to carry out packaging technology; And last in packaging technology, along the second Cutting Road region 250 cutting PCB substrates 204, to form single encapsulating structure.The area in the area of described functional areas 240 and the second Cutting Road region 250 can be set according to actual package process requirements.

Described PCB substrate 204 provides a supporting role for image sensor dice 230, and, follow-up after the patterned metal level of PCB substrate 204 surface formation, described patterned metal level is used for connecting pad 202 and external circuit, and image sensing chip 230 is electrically connected to external circuit.

Cheap due to PCB substrate 204, can reduce packaging cost greatly; And, it is very large that the area of PCB substrate 204 can be done, therefore follow-up can be above PCB substrate 204 the image sensing chip 230 of upside-down mounting a greater number, carry out after a series of packaging technology, can form more encapsulating structure, effectively raise packaging efficiency; Meanwhile, particularity and existing PCB processing procedure due to the material of PCB substrate 204, make the technical process of follow-up formation plastic packaging layer can adopt plastic packaging (molding) technique in PCB processing procedure to carry out, and can further reduce packaging cost.

Can need to determine the size of PCB substrate 204 according to actual process.

Please continue to refer to Fig. 8, in the interior formation of described PCB substrate 204, run through the hole 207 of PCB substrate 204.

The position of described hole 207 corresponding to follow-up image sensing chip 230 upside-down mountings after the position in video sensing district 201.The object that forms described hole 207 is: after follow-up formation encapsulating structure, extraneous light is transmitted to video sensing district 201 by described hole 207, and video sensing district 201 accepts light and is converted into electrical signal.

In the present embodiment, in order to make video sensing district 201 farthest accept extraneous light, the width of hole 207 is more than or equal to the width in video sensing district 201.

The horizontal plane section shape of described hole 207 is square, circular or other shapes, and the present embodiment be take the horizontal plane section shape of described hole 207 and done exemplary illustrated as square as example.

Adopt punching press or bore process to form described hole 207.

Please refer to Fig. 9, at described PCB substrate 204 functional areas 240 forming metal layer on surfaces 208, the metal level on 240 surfaces, same functional areas has opening 209.

In the present embodiment, owing to having hole 207 in PCB substrate 204, described opening 209 is positioned at the top of hole 207, and in order to simplify processing step, to reduce technology difficulty, the shape of described opening 209 is identical with hole 207 shapes, and the width of described opening 209 is identical with the width of hole 207.

In the present embodiment, the metal level 208 on 240 surfaces, adjacent functional district is connected, be metal level 208 except being positioned at 240 surfaces, PCB substrate 204 functional areas, described metal level 208 is also covered in 250 surfaces, the second Cutting Road region, forms the metal level 208 be covered in the PCB substrate surface with hole 207; Because the second Cutting Road region 250 is finally can being cut and holding of packaging technology, cut the opening of metal level 208 in described leap the second Cutting Road region 250, therefore can not affect the performance of single encapsulating structure.

The material of described metal level 208 is Cu, Al, W, Sn, Au or Sn-Au alloy.Because described PCB substrate 204 has special performance, therefore, can adopt conventional PCB processing procedure to form described metal level 208, for example, adopt sputtering technology or depositing operation to form described metal level 207.

Because the material of PCB substrate 204 mostly is resinous material, after described PCB substrate 204 forming metal layer on surfaces 208, between described metal level 208 and PCB substrate 204, there is very strong adhesiveness, improve the reliability of the encapsulating structure of follow-up formation.

In described metal level 208, there are some openings 209, follow-up after pad 202 is connected with metal level 208 video sensing district 201 be positioned at above opening 209.The width of described opening 209 is more than or equal to the width in video sensing district 201, so that the extraneous light of reception of video sensing district 201 energy maximum magnitudes.

In the embodiment of the present invention, 240 surfaces, the same functional areas of PCB substrate 204 form some discrete metal levels 208, and the quantity of discrete metal level 208 is corresponding with quantity and the position of the pad 202 that position has with single image sensor dice 230, for example, video sensing district 201 4 sides of image sensor dice 230 are all formed with pad 202, four sides of opening 209 are all formed with metal level 208, and the quantity of the discrete metal level 208 of opening 209 each side is identical with the quantity of the pad 202 of the corresponding side in video sensing district 201, and each discrete metal level 208 correspondence is connected with a pad 202, in other embodiments of the invention, relative both sides, video sensing district are formed with pad, and the both sides that opening is relative are formed with metal level, and the quantity of the discrete metal level of each side of opening is identical with the quantity of the pad of the corresponding side in video sensing district.

In the present embodiment, it is very large that PCB substrate 204 areas can be done, make PCB substrate 204 there are more functional areas 240, encapsulating structure of the corresponding follow-up formation in each functional areas 240, therefore, on the basis of a PCB substrate 204, follow-uply within an encapsulation cycle can form a large amount of encapsulating structures, packaging efficiency is improved.

Please refer to continuation Fig. 9, at PCB substrate 204 back sides, form adhesive tape layer 206, adhesive tape layer 206 sealing described holes 207.

Described PCB substrate 204 back sides refer to not be formed with the one side of metal level 208, described adhesive tape layer 206 is for cap holes 207 one end, in follow-up potting process, can prevent that video sensing district 201 is exposed in external environment condition, prevent that video sensing district 201 is contaminated or damage.

The material of described adhesive tape layer 206 is UV (Ultraviolet Rays; ultraviolet ray) dispergation rubber belt material or pyrolysis glue rubber belt material or other suitable rubber belt materials; described adhesive tape layer 206 is directly pasted the back side that is formed on PCB substrate 204; formation technique is simple; in encapsulation process, adhesive tape layer 206 can well protect the video sensing district 201 can be not contaminated or damage; after encapsulating structure forms; follow-up, can very easily adhesive tape layer 206 be removed by the mode of UV irradiation or heating, while removing, Ye Buhuidui video sensing district 201 produces damage or pollutes.

In other embodiments, the material of adhesive tape layer can also be IR (infra-red) glass or AR (anti-reflection) glass.

Please refer to Figure 10, described image sensing chip 230 upside-down mountings are placed in to 240 tops, PCB substrate 204 functional areas, and described pad 202 and metal level 208 electrical connections.

In the present embodiment, select the top that image sensing chip 230 upside-down mountings that yield meets standard are placed in PCB substrate 204.

Concrete, described pad 202 is connected by metal coupling 203 with metal level 208, and each pad 202 is corresponding to a discrete metal level 208.Adopt solder bonds technique that pad 202 is connected with metal level 208, described pad 202 and metal level 208 weld together by the material in metal coupling 203.

Described solder bonds technique is eutectic bonding, ultrasonic thermocompression, thermal compression welding, ultrasonic wire bonding etc.For example, when the material of described metal level 208 is Al, the material of described metal coupling 203 is Au, and solder bonds technique is ultrasonic thermocompression mode; When the material of described metal level 208 is Au, the material of described metal coupling 203 is Sn, and solder bonds technique is eutectic bonding mode.

After pad 202 is connected with metal level 208, video sensing district 201 is positioned at opening 209 tops, and extraneous light, is beneficial to video sensing district 201 and receives extraneous lights through the video sensing district 201 that is transmitted to opening 209 tops after PCB substrate 204 by hole 207; And in the present embodiment, the width of opening 209 is greater than the width in video sensing district 201, can make video sensing district 201 receive to greatest extent extraneous light, improve the light utilization in video sensing district 201.

Simultaneously, because the thickness of metal coupling 203 is greater than the thickness of video sensing district 201 interior photo-sensitive cells, make by 230 upside-down mountings of image sensing chip above PCB substrate 204 time, video sensing district 201 can not touch metal level 208 surfaces, prevents that video sensing district 201 from sustaining damage.

Please refer to Figure 11, form the plastic packaging layer 211 that is covered in described metal level 208 surfaces and 230 second of image sensing chips and sidewall surfaces.

Form acting as of described plastic packaging layer 211: on the one hand, the plastic packaging layer 211 forming plays the effect of protection image sensing chip 230, prevent image sensing chip 230 performance failures that cause under the impact of external environment, prevent that moisture from being invaded, being insulated with external electrical by outside; On the other hand, described plastic packaging layer 211 plays the effect of supporting image sensing chip 230, image sensing chip 230 is fixed so that follow-up circuit connects, and, after encapsulation completes, make chip not fragile; In addition, described plastic packaging layer 211 also plays the effect of the solder-bump of fixing follow-up formation, for solder-bump provides protection.

Adopt plastic package process (molding) to form described plastic packaging layer 211, described plastic package process adopts branch mode or pressing mode, and the top surface of described plastic packaging layer 211 flushes with image sensing chip 230 second faces or higher than 230 second of image sensing chips.

Owing to providing PCB substrate 204 to support image sensing chip 230 in the present embodiment, according to the particularity of PCB substrate 204, and image sensing chip 230 quantity of PCB substrate 204 tops more (area of PCB substrate 204 is larger), described plastic package process can adopt the plastic package process in PCB processing procedure to carry out, compare with adopting the plastic package process in wafer level packaging processing procedure, the cost of the plastic package process in PCB processing procedure is lower..The present embodiment adopts the plastic package process in PCB processing procedure to form described plastic packaging layer 211, has obviously reduced the difficulty of plastic package process, and has reduced packaging cost.Adopt the mode of whole module or some separate modules to form described plastic packaging layer 211.

In the present embodiment, adopt the mode of whole module to form described plastic packaging layer 211,, the metal level 208 of PCB substrate 204 tops of monoblock and image sensing chip 230 are carried out to plastic package process, the plastic packaging layer 211 forming, except being covered in the metal level 208 and image sensing chip 230 of functional areas 240, is also covered in metal level 208 surfaces in the second Cutting Road region 250.While adopting the mode of whole module to form plastic packaging layer 211, can avoid alignment issues, thereby reduce the difficulty of plastic package process.

In other embodiments, while adopting the mode of some separate modules to form described plastic packaging layer 211, the plastic packaging layer 211 of a module is at least covered in 230 second of a metal level on functional areas 240 208 surfaces and image sensing chips, as shown in figure 12, described plastic packaging layer 211 can cover the metal level 208 of whole functional areas 240, the metal level 208 of Ye Kejin covering function district 240 part areas.As a specific embodiment, the method described in forming with the plastic packaging layer 211 of some separate modules is simultaneously: adopt a plurality of moulds, and in each mould, fill plastic packaging layer 211 material, metal level 208 surfaces by mold compresses at PCB substrate 204, carry out drying and processing recession except mould, form the plastic packaging layer 211 with some separate modules.

The material of described plastic packaging layer 211 is resin or anti-solder ink material, for example, and epoxy resin or acrylic resin.

Please refer to Figure 13, at the interior formation through hole 212 of described plastic packaging layer 211, described through hole 212 bottom-exposed go out metal level 208 surfaces.

Concrete, the through hole 212 forming in the present embodiment exposes metal level 208 surfaces.The object that forms through hole 212 is, follow-up in the interior formation solder-bump of through hole 212, by solder-bump, metal level 208 is electrically connected to external circuit, thereby realizes being electrically connected to of pad 202 and external circuit, the encapsulating structure that encapsulates rear formation can be dropped in practical application.

Adopt laser drilling technique or etching technics to form described through hole 212.As an embodiment, the processing step that adopts etching technics to form through hole 212 comprises: on described plastic packaging layer 211 surface, form patterned mask layer, in described patterned mask layer, have groove, the position of described groove and width are corresponding to position and the width of follow-up formation through hole 212; The described patterned mask layer of take is mask, and plastic packaging layer 211 described in etching until expose metal level 208 surfaces, exposes the through hole 212 on metal level 208 surfaces in the interior formation of described plastic packaging layer 211; Remove described patterned mask layer.

The quantity of the through hole 212 forming is identical with the quantity of pad 202, in other words, the quantity of described through hole 212 is identical with the quantity of discrete metal level 208, each discrete metal level 208 top is all formed with a through hole 212, and each pad 202 of image sensing chip 230 all can be electrically connected to external circuit.

In the present embodiment, by the mode at the interior formation through hole 212 of plastic packaging layer 211, realize the object that pad 202 is electrically connected to external circuit, avoided the harmful effect that brings at the interior formation through hole of image sensing chip 230, improved the performance of the encapsulating structure of follow-up formation.

In forming the technical process of through hole 212, due to the existence of adhesive tape layer 206, video sensing district 201, in an annular seal space, prevents that the technique that forms through hole 212 from causing damage or impurity to enter in video sensing district 201 to video sensing district 201.

Please refer to Figure 14, form the solder-bump 215 of filling full described through hole 212 (please refer to Figure 13), and described solder-bump 215 tops are higher than plastic packaging layer 211 surface.

By described solder-bump 215, pad 202 is electrically connected to external circuit, thereby image sensing chip 230 is normally worked.

Described solder-bump 215 top surfaces are shaped as arc, the material of solder-bump 215 is gold, tin or ashbury metal, and described ashbury metal can be plumbous for tin silver, tin, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony etc.

As an embodiment, the material of solder-bump 215 is tin, and the step that forms described solder-bump 215 comprises: form the metal material of filling full described through hole 212, adopt reflux technique, form described solder-bump 215.

As a specific embodiment, the distance between described solder-bump 215 tops to plastic packaging layer 211 top is 20 μ m to 100 μ m.

Most solder-bump 215 surfaces are coated by plastic packaging layer 211, only retain few solder-bump 215 surfaces in external environment, effectively prevent that solder-bump 215 is oxidized by external environment, improves the reliability and stability of the encapsulating structure of follow-up formation.And, in the interior formation solder-bump 215 of plastic packaging layer 211, the top of described solder-bump 215 is a little more than plastic packaging layer 211 surface, can make image sensing chip 230 be electrically connected to external circuit, and solder-bump 215 tops are a little more than plastic packaging layer 211 surface (distance on solder-bump 215 tops to plastic packaging layer 211 surface is 20 μ m to 100 μ m), the integral thickness that can further reduce the encapsulating structure of follow-up formation, is conducive to improve encapsulation and integration degree.

Please refer to Figure 15, along described the second Cutting Road region 250 (please refer to Figure 14), cut described plastic packaging layer 211 and PCB substrate 204, form some single encapsulating structures.

In the present embodiment, adopt slicer cutting or laser cutting parameter to cut described plastic packaging layer 211, metal level 208, PCB substrate 204 and adhesive tape layer 206, form some single encapsulating structures.

Described cutting technique only carries out cutting process to PCB substrate 204, plastic packaging layer 211 and metal level 208, has avoided the cutting process to image sensing chip 230; And, due to aforementioned, wafer to be wrapped is being carried out after reduction processing, formed the image sensing chip 230 having compared with minimal thickness, therefore, the thinner thickness of the encapsulating structure that the present embodiment forms; Simultaneously, the packaging technology that the present embodiment forms encapsulating structure is simple, and the encapsulation procedure that image sensing chip 230 is carried out few (encapsulation procedure that image sensing chip 230 itself has only experienced attenuate, formed metal coupling 203 and once cut), make encapsulating structure have extraordinary encapsulation performance, encapsulation yield gets a promotion; Finally, the present embodiment can be selected the good image sensing chip 230 of yield and encapsulate, thereby has further improved encapsulation yield, effectively reduces packaging cost.

And, in the present embodiment, provide PCB substrate 204 to support image sensing chips 230, on the one hand, PCB substrate 204 cheap, has reduced packaging cost; On the other hand, it is very large that the area of PCB substrate 204 can be done, and therefore, the quantity of the image sensing chip 230 of upside-down mounting on PCB substrate 204 is many, a packaging technology, in the cycle, can form more encapsulating structure, thereby has improved greatly packaging efficiency; Meanwhile, due to the particularity of PCB substrate 204, when forming plastic packaging layer 211, can adopt the plastic package process in PCB processing procedure, compare with the plastic package process in silicon wafer process, further reduce packaging cost.

In cutting technique process, the adhesive tape layer 206 not cut techniques in protection video sensing district 201 are destroyed, thereby improve encapsulation performance.

After packaging technology completes, and before head mould group on show, described adhesive tape layer 206 can be removed.

When the material of described adhesive tape layer 206 is UV dispergation adhesive tape, adopt adhesive tape layer 206 described in UV irradiation, then remove described adhesive tape layer 206, expose the video sensing district 101 of hole 207 tops.

When the material of described adhesive tape layer 206 is pyrolysis glue adhesive tape, described adhesive tape layer 206 is heated, then remove described adhesive tape layer 206.

Accordingly, the present embodiment provides a kind of encapsulating structure, please refer to Figure 15, and described encapsulating structure comprises:

PCB substrate 204;

Be positioned at the some discrete metal level 208 on described PCB substrate 204 surfaces;

The image sensing chip 230 of upside-down mounting above PCB substrate 204, described image sensing chip 230 have first surface with relative with described first surface second, described image sensing chip 230 first surfaces have video sensing district 201 and around the pad 202 in described video sensing district 201, and described pad 202 and metal level 208 are electrically connected to;

Be positioned at the plastic packaging layer 211 on described metal level 208 surfaces and image sensing chip 230 surfaces;

Be positioned at the through hole of described plastic packaging layer 211, and described through hole exposes metal level 208 surfaces;

Fill the solder-bump 215 of full described through hole, and described solder-bump 215 tops are higher than plastic packaging layer 211 surface.

In the present embodiment, have the hole 207 that runs through PCB substrate 204 in PCB substrate 204, and video sensing district 201 is positioned at hole 207 tops, the width of hole 207 is more than or equal to the width in video sensing district 201.

In embodiments of the present invention, at PCB substrate 204 back sides, be formed with adhesive tape layer 206, one end of described adhesive tape layer 206 cap holes 207, to prevent that impurity from dropping in video sensing district 201, avoids video sensing district 201 to sustain damage.

In described metal level 208, there is the opening 209 that exposes PCB substrate 204, described video sensing district 201 is positioned at opening 209 tops, video sensing district 201 can receive extraneous light by described opening 209, in the present embodiment, described opening 209 width are greater than video sensing district 201 width, improve the utilance of the 201 pairs of light in video sensing district.

The position of described metal level 208 is corresponding with position and the quantity of pad 202 with quantity.Concrete, when video sensing district 201 4 sides all have some pads 202, hole 207 4 sides all have some discrete metal levels 208, and each discrete metal level 208 is connected corresponding to a pad 202.In other embodiments, when video sensing district 201 1 sides have some pads, described hole one side has the discrete metal level of equal number.

The material of described metal level 208 is Cu, Al or W.

In the present embodiment, described metal level 208 flushes with the sidewall of PCB substrate 204 away from the sidewall of described opening 209.

Described encapsulating structure also comprises: metal coupling 203, described metal coupling 203, between pad 202 and metal level 208, is electrically connected to described pad 202 and metal level 208 by described metal coupling 203.Concrete, by described metal coupling 203, connect pad 202 and metal level 208.

The quantity of described metal coupling 203 is corresponding with quantity and the position of pad 202 with position, the quantity that is metal coupling 203 is identical with the quantity of pad 202, and the spacing of the spacing of adjacent metal projection 203 and adjacent pad 202 equates, so that each pad 202 all can be connected with a metal level 208, thereby realize the object that pad 202 is electrically connected to external circuit.

Being shaped as of described metal coupling 203 is square or spherical, and the material of described metal coupling 203 is tin, gold or ashbury metal.

In the present embodiment, the top shape of described solder-bump 215 is spherical, and the material of described solder-bump 215 is tin, gold or ashbury metal.

The encapsulating structure that the present embodiment provides, plastic packaging layer 211 envelopes image sensing chip 230, prevents that external environment from causing harmful effect to image sensing chip 230, improves the reliability and stability of encapsulating structure; In plastic packaging layer 211, be formed with the through hole that exposes metal level 208 surfaces, in through hole, be formed with solder-bump 215, by solder-bump 215, pad 212 is electrically connected to external circuit, both avoided damage or pollution that image sensing chip 230 is caused itself, the encapsulation performance of encapsulating structure is improved; And, solder-bump 215 major parts are enveloped by plastic packaging layer 211, reduced the area that solder-bump 215 contacts with external environment, thereby it is oxidized or be subject to the possibility of other damages to have reduced greatly solder-bump 215, further improves the reliability of encapsulating structure.

Simultaneously, from described encapsulating structure, can find out, compared with prior art, in packaging technology in the encapsulating structure that formation the present embodiment provides, encapsulation procedure in effect image sensing chip 230 is obviously than few many of prior art, the thickness of the image sensing chip 230 in the present embodiment encapsulating structure is less than the thickness of the image sensing chip of prior art, and therefore, in the present embodiment, the thickness of encapsulating structure is significantly less than the thickness of the encapsulating structure of prior art.

And, because solder-bump 215 tops are very little to the distance on plastic packaging layer 211 surface, be 20 μ m to 100 μ m, therefore, the area that solder-bump 215 is exposed in external environment is very little, effectively improves the reliability of encapsulating structure; Meanwhile, because solder-bump 215 tops are very little to the distance on plastic packaging layer 211 surface, further reduced the thickness of encapsulating structure.

Another embodiment of the present invention also provides a kind of method for packing, Figure 16 to Figure 20 is the cross-sectional view of another embodiment of the present invention image sensor package process, it should be noted that, in the present embodiment, the restriction such as the parameter of structure same with the above-mentioned embodiment and effect repeats no more in the present embodiment, specifically please refer to above-described embodiment.

Please refer to Figure 16, some single image sensing chips 230 are provided, described image sensing chip 230 has video sensing district 201 and around the pad 202 in described video sensing district 201.

The formation step of described image sensing chip 230 and metal coupling 203 can, with reference to the explanation of previous embodiment, not repeat them here.

Please refer to Figure 17, PCB substrate 204 is provided, described PCB substrate 204 comprises some functional areas 240 and the second Cutting Road region 250 between adjacent functional district 240; The hole 207 that runs through PCB substrate 204 in the described PCB substrate 205 interior formation in functional areas 240; On described PCB substrate 204 surfaces, form some discrete metal levels 208, and in the metal level 208 of same functional areas 240, be formed with the opening 209 that exposes PCB substrate 204 surfaces; On described metal level 208 surfaces, form metal coupling 203; At described PCB substrate 204 back sides, form adhesive tape layer 206, the opening of described adhesive tape layer 206 cap holes 207 one end.

The width of described hole 207 is more than or equal to the width in video sensing district 201.

In the present embodiment, in order to save packaging technology cost, described metal level 208 is only positioned at functional areas 240, on 250 surfaces, the second Cutting Road region, does not form metal level 208.Can adopt PCB making technology to form described metal level 208, for example, sputter or depositing operation, in conjunction with etching technics at PCB substrate 204 functional areas 240 forming metal layer on surfaces 208.

Concrete, as an embodiment, the processing step that forms described metal level 208 comprises: on described PCB substrate 204 surfaces, form metal film; In described metallic film surface, form patterned mask layer; Take described mask layer as mask, removal is positioned at the metal film of the metal film on 250 surfaces, the second Cutting Road region and the part area in close the second Cutting Road region 250, form some discrete metal levels 208, expose 20 surfaces, PCB substrate 204 functional areas between metal level 208 sidewalls and 250 borders, the second Cutting Road region.

In the present embodiment, after forming described metal level 208, expose 240 surfaces, PCB substrate 204 functional areas between metal level 208 sidewalls and 250 borders, the second Cutting Road region, its benefit is, follow-up when forming plastic packaging layer, 240 surfaces, PCB substrate 204 functional areas that expose described in plastic packaging layer is covered in, thereby metal level 208 sidewalls are enveloped by plastic packaging layer 211, there is unnecessary being electrically connected to external circuit in the sidewall that prevents metal level 208, the material that can also prevent metal level 208 is oxidized, thereby improves the reliability of follow-up formation encapsulating structure.In other embodiments, the sidewall of described metal level 208 also can be positioned at the boundary in the second Cutting Road region 250.

The material of described metal level 208 is Cu, Al, W, Sn, Au or Sn-Au alloy.

The position of the interior discrete metal level 208 in same functional areas 240 and quantity are corresponding with position and the quantity of pad 202 in image sensing chip 230.Follow-up by 230 upside-down mountings of image sensing chip on PCB substrate 204 time, video sensing district 201 is positioned at opening 209 tops, makes video sensing district 201 can receive extraneous light.In the present embodiment, the width of described opening 209 is greater than the width in video sensing district 201.

It should be noted that, in other embodiments, metal level is covered in PCB functional substrate district and Cutting Road area surfaces.

The quantity of described metal coupling 203 and position are corresponding to quantity and the position of pad 202, the spacing of adjacent metal projection 203 equates with the spacing of adjacent pad 202, that is to say, follow-up by 230 upside-down mountings of image sensing chip on PCB substrate 204 time, each metal coupling 203 contacts corresponding to pad 202 surfaces.

In the present embodiment, on PCB substrate 204 metal level 208 surfaces, form metal coupling 203, avoided forming on pad 202 surfaces the encapsulation procedure of metal coupling 203, therefore the encapsulation procedure that image sensing chip 230 experiences itself further reduces, thereby the harmful effect of avoiding encapsulation procedure to bring image sensing chip 230, makes image sensing chip 230 keep higher performance.

Please refer to Figure 18, by described image sensing chip 230 upside-down mountings, above PCB substrate 204 functional areas 240, pad 202 is electrically connected to by metal coupling 203 with metal level; Metal level 208 in formation covering described PCB substrate 204 functional areas 240 and the plastic packaging layer 211 on image sensing chip 230 surfaces.

By metal coupling 203 and pad 202 solder bonds, thereby realize being electrically connected between pad 202 and metal level.Concrete, each metal coupling 203 correspondence and pad 202 solder bonds, makes pad 202 be connected with discrete metal level 208.

Solder bonds technique is eutectic bonding, ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding.

Adopt plastic package process to form described plastic packaging layer 211.In the present embodiment, the particularity of material and the particularity of PCB processing procedure due to PCB substrate 204, the present embodiment can adopt the plastic package process in PCB processing procedure to form described plastic packaging layer 211, the problem that packaging cost is high and encapsulation difficulty is large of avoiding adopting the plastic package process in silicon wafer process to bring, the present embodiment adopts the plastic package process in PCB processing procedure to form plastic packaging layer 211, reduces packaging cost and encapsulation difficulty.

Adopt the mode of whole module or some separate modules to form described plastic packaging layer 211.

In the present embodiment, described plastic packaging layer 211 is positioned at functional areas 240, and 250 surfaces, the second Cutting Road region are not formed with plastic packaging layer 211,, the plastic packaging layer 211 that adopts the mode of some separate modules to form 211, one module of described plastic packaging layer is at least covered in metal level 208 surface and 230 second surfaces of image sensing chip on functional areas 240.It should be noted that, plastic packaging layer 211 border in same functional areas 240 both can be positioned at functional areas 240, also can overlap with 250 borders, the second Cutting Road region.

In the present embodiment, the plastic packaging layer 211 of formation is covered in metal level 208 sidewall surfaces in same functional areas 240, prevent follow-up formation encapsulating structure after metal level 208 sidewalls be exposed in external environment, thereby improve the reliability and stability of encapsulating structure.

In other embodiments of the invention, the plastic packaging layer of formation also can be covered in the second Cutting Road area surfaces, that is, adopt the mode of whole module to form described plastic packaging layer.

Please refer to Figure 19, at the interior formation through hole of described plastic packaging layer 211, described via bottoms exposes metal level 208 surfaces; Form the solder-bump 215 of filling full described through hole, and described solder-bump 215 tops are higher than plastic packaging layer 211 surface.

Effect and the benefit of the solder-bump 215 forming can, with reference to the description of previous embodiment, not repeat them here.

Please refer to Figure 20, along described the second Cutting Road region 250 (please refer to Figure 19), cut described PCB substrate 204 (please refer to Figure 19), form some single encapsulating structures.

In cutting process, described adhesive tape layer 206 prevents that impurity that cutting process produces from pounding and drops in video sensing district 201, avoids video sensing district 201 to cause harmful effect.

In the present embodiment, metal level 208 sidewalls have certain distance from 250 borders, the second Cutting Road region, therefore, along the second Cutting Road region 250PCB substrate 204, form some single encapsulating structures.Due to cutting technique cutting metal layer 208 not, so metal level 208 sidewalls still cover by plastic packaging layer 211, thereby prevent that metal level 208 sidewalls from exposing in external environment, improved the reliability and stability of encapsulating structure.

In the present embodiment, act on image sensing chip 230 encapsulation procedures seldom (image sensing chip 230 has only experienced attenuate and cutting process), make image sensing chip 230 keep higher performance, the yield of the encapsulating structure of formation gets a promotion, and the encapsulation performance of encapsulating structure is excellent; And the present embodiment, by the interior formation through hole of plastic packaging layer 211, forms the mode of solder-bump 215 in through hole, and image sensing chip 230 can be electrically connected to external circuit, has further reduced packaging technology step, packaging technology is simple; And solder-bump 215 major parts are covered by plastic packaging layer 211, reduced the harmful effect of external environment to solder-bump 215, improve the reliability and stability of encapsulating structure; Meanwhile, because image sensing chip 230 is thinned to thinner thickness, make the encapsulating structure forming also there is thinner thickness.And the present embodiment can select the good image sensing chip 230 of yield and encapsulate, improved greatly the encapsulation yield of packaging efficiency and encapsulating structure, reduce packaging technology cost.

And, in the present embodiment, provide PCB substrate 204 to support image sensing chips 230, on the one hand, PCB substrate 204 cheap, thus packaging cost reduced; On the other hand, it is very large that the area of PCB substrate 204 can be done, and therefore, the quantity of the image sensing chip 230 of upside-down mounting on PCB substrate 204 is many, a packaging technology, in the cycle, can form more encapsulating structure, thereby has improved greatly packaging efficiency; Meanwhile, due to the particularity of PCB substrate 204, when forming plastic packaging layer 211, can adopt the plastic package process in PCB processing procedure, compare with the plastic package process in silicon wafer process, further reduce packaging cost.

After packaging technology completes, and before head mould group on show, remove described adhesive tape layer 206.

Accordingly, the present embodiment provides a kind of encapsulating structure, please refer to Figure 20, and described encapsulating structure comprises:

PCB substrate 204;

Be positioned at the metal level 208 on described PCB substrate 204 surfaces;

The image sensing chip 230 of upside-down mounting above PCB substrate 204, described image sensing chip 230 have first surface with relative with described first surface second, described image sensing chip 230 first surfaces are formed with some video sensings district 201 and around the pad 202 in described video sensing district 201, and described pad 202 is connected with metal level 208;

Be positioned at the plastic packaging layer 211 of 230 second of described metal level 208 surfaces and image sensing chips and sidewall surfaces;

Solder-bump 215, shown in solder-bump 215 fill full described through hole, and the top of described solder-bump 215 is higher than plastic packaging layer 211 surface.

PCB substrate 204 surfaces have discrete metal level 208, and the position of described discrete metal level 208 is corresponding with position and the quantity of pad 202 with quantity.Concrete, when video sensing district 201 4 sides all have some pads 202, hole 207 4 sides all have some discrete metal levels 208.In other embodiments, when video sensing district 201 1 sides have some pads, described hole one side has the discrete metal level of equal number.

The material of described metal level 208 is Cu, Al or W.

In the present embodiment, described metal level 208 exposes PCB substrate 204 part surfaces away from described opening 209, PCB substrate 204 part surfaces that expose described in described plastic packaging layer 211 is covered in, and described plastic packaging layer 211 is covered in metal level 208 sidewall surfaces, the sidewall that prevents metal level 208 is exposed in external environment, there is unnecessary being electrically connected to external circuit in the metal level 208 of avoiding being exposed in external environment, the material that can also prevent metal level 208 is oxidized by external environment, has improved the reliability of encapsulating structure.

Described encapsulating structure also comprises: metal coupling 203, described metal coupling 203, between pad 202 and metal level, connects described pad 202 and metal level by described metal coupling 203.Concrete, by described metal coupling 203, connect pad 202 and metal level 208.

The position of described metal coupling 203 is corresponding with position and the quantity of pad 202 with quantity.Concrete, when video sensing district 201 4 sides all have some pads 202, hole 207 4 sides all have the metal coupling 203 of equal number, and the spacing of each side pad 202 equates with the spacing of the metal coupling 203 of a corresponding side.In other embodiments, when video sensing district 201 1 sides have some pads 202, described hole 207 1 sides have the metal coupling 203 of equal number, and the spacing between metal coupling 203 equates with the spacing between pad 202.

The encapsulating structure that the present embodiment provides, plastic packaging layer 211 envelopes image sensing chip 230, prevents that external environment from causing harmful effect to image sensing chip 230, improves the reliability and stability of encapsulating structure; In plastic packaging layer 211, be formed with the through hole that exposes metal level 208 surfaces, in through hole, be formed with solder-bump 215, by solder-bump 215, pad 202 is electrically connected to external circuit, both avoided damage or pollution that image sensing chip 230 is caused itself, the encapsulation performance of encapsulating structure is improved; And, solder-bump 215 major parts are enveloped by plastic packaging layer 211, reduced the area that solder-bump 215 contacts with external environment, thereby it is oxidized or be subject to the possibility of other damages to have reduced greatly solder-bump 215, further improves the reliability of encapsulating structure.

Further embodiment of this invention also provides a kind of method for packing, Figure 21 to Figure 23 is the cross-sectional view of further embodiment of this invention image sensor package process, it should be noted that, in the present embodiment, the restriction such as the parameter of structure same with the above-mentioned embodiment and effect repeats no more in the present embodiment, specifically please refer to above-described embodiment.

Please refer to Figure 21, some single image sensing chips 230 are provided, described image sensing chip 230 has video sensing district 201 and around the pad 202 in described video sensing district; PCB substrate 204 is provided, and described PCB substrate 204 comprises some functional areas 210 and the second Cutting Road region 250 between adjacent functional district 240, and 240 surfaces, described PCB substrate 204 functional areas are formed with metal level 208; Described image sensing chip 230 upside-down mountings are placed in to the top of PCB substrate 204 functional areas 240, and described pad 202 and metal level 208 electrical connections.

The hole 207 that runs through described PCB substrate 204 in the interior formation of described PCB substrate 204, in described metal level 208, there is opening 209, described video sensing district 201 is positioned at opening 209 tops, after 230 upside-down mountings of image sensing chip being placed in to 240 surfaces, PCB substrate 204 functional areas, video sensing district 201 is positioned at the top of hole 207, is beneficial to video sensing district 201 and receives extraneous light.In the present embodiment, the position of described opening 209 and hole 207 is corresponding and measure-alike.

Also comprise step: at PCB substrate 204 back sides, form adhesive tape layer 206, one end of described adhesive tape layer 206 sealing described holes 207.The material of described adhesive tape layer 206 is UV dispergation rubber belt material, pyrolysis glue rubber belt material, IR glass or AR glass.

Also comprise step: on described pad 202 surfaces or metal level 208 surface form metal couplings 203, described pad 202 and metal level 208 are electrically connected to by metal coupling 203.

The description of relevant image sensing chip 230, PCB substrate 204, metal level 208, metal coupling 203 can, with reference to previous embodiment, not repeat them here.

Please refer to Figure 22, form the some glue-line 214 that is covered in described image sensing chip 230 sidewall surfaces; On described metal level 208 surfaces, form solder-bump 215, and described solder-bump 215 tops are higher than image sensing chip 230 surfaces.

Described some glue-line 214 can be covered in image sensing chip 230 partial sidewall surfaces, also can be covered in whole sidewall surfaces of image sensing chip 230.In the present embodiment, the some glue-line 214 of formation is also covered in metal coupling 203 sidewall surfaces.

In the present embodiment, the some glue-line 214 of formation is also covered in metal coupling 203 sidewall surfaces.

Described some glue-line 214Shi video sensing district 201, in sealing state, prevents that external environment from causing harmful effect to image sensing chip 230.

As a specific embodiment, adopt point gum machine to carry out gluing process and form described some glue-line 214.

The material of described solder-bump 215 can be with reference to the explanation of previous embodiment.In the present embodiment, employing is planted ball technique and is formed described solder-bump 215, and the vertical range on solder-bump 215 tops to image sensing chip 230 surfaces is 20 μ m to 100 μ m.

Please refer to Figure 23, along the described PCB substrate 204 of described the second Cutting Road region 250 cutting, form some single encapsulating structures.

Described cutting technique can, with reference to the explanation of previous embodiment, not repeat them here.

In the present embodiment, because image sensing chip 230 has only experienced cutting technique (cutting wafer to be wrapped forms some single image sensing chips 230), by form the mode of solder-bump 215 on metal level 208 surfaces, image sensing chip 230 is electrically connected to external circuit, therefore described image sensing chip 230 has kept higher performance, thereby makes the encapsulation performance of the encapsulating structure that forms good.

And due to the thinner thickness of the image sensing chip 230 providing in the present embodiment (concrete reason can with reference to the explanation of previous embodiment), therefore, the thickness of the encapsulating structure of formation reduces.Meanwhile, the method for packing that the embodiment of the present invention provides, packaging technology is more simple.

Accordingly, this enforcement provides a kind of encapsulating structure, please refer to Figure 23, and described encapsulating structure comprises:

PCB substrate 204;

Be positioned at the metal level 208 on described PCB substrate 204 surfaces;

The image sensing chip 230 of upside-down mounting above PCB substrate 204, described image sensing chip 230 has video sensing district 201 and around the pad 202 in described video sensing district 201, and described pad 202 and metal level 208 are electrically connected to;

Be positioned at the solder-bump 215 on described metal level 208 surfaces, and described solder-bump 215 tops are higher than image sensing chip 230 surfaces.

Also comprise: metal coupling 203, described metal coupling 203, between pad 202 and metal level 208, is electrically connected to described pad 202 and metal level 208 by described metal coupling 203.

Also comprise: be covered in the some glue-line 214 of described image sensing chip 230 sidewall surfaces, and described some glue-line 214 is also covered in metal coupling 203 sidewall surfaces.Described some glue-line 214 plays the effect of protection image sensing chip 230, prevents that external environment from causing harmful effect to image sensing chip 230, improves the reliability of encapsulating structure.Described some glue-line 214 can be covered in image sensing chip 230 partial sidewall surfaces, also can be covered in whole sidewall surfaces of image sensing chip 230.In the present embodiment, the some glue-line 214 of formation is also covered in metal coupling 203 sidewall surfaces.

In described PCB substrate 204, have the hole 209 that runs through described PCB substrate 204, the size of described hole 209 is more than or equal to the size in video sensing district 201; The interior tool opening 209 of described metal level 208, video sensing district 201 is positioned at the top of opening 209, that is and, the width that described video sensing district 201 is positioned at the hole 207 described openings 209 in top is more than or equal to the width in video sensing district 201.

Also comprise: be positioned at the adhesive tape layer 206 at PCB substrate 204 back sides, one end of described adhesive tape layer 206 sealing described holes 207.The material of described adhesive tape layer 206 is UV dispergation rubber belt material, pyrolysis glue rubber belt material, IR glass or AR glass.

In the present embodiment, the vertical range on solder-bump 215 tops to image sensing chip 230 surfaces is 20 μ m to 100 μ m, wherein, described vertical range refers to perpendicular to the distance on the in-plane of the surperficial place of metal level 208, and described image sensing chip 230 surfaces refer to the surface that is not formed with pad 202.

The encapsulating structure that the present embodiment provides is simple, by solder-bump 215 being set on metal level 208 surfaces, pad 202 is electrically connected to external circuit, has avoided damage or pollution that image sensing chip 230 is caused itself, the encapsulation performance of encapsulating structure is improved; And solder-bump 215 tops are very little to the distance on image sensing chip 230 surfaces, be 20 μ m to 100 μ m, make encapsulating structure there is less thickness, meet the development trend of semiconductor miniaturization microminiaturization.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a method for packing, is characterized in that, comprising:

Some single image sensing chips are provided, and described image sensing chip has video sensing district and around the pad in described video sensing district;

PCB substrate is provided, and described PCB substrate comprises some functional areas and the Cutting Road region between adjacent functional district, and surface, described PCB functional substrate district is formed with metal level;

Described image sensing flip-chip is placed in to the top in PCB functional substrate district, and described pad and metal level electrical connection;

Formation is covered in the plastic packaging layer of described functional areas layer on surface of metal and image sensing chip surface;

In described plastic packaging layer, form through hole, described via bottoms exposes layer on surface of metal;

Form the solder-bump of filling full described through hole, and described solder-bump top is higher than plastic packaging layer surface;

Along described Cutting Road region, cut described PCB substrate, form some single encapsulating structures.

2. method for packing as claimed in claim 1, is characterized in that, forms the hole that runs through PCB substrate in described PCB substrate, and video sensing district is positioned at above hole after pad and metal level are electrically connected to.

3. method for packing as claimed in claim 2, is characterized in that, adopts punching press or bore process to form described hole.

4. method for packing as claimed in claim 2, is characterized in that, after forming described metal level, at PCB substrate back, forms adhesive tape layer, adhesive tape layer sealing described hole one end.

5. method for packing as claimed in claim 4, is characterized in that, the material of described adhesive tape layer is UV dispergation rubber belt material, pyrolysis glue rubber belt material, IR glass or AR glass.

6. method for packing as claimed in claim 1, is characterized in that, described metal level is covered in PCB functional substrate district and Cutting Road area surfaces.

7. method for packing as claimed in claim 1, is characterized in that, described plastic packaging layer is covered in the metal level sidewall surfaces of same functional areas.

8. method for packing as claimed in claim 1, is characterized in that, the material of described metal level is Cu, Al, W, Sn, Au or Sn-Au alloy.

9. method for packing as claimed in claim 1, is characterized in that, the formation step of described some single image sensing chips comprises: wafer to be wrapped is provided, has some video sensings district and around the pad in described video sensing district in described wafer to be wrapped; Cut described wafer to be wrapped, form some single image sensing chips.

10. method for packing as claimed in claim 9, is characterized in that, before the described wafer to be wrapped of cutting, also comprises step: described encapsulation wafer is carried out to reduction processing.

11. method for packing as claimed in claim 9, is characterized in that, also comprise step: in described bond pad surface or layer on surface of metal, form metal coupling, described pad and metal level are electrically connected to by metal coupling.

12. method for packing as claimed in claim 11, is characterized in that, the material of described metal coupling is tin, gold or ashbury metal.

13. method for packing as claimed in claim 11, is characterized in that, adopt solder bonds technique that pad is connected with metal level, and wherein, solder bonds technique is eutectic bonding, ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding.

14. method for packing as claimed in claim 1, is characterized in that, the material of described plastic packaging layer is epoxy resin or acrylic resin.

15. method for packing as claimed in claim 1, is characterized in that, the processing step that forms solder-bump comprises: form the metal material of filling full described through hole, adopt reflux technique, form described solder-bump.

16. as claimed in claim 1 method for packing it is characterized in that, the distance at described solder-bump top to plastic packaging layer top is 20 μ m to 100 μ m.

17. method for packing as claimed in claim 1, is characterized in that, adopt etching or laser drilling technique to form described through hole.

18. 1 kinds of encapsulating structures, is characterized in that, comprising:

PCB substrate;

Be positioned at the metal level of described PCB substrate surface;

The image sensing chip of upside-down mounting above PCB substrate, described image sensing chip has video sensing district and around the pad in described video sensing district, and described pad and metal level are electrically connected to;

Be positioned at the plastic packaging layer of described layer on surface of metal and image sensing chip surface;

Be positioned at the through hole of described plastic packaging layer, and described through hole exposes layer on surface of metal;

Fill the solder-bump of full described through hole, described solder-bump top is higher than plastic packaging layer surface.

19. encapsulating structures as claimed in claim 18, is characterized in that having the hole that runs through PCB substrate in described PCB substrate, and video sensing district is positioned at hole top.

20. encapsulating structures as claimed in claim 18, is characterized in that, the width of described hole is more than or equal to the width in video sensing district.

21. encapsulating structures as claimed in claim 18, is characterized in that, the distance at described solder-bump top to plastic packaging layer top is 20 μ m to 100 μ m.

22. encapsulating structures as claimed in claim 18, is characterized in that, also comprise: metal coupling, described metal coupling, between pad and metal level, is electrically connected to described pad and metal level by described metal coupling.

23. encapsulating structures as claimed in claim 22, is characterized in that, the material of described metal coupling is tin, gold or ashbury metal.

24. encapsulating structures as claimed in claim 18, is characterized in that, the material of described metal level is Cu, Al, W, Sn, Au or Sn-Au alloy.

25. encapsulating structures as claimed in claim 18, is characterized in that, described metal level sidewall flushes with PCB substrate sidewall.

26. encapsulating structures as claimed in claim 18, is characterized in that, described plastic packaging layer is covered in metal level sidewall surfaces.

27. encapsulating structures as claimed in claim 18, is characterized in that, described PCB substrate back is formed with adhesive tape layer, one end of adhesive tape layer sealing described hole.

28. 1 kinds of method for packing, is characterized in that, comprising:

At described layer on surface of metal, form solder-bump, and described solder-bump top is higher than image sensing chip surface;

29. method for packing as claimed in claim 28, is characterized in that, also comprise step: form the some glue-line that is covered in described image sensing chip side wall surface.

30. method for packing as claimed in claim 29, is characterized in that, also comprise step: in described bond pad surface or layer on surface of metal, form metal coupling, described pad and metal level are electrically connected to by metal coupling.

31. method for packing as claimed in claim 30, is characterized in that, the some glue-line of formation is also covered in metal coupling sidewall surfaces.

32. method for packing as claimed in claim 28, is characterized in that, form the hole that runs through PCB substrate in described PCB substrate, and after image sensing flip-chip being placed in above PCB functional substrate district, video sensing district is positioned at hole top.

33. 1 kinds of encapsulating structures, is characterized in that, comprising:

PCB substrate;

Be positioned at the metal level of described PCB substrate surface;

Be positioned at the solder-bump of described layer on surface of metal, and described solder-bump top is higher than image sensing chip surface.

34. encapsulating structures as claimed in claim 33, is characterized in that, also comprise: metal coupling, described metal coupling, between pad and metal level, is electrically connected to described pad and metal level by described metal coupling.

35. encapsulating structures as claimed in claim 34, is characterized in that, also comprise: the some glue-line that is covered in described image sensing chip side wall surface and metal coupling sidewall surfaces.

36. encapsulating structures as claimed in claim 33, is characterized in that having the hole that runs through described PCB substrate in described PCB substrate, and video sensing district is positioned at hole top.