CN103926768B - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- CN103926768B CN103926768B CN201310589624.7A CN201310589624A CN103926768B CN 103926768 B CN103926768 B CN 103926768B CN 201310589624 A CN201310589624 A CN 201310589624A CN 103926768 B CN103926768 B CN 103926768B
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Abstract
The invention discloses a kind of array base palte, the problem that there is horizontal band in image display process with solution.Array base palte includes: substrate, the grid line being formed on substrate and sub-pixel unit array, each sub-pixel unit includes TFT and public electrode, it is a sub-pixel unit group with sub-pixel unit described in two the most adjacent row, described in two row of described sub-pixel unit group, between sub-pixel unit, two grid lines is set；The gate electrode of the gate electrode of the described TFT of the lastrow sub-pixel unit in described sub-pixel unit group and the described TFT of next line sub-pixel unit is respectively positioned between described two grid lines and is crisscross arranged, and the gate electrode of each described TFT is respectively positioned on the homonymy of respective described sub-pixel unit；Described in two row of described sub-pixel unit group, sub-pixel unit offsets one from another less than the width of a sub-pixel unit along described grid line direction.The invention also discloses a kind of display floater and display device.
Description
Technical field
The present invention relates to display field, particularly relate to a kind of array base palte and comprise the aobvious of this array base palte
Show panel and display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display,
TFT-LCD) array base palte, color membrane substrates and liquid crystal layer positioned there between are included.In order to obtain more preferably
Display effect, each producer of the target that high aperture is pursue target.
See Fig. 1, for the array base palte of a kind of high aperture.Including grid line 101 arranged in a crossed manner and data
Line 102, public electrode wire 103 and enclosed by data wire 102 and grid line 101 and set the sub-pix list formed
Unit's (Fig. 1 only illustrates two sub-pixel unit up and down in adjacent two row sub-pixel unit), each sub-pix
Unit includes a TFT104 and a pixel electrode 105；Adjacent rows grid line 101 is positioned at adjacent two
Between row sub-pixel unit, the grid of the TFT being positioned at same row in this adjacent rows sub-pixel unit interlocks
In opposite directions, two row sub-pixel unit it are separated by between adjacent rows public electrode wire 103.
But array base palte as shown in Figure 1, each pixel is perfectly aligned, there is horizontal band during image display
Phenomenon.
Summary of the invention
It is an object of the invention to provide a kind of array base palte, display floater and display device, to solve at image
The problem that there is horizontal band during display.
It is an object of the invention to be achieved through the following technical solutions:
The embodiment of the present invention provides a kind of array base palte, including substrate, the grid line being formed on substrate and sub-picture
Element cell array, each sub-pixel unit includes TFT and public electrode, with picture sub-described in two the most adjacent row
Element unit is a sub-pixel unit group, sets described in two row of described sub-pixel unit group between sub-pixel unit
Put two grid lines；The gate electrode of the described TFT of the lastrow sub-pixel unit in described sub-pixel unit group
And the gate electrode of the described TFT of next line sub-pixel unit is respectively positioned between described two grid lines and interlocks
Arrange, and the gate electrode of each described TFT is respectively positioned on the homonymy of respective described sub-pixel unit.
Described in two row of described sub-pixel unit group, sub-pixel unit offsets one from another little along described grid line direction
Width in a sub-pixel unit.
The embodiment of the present invention has the beneficial effect that: the gate electrode of each described TFT is respectively positioned on respective described sub-pix
The homonymy of unit, and the grid formation phase buckle structure of the TFT of the sub-pixel unit of adjacent lines, adjacent rows is sub-
Pixel cell then offsets one from another less than the width of a sub-pixel unit along described grid line direction, thus reduces
Horizontal band during image display.
The embodiment of the present invention provides a kind of display floater, including the color membrane substrates being oppositely arranged and array base palte,
The array base palte that described array base palte provides for above-described embodiment.
The embodiment of the present invention has the beneficial effect that: the array base palte that display floater is used, by making sub-pix
The gate electrode of the TFT of unit is respectively positioned on the homonymy of respective sub-pixel unit, and the sub-pixel unit of adjacent lines
The grid of TFT forms phase buckle structure, and adjacent rows sub-pixel unit then offsets one from another along described grid line direction
Less than the width of a sub-pixel unit, thus reduce the display floater horizontal band when showing image；Enter
One step, the region that the public electrode wire that array base palte is arranged overlaps with data wire has opening, thus subtracts
The two overlapping parasitic capacitance formed little, improves the display effect of display floater.
The embodiment of the present invention provides a kind of display device, the described display surface provided including above-described embodiment
Plate.
The embodiment of the present invention has the beneficial effect that: the array base palte that display floater is used, by making sub-pix
The gate electrode of the TFT of unit is respectively positioned on the homonymy of respective sub-pixel unit, and the sub-pixel unit of adjacent lines
The grid of TFT forms phase buckle structure, and adjacent rows sub-pixel unit then offsets one from another along described grid line direction
Less than the width of a sub-pixel unit, thus reduce the display floater horizontal band when showing image；Enter
One step, the region that the public electrode wire that array base palte is arranged overlaps with data wire has opening, thus subtracts
The two overlapping parasitic capacitance formed little, improves the display effect of display floater.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte described in prior art；
The structural representation of the array base palte that Fig. 2 provides for the embodiment of the present invention；
Fig. 3 is array base palte schematic cross-section at AA shown in embodiment of the present invention Fig. 2；
Fig. 4 is array base palte schematic cross-section at BB shown in embodiment of the present invention Fig. 2；
The structural representation of the public electrode wire of the array base palte that Fig. 5 provides for the embodiment of the present invention；
The structural representation of the display floater that Fig. 6 provides for the embodiment of the present invention；
The structural representation of the first display device that Fig. 7 provides for the embodiment of the present invention；
The structural representation of the second display device that Fig. 8 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with Figure of description, the embodiment of the present invention is realized process to be described in detail.Should be noted that
, the most same or similar label represents same or similar element or has same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the present invention,
And be not considered as limiting the invention.
Seeing Fig. 2, the embodiment of the present invention provides a kind of array base palte, including substrate 1, is formed at substrate 1
On grid line 2 and sub-pixel unit array, each sub-pixel unit includes TFT3.See Fig. 3, it is shown that
Array base palte schematic cross-section at AA shown in Fig. 2, each sub-pixel unit also includes pixel electrode
8 and public electrode 4, public electrode 4 is comb teeth-shaped structure (generally, including multiple strip shaped electric poles and slit)；
It is additionally provided with data wire 5 on substrate 1 simultaneously.Between data wire 5 place layer and public electrode, passivation layer is set
9.See Fig. 4, it is shown that the schematic cross-section at BB of the array base palte shown in Fig. 2, TFT3 includes grid
Electrode 31, source electrode 32 and drain electrode 33；And gate insulation layer 10, active layer 11, gate insulation layer 10
Be arranged between gate electrode 31 and active layer 11, active layer 11 be arranged at the exhausted layer of grid 10 and source electrode 32,
Being arranged between the exhausted layer of grid 10 and drain electrode 33, source electrode 32 and drain electrode 33 are arranged with layer, and source electricity
Pole 32 directly contacts with pixel electrode 8.It should be noted that Fig. 3 and Fig. 4 is a kind of common Asia picture
The structure of element unit, in other embodiments of the invention, sub-pixel unit can also use other structures, such as picture
Element electrode is positioned on public electrode；Public electrode does not cover data wire, TFT, and public electrode can not also cover
Lid grid line；TFT can also be top gate structure etc.；It is not repeated to illustrate.
As in figure 2 it is shown, in the present embodiment, sub-pixel unit array arrangement mode is as follows: with the most adjacent two
Row sub-pixel unit is a sub-pixel unit group, arranges between two row sub-pixel unit of sub-pixel unit group
Article two, grid line 2, a grid line in the gate electrode of the TFT3 of every a line sub-pixel unit and two grid lines 2
2 corresponding electrical connections；Preferably, a line sub-pix that two grid lines 2 are close with two row sub-pixel unit respectively
Unit electrically connects.The gate electrode 31 of the TFT3 of the lastrow sub-pixel unit in sub-pixel unit group with under
The gate electrode 31 of the TFT3 of a line sub-pixel unit is respectively positioned between two grid lines 2 and is crisscross arranged,
The specifically gate electrode 31 of certain TFT3 of the lastrow sub-pixel unit in sub-pixel unit group is positioned at
Between the gate electrode 31 of adjacent two TFT3 of next line sub-pixel unit, in sub-pixel unit group
The gate electrode 31 of certain TFT3 of next line sub-pixel unit is positioned at the adjacent of lastrow sub-pixel unit
Between the gate electrode 31 of two TFT3.It addition, the gate electrode 31 of each TFT3 is respectively positioned on respective sub-pix
The homonymy of unit, as in figure 2 it is shown, the gate electrode 31 of each TFT3 is respectively positioned on a left side for respective sub-pixel unit
Side.
Two row sub-pixel unit of sub-pixel unit group offset one from another less than a sub-pix along grid line 2 direction
The width of unit.Consider based on sub-pixel unit arrangement and preferably display effect, it is preferred that sub-pix list
Next line sub-pixel unit in tuple has more than or equal to one relative to lastrow sub-pixel unit
The lateral displacement of the width of the gate electrode 31 of TFT3, and lateral displacement is less than or equal to a sub-pixel unit
Width and the difference of width of gate electrode 31 of a TFT3.
In above-mentioned sub-pixel unit array arrangement side, data wire 5 electrically connects with a row sub-pixel unit, and
Each data wire 5 be positioned at the sub-pixel unit being connected electrically the same side (in Fig. 2, with data line bit in
As a example by the left side of the sub-pixel unit of its electrical connection).
In the embodiment of the present invention, the gate electrode 31 of the TFT3 of adjacent rows sub-pixel unit interlocks setting,
Ensure that the aperture opening ratio of sub-pixel unit；While ensureing the aperture opening ratio of sub-pixel unit, adjacent lines
Sub-pixel unit offsets one from another, and effectively reduces horizontal band during display.
Data wire 5 as shown in Figure 2 and public electrode 6.Wherein, data wire 5 includes the first broken line 51,
This first broken line 51 overlaps with public electrode wire 6.Public electrode wire 6 is arranged at neighboring sub-pixel unit group
Between, can arrange with layer with gate electrode 31 and grid line 2；The public electrode wire 6 via 7 by top
Electrically connect with public electrode 4(public electrode 4 as shown in Figure 3).
Seeing Fig. 5, it is shown that the structural representation of public electrode wire 6, it has opening 61, this opening 61
Corresponding with the first broken line 51 of data wire 5, its corresponding relation is as shown in Figure 2.The figure of opening 61 is permissible
For arbitrary graphic, it is preferred that this opening 61 length in the row direction is more than the first broken line of data wire 5
51 length in the row direction.That is, opening 61 meets following condition: the first broken line 51 of data wire 5
Upright projection fall within the upright projection of this opening 61 so that this first broken line 51 of data wire 5 with
This open area no overlap part of public electrode wire 6, reduces data wire 5 and overlaps institute with public electrode wire 6
The parasitic capacitance formed.
As in figure 2 it is shown, data wire 5 also includes that the second broken line 52, the second broken line 52 are arranged at two grid lines
Between 2, thus electrically connect with the drain electrode 33 of sub-pixel unit.
The embodiment of the present invention has the beneficial effect that: by making the gate electrode of the TFT of sub-pixel unit be respectively positioned on respectively
From the homonymy of sub-pixel unit, and the grid of the TFT of the sub-pixel unit of adjacent lines forms phase buckle structure, phase
Adjacent two row sub-pixel unit then offset one from another less than the width of a sub-pixel unit along described grid line direction,
Thus horizontal band when reducing image display；Further, the region that public electrode wire is overlapping with data wire
There is opening, thus reduce the two overlapping parasitic capacitance formed, improve display effect.
Seeing Fig. 6, the embodiment of the present invention provides a kind of display floater, including the color membrane substrates 201 being oppositely arranged
With array base palte 202, the array base palte that array base palte 202 provides for above-described embodiment, at color membrane substrates 201
And liquid crystal layer 203 is set between array base palte 202.Certainly the assembly of other necessity can also be included, such as limit
Frame 205, sealed plastic box 204 etc., do not enumerate at this.
The display floater that the present embodiment is provided, can be as display panels, Electronic Paper, OLED face
Plate, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator etc. are appointed
What has the parts of product of display function.
The embodiment of the present invention has the beneficial effect that: the array base palte that display floater is used, by making sub-pix
The gate electrode of the TFT of unit is respectively positioned on the homonymy of respective sub-pixel unit, and the sub-pixel unit of adjacent lines
The grid of TFT forms phase buckle structure, and adjacent rows sub-pixel unit then offsets one from another along described grid line direction
Less than the width of a sub-pixel unit, thus reduce the display floater horizontal band when showing image；Enter
One step, the region that the public electrode wire that array base palte is arranged overlaps with data wire has opening, thus subtracts
The two overlapping parasitic capacitance formed little, improves the display effect of display floater.
The embodiment of the present invention provides a kind of display device, the display floater provided including above-described embodiment.
The display device that the present embodiment is provided, can be display panels, Electronic Paper, oled panel,
Any tools such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator
There is the product of display function.For example, with reference to the display 300 shown in Fig. 7, including display floater 301；
Again for example, with reference to the mobile phone 400 shown in Fig. 8, including display floater 401.
The embodiment of the present invention has the beneficial effect that: the array base palte that display floater is used, by making sub-pix
The gate electrode of the TFT of unit is respectively positioned on the homonymy of respective sub-pixel unit, and the sub-pixel unit of adjacent lines
The grid of TFT forms phase buckle structure, and adjacent rows sub-pixel unit then offsets one from another along described grid line direction
Less than the width of a sub-pixel unit, thus reduce the display floater horizontal band when showing image；Enter
One step, the region that the public electrode wire that array base palte is arranged overlaps with data wire has opening, thus subtracts
The two overlapping parasitic capacitance formed little, improves the display effect of display floater.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an array base palte, including substrate, the grid line being formed on substrate and sub-pixel unit array,
Each sub-pixel unit includes TFT and public electrode, is one with sub-pixel unit described in two the most adjacent row
Sub-pixel unit group, arranges two grid lines between sub-pixel unit described in two row of described sub-pixel unit group；
It is characterized in that:
The gate electrode of the described TFT of the lastrow sub-pixel unit in described sub-pixel unit group and next line
The gate electrode of the described TFT of sub-pixel unit is respectively positioned between described two grid lines and is crisscross arranged, and respectively
The gate electrode of described TFT is respectively positioned on the homonymy of respective described sub-pixel unit；
Described in two row of described sub-pixel unit group, sub-pixel unit offsets one from another little along described grid line direction
Width in a sub-pixel unit.
2. array base palte as claimed in claim 1, it is characterised in that also include data wire and common electrical
Polar curve；
Described data wire includes that the first broken line, described first broken line overlap with described public electrode wire；
Described public electrode wire is arranged between adjacent described sub-pixel unit group, public with described by via
Electrode electrically connects, and described public electrode wire has the opening corresponding with described first broken line of described data wire.
3. array base palte as claimed in claim 2, it is characterised in that data wire described in one and a row institute
State sub-pixel unit electrical connection, and each described data line bit is in the described sub-pixel unit being connected electrically
The same side.
4. array base palte as claimed in claim 2, it is characterised in that described public electrode wire described
Opening length in the row direction is more than the described first broken line length in the row direction of described data wire.
5. array base palte as claimed in claim 2 or claim 3, it is characterised in that described data wire also includes
Second broken line, described second broken line is arranged between described two grid lines.
6. array base palte as claimed in claim 1, it is characterised in that in described sub-pixel unit group,
The gate electrode of the described TFT of sub-pixel unit described in every a line and described grid in described two grid lines
Line correspondence electrically connects.
7. array base palte as claimed in claim 1, it is characterised in that in described sub-pixel unit group
Described next line sub-pixel unit has more than or equal to an institute relative to described lastrow sub-pixel unit
State the lateral displacement of the width of the gate electrode of TFT, and described lateral displacement is less than or equal to described sub-pix list
The difference of the width of the width of unit and the gate electrode of a described TFT.
8. array base palte as claimed in claim 1, it is characterised in that the pixel of described sub-pixel unit
Electrode directly contacts with the source electrode of described TFT.
9. a display floater, including the color membrane substrates being oppositely arranged and array base palte, it is characterised in that
Described array base palte is the array base palte described in any one of claim 1 to 8.
10. a display device, it is characterised in that include display floater as claimed in claim 9.
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| CN201310589624.7A CN103926768B (en) | 2013-11-20 | 2013-11-20 | A kind of array base palte, display floater and display device |
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| CN201310589624.7A CN103926768B (en) | 2013-11-20 | 2013-11-20 | A kind of array base palte, display floater and display device |
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| CN103926768B true CN103926768B (en) | 2016-09-07 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104483788B (en) * | 2014-10-10 | 2018-04-10 | 上海中航光电子有限公司 | Dot structure and its manufacture method, array base palte, display panel and display device |
| CN106502474B (en) * | 2017-01-12 | 2019-04-26 | 京东方科技集团股份有限公司 | A kind of array substrate and display panel |
| CN107085335A (en) * | 2017-04-20 | 2017-08-22 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof |
| CN107767773A (en) * | 2017-10-12 | 2018-03-06 | 惠科股份有限公司 | Array substrate and display device applying same |
| CN108269503A (en) * | 2018-03-26 | 2018-07-10 | 上海天马微电子有限公司 | Display panel and display device |
| US11869898B2 (en) * | 2020-04-01 | 2024-01-09 | Beijing Boe Display Technology Co., Ltd. | Array substrate and display device |
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