CN103914664A - Controller and control method having interior memory bank protecting function - Google Patents
Controller and control method having interior memory bank protecting function Download PDFInfo
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- CN103914664A CN103914664A CN201210593382.4A CN201210593382A CN103914664A CN 103914664 A CN103914664 A CN 103914664A CN 201210593382 A CN201210593382 A CN 201210593382A CN 103914664 A CN103914664 A CN 103914664A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
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Abstract
The invention discloses a controller having an interior memory bank protecting function. The controller having the interior memory bank protecting function comprises an interface module, a memory bank, a memory bank controller, an inner core controller and a protection logic module; the protection logic module is connected between the interface module and the memory bank controller; the protection logic module is connected with the inner core controller; the protection logic module is used for judging whether request messages received by the interface module are request messages for accessing the memory bank, the protection logic module sends messages to the inner core controller to enable the controller to be in a normal working state if the request messages are not the request messages for accessing the memory bank, and the protection logic module sends messages to the inner core controller to enable the controller to be in a protection limit state if the request messages are the request messages for accessing the memory bank. The controller has the advantages of enabling hardware design costs to be low and is high in protection intensity to be high, convenient to use and compatible with an online upgrading function of MCU products effectively. The invention also discloses a control method having the interior memory bank protecting function.
Description
Technical field
The present invention relates to control information technical field, particularly a kind of controller and control method with internal repository defencive function.
Background technology
At present, for MCU microcontroller field, no matter at 8 MCU, or in 16 or 32 s' MCU, generally can be divided into two kinds to the protected mode of its inside eFlash memory bank program: one is normally to realize based on a series of protection configuration registers and protection configuration words; Another kind is to realize based on key mechanism and associated encryption algorithm.
Above-mentioned first kind of way is mainly passed through hardware logic electric circuit; design several defencive function configuration registers; according to values different in these configuration registers, select different hardware logics, realize the protection of reading, wiping and the writing operation of corresponding eFlash internal processes.MCU manufacturer protects configuration words according to different clients for the NVR that eFlash memory bank is read, wiping is different with write-protected requirements set.During MCU electrifying startup, hardware logic is read the configuration words in eFlash memory bank NVR region automatically, sends in protection configuration register.Hardware circuit, by according to the setting in protection configuration register, is taked different safeguard measures: as a read protection, erasable protection afterwards.These protections do not affect MCU and normally work, the erasable operation of reading to eFlash can not limit CPU and normally work time; When MCU is operated under debugging or upgrade mode, this protected mode is effective, to limit illegal third party according to actual disposition and utilize debugging method that program is cracked and reads or destroy internal processes, invalid to data writing in eFlash by this class interface, from eFlash, attempt sense data conductively-closed; The another kind of protection based on key mechanism and cryptographic algorithm realization mainly realizes by the form of software algorithm.Such algorithm routine is implanted in eFlash memory bank by MCU manufacturer or product development business.This subprogram can not be read and be programmed by any external debug means or interface, only has the client of legitimate secret by the input of outside correct key, debugging restriction, eFlash could be read to erasable restriction and cryptographic algorithm amendment restriction cancellation.In two kinds of MCU, the mode of eFlash programmed protection is widely used on different product according to different MCU production development business, can guarantee the program confidentiality of general application product, and protection application program is not illegally modified or steals.
Further; use protection configuration register and protection configuration words to realize eFlash programmed protection in MCU; due to protection restriction scheme, the MCU can not be to normal work time exerts an influence; need the ROMPaq in CPU operation eFlash to realize by external communication interface refresh routine in On-line Product upgrading; so hardware protection logical circuit is mainly to realize in debug port, debug logic or communication port; only for limiting the legitimacy of interface data, and for the data of eFlash memory bank and controller itself less than protection.Due to NVR region non-volatile, power on and read the stationarity of configuration words process; so just limited by the protection of initial setting when normal MCU brings into operation; eFlash need to be all wiped in de-preservation restriction; the online upgrading function that therefore cannot realize MCU, is unfavorable for the continuity of MCU product.Meanwhile, such guard method needs to increase extra steering logic on hardware is realized, and control register classification is more, realizes comparatively complexity, and cost is higher.
Protection based on key mechanism and cryptographic algorithm realization is without extra hardware control logic; only need by the processing of the key process algorithm routine of input; it is legal to judge whether, and then restriction or releasing external debug interface or the operation of upgrading communication interface to eFlash memory bank in MCU.Such protection application is simple and convenient, but lacks the support of hardware logic, is easily utilized software and hardware leak or the exhaustive of key cracked, and product is caused and had a strong impact on.
Prior art is mainly to control configuration words by hardware circuit and protection to be limited in outside data path and the operation to eFlash memory bank in MCU of outside port logic place restriction, steering logic relative complex, configure rear protected mode unique, to belonging to the protection of passive mode; Or utilize key mechanism and relevant software and hardware algorithm, judge that key legitimacy determines whether eFlash to be protected, belong to passive protection mode, easily cracked by exhaustive.
Summary of the invention
Object of the present invention is intended at least solve one of described technological deficiency.
For this reason, first object of the present invention is to propose a kind of controller with internal repository defencive function, and this controller makes that cost of hardware design is low, protection is high, application is convenient, the online upgrading function of effective compatible MCU product.Second object of the present invention is to propose a kind of control method with internal repository defencive function.
To achieve these goals, the embodiment of first aspect present invention provides a kind of controller with internal repository defencive function, comprising: interface module, memory bank and bank controller, kernel controller, and protection logic module, described protection logic module is connected between described interface module and described bank controller, and described protection logic module is connected with described kernel controller, described protection logic module is for judging whether the request message that described interface module receives is the access request message to described memory bank, if be not the access request message to described memory bank, described protection logic module sends message so that controller enters normal operating conditions to described kernel controller, access request message to described memory bank if, described protection logic module sends message so that controller enters protection restriction state to described kernel controller.
According to the controller with internal repository defencive function of the embodiment of the present invention, not protected restriction when MCU normally works, in the time receiving outer needles to MCU inside eFlash memory bank operation requests, starting protection limitation function.This controller makes that cost of hardware design is low, protection is high, application is convenient, the online upgrading function of effective compatible MCU product.
The embodiment of second aspect present invention proposes a kind of control method with internal repository defencive function, comprises the following steps: receive request message; And after receiving described request message, judge whether described request message is the access request message to memory bank; If be not the access request message to described memory bank, inwardly nuclear control device sends message, so that controller enters normal operating conditions; And the access request message to described memory bank if, send message to described kernel controller, so that controller enters protection restriction state.
According to the control method with internal repository defencive function of the embodiment of the present invention, not protected restriction when MCU normally works, in the time receiving outer needles to MCU inside eFlash memory bank operation requests, starting protection limitation function.This control method makes that cost of hardware design is low, protection is high, application is convenient, the online upgrading function of effective compatible MCU product.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Brief description of the drawings
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is according to the structural representation of the controller with internal repository defencive function of the embodiment of the present invention;
Fig. 2 is the structural representation according to another embodiment of the present invention with the controller of internal repository defencive function;
Fig. 3 protects the schematic diagram of logical circuit in system in MCU;
Fig. 4 be protection logical block in system with the schematic diagram of external debug interface and eFlash control unit interface;
Fig. 5 is that overall hardware is realized schematic diagram;
Fig. 6 is for realizing and implementation and operation processing flow chart;
Fig. 7 is according to the process flow diagram of the control method with internal repository defencive function of the embodiment of the present invention; And
Fig. 8 is the process flow diagram according to another embodiment of the present invention with the control method of internal repository defencive function.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " " center ", " longitudinally ", " laterally ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of instructions such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of device or the element of instruction or hint indication must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.
In addition, term " first ", " second " be only for describing object, and can not be interpreted as instruction or hint relative importance or the implicit quantity that indicates indicated technical characterictic.Thus, one or more these features can be expressed or impliedly be comprised to the feature that is limited with " first ", " second ".In description of the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the terms such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and for example, can be to be fixedly connected with, and can be also to removably connect, or connect integratedly; Can be mechanical connection, can be also electrical connection; Can be to be directly connected, also can indirectly be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, can understand as the case may be above-mentioned term concrete meaning in the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but by the other feature contact between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is less than Second Characteristic.
As shown in Figure 1, structural representation Figure 100 of the controller with internal repository defencive function of the embodiment of the present invention, comprising: interface module 110, memory bank 120 and bank controller 130, kernel controller 140 and protection logic module 150.
Between protection logic module 150 connection interface module 110 and bank controller 130, and protection logic module 150 is connected with kernel controller 140, whether protection logic module 150 is the access request message to memory bank 120 for the request message that judges interface module 110 and receive, if be not the access request message to memory bank, protect the inside nuclear control device 140 of logic module 150 to send message so that controller enters normal operating conditions, access request message to memory bank 120 if, protect the inside nuclear control device 140 of logic module 150 to send message so that controller enters protection restriction state.
Further; after controller enters protection restriction state; protection logic module 150 receives the identifying code of outside input by interface module 110; and identifying code is verified; after identifying code is by checking, protection logic module 150 operates memory bank 120 according to request message by bank controller 130.
Particularly, protection logic module 150 is upgraded the errors number of preserving in memory bank 120.Further; after the errors number of preserving in memory bank is greater than preset times; protection logic module 150 writes lock flag in memory bank 120; with lockout controller; and after controller lock; after protection logic module 150 receives erasing instruction by interface module 110, protection logic module 150 is wiped memory bank 120 by bank controller 130.
Protection logic module 150 is also for after identifying code is by checking, by the errors number zero clearing of preserving in memory bank 120.
As shown in Figure 2; structural representation Figure 100 of the controller with internal repository defencive function of another embodiment of the present invention; protection logic module also comprises: register 1501, judge submodule 1502, and errors number is added up submodule 1503 and from lock control submodule 1504.
The identifying code that register 1501 receives for store interface module 110 and instruction.
Judge submodule 1502 for the identifying code that judges register and preserve whether by checking.
Errors number statistics submodule 1503 is for judge that submodule 1502 judges that identifying code does not upgrade errors number after verifying.
From lock control submodule 1504, after being greater than preset times for errors number statistical module 1503 misjudgment number of times, from lock control submodule 1504, lock flag is write in memory bank 120, with lockout controller.
According to the controller with internal repository defencive function of the embodiment of the present invention, not protected restriction when MCU normally works, in the time receiving outer needles to MCU inside eFlash memory bank operation requests, starting protection limitation function.This controller makes that cost of hardware design is low, protection is high, application is convenient, the online upgrading function of effective compatible MCU product.
Fig. 3 is the schematic diagram of MCU protection logical circuit in system.
As shown in Figure 3, the MCU protection logical circuit in system comprises: CPU, and miscellaneous equipment, eFlash memory bank, eFlash controller, protection logical circuit, interface, wherein interface comprises debugging interface, upgrade interface, DLL (dynamic link library).
Particularly, protection logical circuit is associated with eFlash controller and debugging interface, and eFlash controller and eFlash memory bank are associated, and adopt with 32 bit CPUs the MCU system of ahb bus framework in embodiment.
Further, not protected restriction when MCU normally works, in the time receiving outer needles to MCU inside eFlash memory bank operation requests, enables protection limitation function.In the time that illegal request reaches certain number of times, this MCU will automatically lock, and can be considered the stage 1, wherein, can return to the stage 1 by the stage 2, cannot normally work.Wherein, illegal request cumulative number,, with MCU power down or the impact that resets, can totally not preserve.In the time again receiving illegal unlocking request; this unlocking request key is different from protection releasing request key; MCU will cut off eFlash and control and data path; outside all orders for eFlash operation are invalid; cause current MCU can only carry out unique operation, outside is sent eFlash full wafer and is wiped request, wipes all programs; be the stage 2, irrecoverable.When MCU chip is during in stage 2, after full wafer is wiped, person can recover the original function of this MCU only to have production development, thereby has the initiative in hands, and improves produce market status and competitive power.
Fig. 4 be protection logical block in system with the schematic diagram of external debug interface and eFlash control unit interface.
As shown in Figure 4, eFlash controller is interrelated with protection logical circuit and eFlash memory bank, and protection logical circuit and interface module are interrelated, and wherein interface module comprises: debugging interface, upgrade interface, DLL (dynamic link library).
Particularly, not protected logical restriction when MCU normally works, MCU inside is normal to the access of eFlash, and PERCOM peripheral communication is subject to MCU programmed control; For example, when have pair MCU inside eFlash memory bank operation requests when outside: debugging, upgrading, first need to write 16 PR registers by external communication interface and send peripheral operation request.This input key PR_KEY is together with inside coupling ciphering key P_KEY, the unique ID identifier of this MCU, only provide legal authorization side; When writing after the value identification error of PR register, logical circuit write by multiplexing eFlash controller by MCU system, record external request lifts restrictions so far the errors number Pro_Info district to eFlash memory bank, this number of times only MCU legal authorization side is inputted after legal PR value, by erasable removing the to eFlash memory bank Pro_Info district automatically of eFlash controller; In the time that cumulative requests errors number reaches design code number of times, whole MCU system locks oneself.After this, MCU will keep the state that cannot work always, and externally provides indication information MCU_LOCK; But outside is addressable PR register still, when after MCU oneself locking, can separate drop lock PR_UL_KEY by continuing to write another to PR register, this value is different with operation requests value; When separating after drop lock input correctly, MCU will remove self-lock-out state, false request number of times before simultaneously removing.MCU chip recovers original function.When separating after drop lock input error, MCU system will be cut off control and the data path of eFlash and system, and outside and any operation for eFlash of system are by invalid.Now need outside to write the full wafer request of wiping to PR register, eFlash is carried out to data and all wipe, recover MCU chip original state, make illegally to crack and lose meaning.MCU under original state can the person's of being developed reprogramming, gets back to product function and defencive function state.
Further, in whole design, main operation realizes equal reusable eFlash controller function, except decision logic, without separately adding hardware logic.The full wafer erase operation of eFlash is initiatively sent by external request, sends auto-erasing operation after being different from release failure.Like this can people for guaranteeing MCU reliability, greatly reduce chip and damage risk.
Fig. 5 is that overall hardware is realized schematic diagram.
In specific embodiment: define the request key that 16 RP registers send for receiving outside GPIO; Decision logic carries out logic judgement to the coupling of different external request mark EXT_REQ and PR_KEY respectively; Number of times is added up and is carried out self-lock protection from lock control according to request number of times REQ_NUM and PR_UL_KEY; The protection information that each protection generates will be stored in eFlash memory bank by eFlash controller.
Further, by pure hardware circuit, efficient multiplexing eFlash controller logic, increases on decision logic basis, realizes self-locking limitation function, initiatively protects and prevents cracking behavior, and effectively inhibition illegally cracks.Meanwhile, full wafer erase operation in protection, the stage 2 is sent with active form by external request, and reliability is improved, and effectively reduces chip and damages risk.
Fig. 6 is for realizing and implementation and operation processing flow chart.
Particularly; in enforcement, taking protection request maximum times is 10 times; the unique ID value of system is 32 ＇ h5D7A_83D9; coupling ciphering key P_KEY value is 32 ＇ h8719_A102; the PR value that asks for permission is 16 ＇ h261B(16 ＇ h8719^16 ＇ hA102), release license PR value is 16 ＇ hDEA3(16 ＇ h5D7A^16 ＇ h83D9).Wiping request PR value is 16 ＇ hffff.
Step S601 is that MCU starts.
Step S602 is for resetting.Particularly, PR register value is: 16 ＇ b0.
Particularly, when MCU system normally starts, PR default value is 16 ＇ h0000.Starting to carry out example procedure, is to circulate and write number operation in the space of 0X4000_0000 to address, is worth for successively increasing progressively since 1.
Step S603 is for reading Pro_Info district data in eFlash.
Step S604 is for to judge that whether MCU is in self-locking state.
Step S605 is if judge that MCU, not in self-locking state, normally works, and forbids outside eFlash being accessed.
Step S606, for external request access eFlash event occurs in judgement, comprising debugging, upgrades, the requests such as programming.
Step S607 is 1 for putting external request Status Flag EXREQ_FLAG value, requires outside input PR value simultaneously.
Step S608 is for to judge whether PR is 16 ＇ h261B.
Step S609 is for to judge that PR is 16 ＇ h261B, and the protection of eFlash external reference is removed, request error number of times REQ_NUM clear 0.Particularly, execution step S620 is that outside can be read eFlash program, erasable operation, and final step S621 is for to have operated, and step S622 is for resetting.
Further, input PR value is 16 ＇ h261B, and now external request is passed through, and e Fla sh memory bank can normally be accessed in outside, can read erasable operation to it.Reading address is the eFlash space of 0x0000_0100, and read value is coupling, correct.Erasable address is that the eFlash space of 0x0000_0f00 is 0x0000_aaaa, reads back, correct.Operate rear reset.
Step S610 is for to judge that PR is not 16 ＇ h261B, request error number of times REQ_NUM+1, and this value writes Pro_Info district simultaneously.
Particularly, input PR value is 16 ＇ h1234, checks that errors number REQ_NUM value is 1, and the eFlash space that reading address is 0x0000_0100, is worth for 0xffff_ffff, reads failure.Erasable address is that the eFlash space of 0x0000_0f00 is 0x0000_aaaa, and checking is read back, and finds that the value of reading back is not equal to 0x0000_aaaa, writes failure.Protection effectively.
Step S611 is for judging now whether REQ_NUM value is 10.
Step S612 is for judging that now REQ_NUM value is at 10 o'clock, and putting lock flag MCU_LOCK value is 1, this value is write to Pro_Info district simultaneously.
Particularly, write continuously PR value and unsuccessfully reach 10 times, the self-locking of MCU system, now operating 1 example procedure cannot move, and MCU normal function is locked.MCU_LOCK value is 1.
Particularly, in the time judging that now REQ_NUM value is not 10, perform step S623 and send request for judgement continues to write PR value.
Step S613 is that MCU is in self-locking state.
Step S614 is for judging whether that writing PR separates drop lock.
Step S615 separates drop lock for judgement writes PR, continues to judge that whether solution drop lock PR is correct.
Particularly, step S615, for judgement solution drop lock PR is correct, performs step S607.
For example: input release PR value is 16 ＇ hDEA3, checks that REQ_NUM value is that 0, MCU_LOCK value is 0, MCU release, can normally carry out.
Step S616 is incorrect for judgement solution drop lock PR, and MCU locks completely, irrecoverable, can only send full wafer by outside and wipe request.
Particularly, for example: input release PR value is 16 ＇ h4321, and it fails to match, now invalid to any operation of MCU.
Step S617 judges for continuing whether PR is 16 ＇ hfff.
Particularly, it is 16 ＇ hffff that PR value is wiped in input, performs step S618, and checking finds that eFlash is all wiped free of.
Step S619 is that MCU is in original factory state.
The reinforcement of the very big degree of above-mentioned implementation procedure eFlash program code protection, become passive protection for initiatively protecting; There is self-locking feature, even if manage to crack, the also restriction above and on number of times if having time; Traditional scheme cannot be supported online upgrading, debugging and programming simultaneously, and this scheme is effectively supported the debugging of outer needles to MCU and the restriction of online upgrading, instead of single carrying out debugging protection or upgrading protection; In realization, multiplexing eFlash controls function, and applicability is better; Hardware circuit is realized, and multiplexing MCU existing capability is safe; Send eFlash full wafer erase operation in active request mode, without considering that power supply postpones powerup issue, reduce extra cost, reliability is high, and risk is low.
As shown in Figure 7, the process flow diagram of the control method with internal repository defencive function of the embodiment of the present invention, comprises the steps:
Step S701 is for receiving solicited message.
Step S702, for after receiving request message, judges whether request message is the access request message to memory bank.
Step S703 is that inwardly nuclear control device sends message, so that controller enters normal operating conditions if be not the access request message to memory bank.
Step S704 is the access request message to memory bank if, and inwardly nuclear control device sends message, so that controller enters protection restriction state.
As shown in Figure 8, the process flow diagram of the control method with internal repository defencive function of another embodiment of the present invention, comprises the steps:
Step S705 is the identifying code that receives outside input, and identifying code is verified, after identifying code is by checking, memory bank is operated according to request message by bank controller.
Particularly, after identifying code is by checking, upgrade the errors number of preserving in memory bank, and by the errors number zero clearing of preserving in memory bank; After judging that the errors number of preserving in memory bank is greater than preset times, lock flag is write in memory bank, with lockout controller.
Further, after receiving solution drop lock, eliminate lock flag; And after receiving erasing instruction, by bank controller, memory bank is wiped.
According to the control method with internal repository defencive function of the embodiment of the present invention, not protected restriction when MCU normally works, in the time receiving outer needles to MCU inside eFlash memory bank operation requests, starting protection limitation function.This control method makes that cost of hardware design is low, protection is high, application is convenient, the online upgrading function of effective compatible MCU product.
Any process of otherwise describing in process flow diagram or at this or method are described and can be understood to, represent to comprise that one or more is for realizing module, fragment or the part of code of executable instruction of step of specific logical function or process, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can be not according to order shown or that discuss, comprise according to related function by the mode of basic while or by contrary order, carry out function, this should be understood by embodiments of the invention person of ordinary skill in the field.
The logic and/or the step that in process flow diagram, represent or otherwise describe at this, for example, can be considered to the sequencing list of the executable instruction for realizing logic function, may be embodied in any computer-readable medium, use for instruction execution system, device or equipment (as computer based system, comprise that the system of processor or other can and carry out the system of instruction from instruction execution system, device or equipment instruction fetch), or use in conjunction with these instruction execution systems, device or equipment.With regard to this instructions, " computer-readable medium " can be anyly can comprise, device that storage, communication, propagation or transmission procedure use for instruction execution system, device or equipment or in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wirings, portable computer diskette box (magnetic device), random-access memory (ram), ROM (read-only memory) (ROM), the erasable ROM (read-only memory) (EPROM or flash memory) of editing, fiber device, and portable optic disk ROM (read-only memory) (CDROM).In addition, computer-readable medium can be even paper or other the suitable medium that can print described program thereon, because can be for example by paper or other media be carried out to optical scanning, then edit, decipher or process in electronics mode and obtain described program with other suitable methods if desired, be then stored in computer memory.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple steps or method can realize with being stored in software or the firmware carried out in storer and by suitable instruction execution system.For example, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: there is the discrete logic for data-signal being realized to the logic gates of logic function, there is the special IC of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is can carry out the hardware that instruction is relevant by program to complete, described program can be stored in a kind of computer-readable recording medium, this program, in the time carrying out, comprises step of embodiment of the method one or a combination set of.
In addition, the each functional unit in each embodiment of the present invention can be integrated in a processing module, can be also that the independent physics of unit exists, and also can be integrated in a module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.If described integrated module realizes and during as production marketing independently or use, also can be stored in a computer read/write memory medium using the form of software function module.
The above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
In the description of this instructions, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, amendment, replacement and modification.Scope of the present invention is extremely equal to and limits by claims.
Claims (14)
1. a controller with internal repository defencive function, is characterized in that, comprising:
Interface module;
Memory bank and bank controller;
Kernel controller; And
Protection logic module, described protection logic module is connected between described interface module and described bank controller, and described protection logic module is connected with described kernel controller, described protection logic module is for judging whether the request message that described interface module receives is the access request message to described memory bank, if be not the access request message to described memory bank, described protection logic module sends message so that controller enters normal operating conditions to described kernel controller, access request message to described memory bank if, described protection logic module sends message so that controller enters protection restriction state to described kernel controller.
2. the controller with internal repository defencive function as claimed in claim 1; it is characterized in that; after described controller enters protection restriction state; described protection logic module receives the identifying code of outside input by described interface module; and described identifying code is verified; after described identifying code is by checking, described protection logic module operates described memory bank according to described request message by described bank controller.
3. the controller with internal repository defencive function as claimed in claim 2, is characterized in that, after described identifying code is by checking, described protection logic module is upgraded the errors number of preserving in described memory bank.
4. the controller with internal repository defencive function as claimed in claim 3, is characterized in that, described protection logic module is also for after described identifying code is by checking, by the errors number zero clearing of preserving in described memory bank.
5. the controller with internal repository defencive function as claimed in claim 3; it is characterized in that; after the errors number of preserving in described memory bank is greater than preset times, described protection logic module writes lock flag in described memory bank, to lock described controller.
6. the controller with internal repository defencive function as claimed in claim 5, is characterized in that, when described protection logic module receives solution drop lock by described interface module after, eliminates described lock flag.
7. the controller with internal repository defencive function as claimed in claim 5; it is characterized in that; after described controller lock; after described protection logic module receives erasing instruction by interface module, described protection logic module is wiped described memory bank by described bank controller.
8. the controller with internal repository defencive function as claimed in claim 1, is characterized in that, described protection logic module comprises:
Register, the identifying code and the instruction that receive for storing described interface module;
Judge submodule, for judging whether the identifying code that register is preserved passes through checking;
Errors number statistics submodule, for judging that at described judgement submodule identifying code is not by upgrading errors number after checking.
9. the controller with internal repository defencive function as claimed in claim 8, is characterized in that, described protection logic module also comprises:
From lock control submodule, for after described errors number statistical module misjudgment number of times is greater than preset times, described from lock control submodule, lock flag being write in described memory bank, to lock described controller.
10. a control method with internal repository defencive function, is characterized in that, comprises the following steps:
Receive request message, and after receiving described request message, judge whether described request message is the access request message to memory bank;
If be not the access request message to described memory bank, inwardly nuclear control device sends message, so that controller enters normal operating conditions; And
Access request message to described memory bank if, sends message to described kernel controller, so that controller enters protection restriction state.
11. control methods with internal repository defencive function as claimed in claim 10; it is characterized in that; sending message to described kernel controller; so that entering protection restriction state, controller further comprises: the identifying code that receives outside input; and described identifying code is verified; after described identifying code is by checking, described memory bank is operated according to described request message by described bank controller.
12. control methods with internal repository defencive function as claimed in claim 11, is characterized in that, after described identifying code is by checking, also comprise:
Upgrade the errors number of preserving in described memory bank, and
By the errors number zero clearing of preserving in described memory bank.
13. control methods with internal repository defencive function as claimed in claim 11, is characterized in that, after described identifying code is by checking, also comprise:
After judging that the errors number of preserving in memory bank is greater than preset times, lock flag is write in described memory bank, to lock described controller.
14. control methods with internal repository defencive function as claimed in claim 13, is characterized in that, after locking described controller, also comprise:
After receiving solution drop lock, eliminate described lock flag; And after receiving erasing instruction, by described bank controller, described memory bank is wiped.
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| CN201210593382.4A CN103914664A (en) | 2012-12-31 | 2012-12-31 | Controller and control method having interior memory bank protecting function |
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| CN201210593382.4A CN103914664A (en) | 2012-12-31 | 2012-12-31 | Controller and control method having interior memory bank protecting function |
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Application publication date: 20140709 |