CN103795502B

CN103795502B - Data frame check code generating method and device

Info

Publication number: CN103795502B
Application number: CN201410070453.1A
Authority: CN
Inventors: 魏初舜
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: New H3C Semiconductor Technology Co Ltd
Priority date: 2014-02-28
Filing date: 2014-02-28
Publication date: 2017-04-12
Anticipated expiration: 2034-02-28
Also published as: CN103795502A

Abstract

The invention discloses a data frame check code generating method. The method comprises the following steps: when a data frame is received or sent, calculating a CRC code according to the data frame, and when the CRC code is calculated, processing multi-bit parallel data one by one on the basis of logic design. On the basis of the same invention concept, the invention further discloses a device, and under the condition of saving resources, the device can accurately and fast calculate the CRC code so as to meet the requirement for the data transmission rate.

Description

Data frame check code generation method and device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for generating a data frame check code.

Background

Cyclic Redundancy Check (CRC) is an error detection code that has a high error detection probability and is easy to implement in hardware. The CRC code is generated by a generator polynomial of which the highest power is r +1, and the generator polynomial of which the highest power is r +1 can generate a redundancy code of r bits. The appropriate selection of the generator polynomial enables the CRC code to detect random bit errors of all parity bits and burst bit errors with burst lengths less than or equal to r.

CRC checks are widely used in communication and memory systems. When data is transmitted and received, in order to adapt to the actual requirements of interfaces with higher speed, such as 10Gbps ethernet, 40Gbps ethernet, 100Gbps ethernet interfaces and the like, it is necessary to provide an improved scheme for a circuit structure on the basis of realizing serial CRC, and to realize parallel computation of CRC, so that the method can be further applied to the data input condition with multi-bit data width.

At present, when data is transmitted and received, methods for calculating CRC mainly include two methods: first, a parallel algorithm based on a look-up table structure obtains the CRC. The depth of a lookup table required by the method during implementation and the parallel processing bit width are in a power relation of 2, and the method is not suitable for performing parallel processing with large bit width; secondly, the CRC is acquired based on a parallel algorithm of logic design, the method is difficult to realize, more logic resources are occupied by combinational logic, or the working speed is difficult to improve.

Therefore, it is seen that a method for rapidly calculating CRC check codes under the condition of resource saving needs to be provided in reality, so as to meet the requirement of continuously increasing data transmission rate.

Disclosure of Invention

In view of this, the present invention provides a method and an apparatus for generating a data frame check code, which can accurately and quickly calculate a CRC check code under the condition of saving resources, thereby satisfying a data transmission rate.

In order to solve the technical problem, the technical scheme of the invention is realized as follows:

a method for generating a check code of a data frame, the method comprising:

when sending the data frame, calculating the CRC check code of the data frame, and sending the calculated CRC check code together with the data frame;

when a data frame is received, calculating a CRC (cyclic redundancy check) code of the data frame to judge whether the received data frame is wrong;

wherein, the calculating the CRC check code of the data frame includes:

for the r +1 CRC generator polynomial, reading the data frame successively from the frame of the data frame by taking w bits as a unit; wherein w is not less than r;

aiming at the ith read data, obtaining input data and a first temporary CRC remainder calculated by the higher-order CRC matrix transformation through alignment processing according to a CRC initial value; wherein, I is the number of times of reading the data frame, I is an integer from 1 to I, and when I is 1, the CRC initial value is a preset r-bit initial value; when i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read for the (i-1) th time;

transforming the calculated input data by a high-order CRC matrix to obtain a second temporary CRC remainder;

performing XOR calculation on the first temporary CRC remainder and the second temporary CRC remainder, and when I is determined to be equal to I, taking an XOR result as a CRC check code of the data frame; and when I is determined to be smaller than I, calculating the CRC initial value of the CRC check code by taking the exclusive OR result as the data read for the (I +1) th time.

An apparatus, the apparatus comprising: the device comprises a calculation unit, a sending unit, a receiving unit and a processing unit;

the calculating unit is used for calculating the CRC code of the data frame when the sending unit sends the data frame; when the receiving unit receives a data frame, calculating a CRC (cyclic redundancy check) code of the data frame;

the sending unit is used for sending the CRC code of the data frame calculated by the calculating unit together with the data frame;

the receiving unit is used for receiving a data frame;

the processing unit is used for judging whether the data frame received by the receiving unit is wrong or not according to the CRC code calculated by the calculating unit according to the data frame received by the receiving unit;

wherein the calculation unit includes: the device comprises an alignment unit, a high-order CRC calculation unit and an exclusive OR unit;

the alignment unit is used for reading the data frame from the frame of the data frame successively by taking w bits as a unit aiming at the CRC generator polynomial of the r +1 times; aiming at the ith read data, obtaining input data and a first temporary CRC remainder calculated by the higher-order CRC matrix transformation through alignment processing according to a CRC initial value; w is not less than r, I is the number of times of reading the data frame, I is an integer from 1 to I, and when I is 1, the CRC initial value is a preset r-bit initial value; when i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read for the (i-1) th time;

the high-order CRC calculation unit is used for transforming the input data calculated by the alignment unit through a high-order CRC matrix to obtain a second temporary CRC remainder;

the XOR unit is used for carrying out XOR calculation on the first temporary CRC remainder calculated by the alignment unit and a second temporary CRC remainder obtained by the high-order CRC calculation unit after high-order matrix transformation, and when I is equal to I, the XOR result is used as a CRC check code of the data frame; and when I is smaller than I, returning the exclusive OR result to the alignment unit as a CRC initial value for calculating a CRC check code for the data read at the (I +1) th time.

the receiving unit is used for receiving a data frame;

wherein the calculation unit includes: the device comprises a first alignment unit, a first high-order CRC calculation unit, a first exclusive OR unit, a second alignment unit, a second high-order CRC calculation unit and a second exclusive OR unit;

the first alignment unit is configured to sequentially read the data frame from a frame of the data frame in units of w bits for the CRC generator polynomial of the order r + 1; aiming at the ith read data, obtaining input data and a first temporary CRC remainder calculated by the higher-order CRC matrix transformation through alignment processing according to a CRC initial value; w is not less than r, I is the number of times of reading the data frame, I is an integer from 1 to I-1, and when I is 1, the CRC initial value is a preset r-bit initial value; when i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read for the (i-1) th time;

the first high-order CRC calculation unit is used for transforming the input data calculated by the first alignment unit through a high-order CRC matrix to obtain a second temporary CRC remainder;

the first exclusive-or unit is configured to perform exclusive-or calculation on a first temporary CRC remainder calculated by the first alignment unit and a second temporary CRC remainder obtained by the first high-order CRC calculation unit, and when I is smaller than I-1, use an exclusive-or result as a CRC initial value of a CRC check code calculated for the I +1 th read data; when I is equal to I-1, sending an exclusive OR result to the second alignment unit as a CRC initial value calculated by the second alignment unit;

the second alignment unit is used for reading the data left after the first alignment unit reads the data for the I-1 th time, and obtaining input data calculated by the second high-order CRC matrix transformation and a first temporary CRC remainder for the data read for the I-1 th time through alignment processing according to the effective bit quantity of the data read for the time and an XOR result calculated by the first XOR unit aiming at the CRC code of the data read for the I-1 time;

the second high-order CRC calculation unit is used for transforming the input data calculated by the second alignment unit through a high-order CRC matrix to obtain a second temporary CRC remainder aiming at the I-th read data;

and the second exclusive-or unit is configured to perform exclusive-or calculation on the first temporary CRC remainder calculated by the second alignment unit and the second temporary CRC remainder obtained by the second high-order CRC calculation unit, and use the exclusive-or calculation result as a CRC check code of the data frame.

In summary, the CRC check code is calculated according to the data frame when the data frame is received or transmitted, and when the CRC check code is calculated, the multi-bit parallel data is processed one by one based on the logic design, so that the CRC check code can be calculated accurately and quickly while resources are saved, and thus, the data transmission efficiency is satisfied.

Drawings

Fig. 1 is a schematic flow chart illustrating a process of calculating a check code according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of an apparatus employing the above embodiments in an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a computing unit according to a fifth embodiment of the present invention;

FIG. 4 is a diagram illustrating an internal structure of a high level CRC calculation unit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a computing unit in a sixth embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiment of the invention provides a method for generating a data frame check code, when equipment receives or sends a data frame, the equipment calculates the CRC check code according to the data frame, and when the CRC check code is calculated, the multi-bit parallel data is processed one by one based on logic design, so that the CRC check code can be calculated accurately and quickly under the condition of saving resources, and the data transmission efficiency is further met.

When the device serves as a sending end and sends a data frame, the CRC code of the data frame is calculated, and the calculated CRC code and the data frame are sent together.

When the device is used as a receiving end and receives a data frame, the CRC code of the data frame is calculated so as to judge whether the received data frame has errors.

If the calculated check code of the data frame is the same as the check code of the data frame, the received data frame is considered to be correct; otherwise, the received data frame is considered to be erroneous.

In specific implementation, the CRC check code generation method provided by the present invention can be used for calculating the CRC check code of the data frame, and the application of the CRC check code generation method to the data frame and the check data frame is not limited.

How to calculate the CRC check code when the device is used as a receiving end or as a transmitting end in the embodiments of the present invention is described in detail below with reference to the accompanying drawings.

Example one

Referring to fig. 1, fig. 1 is a schematic flow chart of calculating a check code according to a first embodiment of the present invention. The method comprises the following specific steps:

in step 101, for the r +1 CRC generator polynomial, the device reads the data frame one by one starting from the frame of the data frame in units of w bits.

Wherein w is not less than r. The last time the significand of the frame was read is less than or equal to W bits. When data is read in the unit of w bits, the frame start mark and the frame end mark of the data frame are obtained at the same time.

And 102, aiming at the ith read data, the equipment obtains the input data and the first temporary CRC remainder calculated by the second-order CRC matrix transformation through alignment processing according to the initial CRC value.

The device performs CRC check code calculation on the data read each time, and here, the CRC check code calculation is performed on the data read i time.

If I is the number of times of reading the data frame, i.e. the number of times of reading the data frame, and is greater than 1, I is an integer from 1 to I.

When the apparatus determines that i is 1, the CRC initial value in step 102 is a preset initial value of r bits.

When i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read for the (i-1) th time; namely, the CRC check code calculated last time is used as the CRC initial value for calculating the CRC check code this time.

In the specific embodiment of the present invention, the device does not distinguish the data read for the second time when the input data calculated by the second-order CRC matrix transformation and the first temporary CRC remainder are obtained by the alignment processing, and determines the magnitudes of w, v, and r, that is, a dynamic alignment processing scheme, to determine the specific processing method.

Wherein, w is the bit number of reading the data frame each time; v is the number of effective bits in the w bits read each time; r is the degree of the CRC polynomial.

When the device determines that the number v of effective bits in the read data is equal to w, performing exclusive-or calculation on the CRC initial value and the high r bits in the w bits during alignment processing, taking the exclusive-or calculation result as the high r bits of the input data, and taking the low w-r bits in the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0;

when the device determines that r is not more than v and v is less than w, carrying out exclusive OR calculation on a CRC initial value and high r bits in v bits during alignment processing, taking the exclusive OR calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as low v-r bits of the input data; setting the r bits of the temporary CRC remainder as 0;

when the device determines that v is smaller than r, performing exclusive-or calculation on high-v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive-or calculation result as low-v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

In this implementation, only when the CRC initial value is determined, whether the data read next time is the data read for the first time is determined, and the data read for the second time is not distinguished when alignment is performed.

In specific implementation, the data read at the 1 st time and the data read at the I th time can be distinguished through the obtained frame start identifier and frame end identifier.

Step 103, the device transforms the calculated input data through a high-order CRC matrix to obtain a second temporary CRC remainder.

In a high-speed interface, parallel data generally participating in calculation of the CRC check code at the same time is wide, and the calculation rate is affected.

In the specific implementation of the invention, the device is configured with n r rows and m columns of parallel sub CRC transformation matrix coefficients, wherein n = w/n.

When the device carries out high-order CRC matrix transformation, input data obtained through alignment processing are equally divided into n parts, the n parts of input data are respectively subjected to modulo-2 product calculation with one matrix coefficient in n sub-CRC transformation matrix coefficients, n r-bit CRC remainders are obtained, the obtained n r-bit CRC remainders are subjected to exclusive OR calculation, and a second temporary CRC remainder of ith read data is obtained.

The concrete implementation is as follows: when CRC matrix transformation is calculated, n sub CRC transformation matrix coefficients (with the serial number of 0,1, …, n-1) of r rows and w/n columns which can be parallel are adopted, n is an integer larger than 1, and w is an integral multiple of n, n parts of data Y [ w-1:0] which are output in a dynamic alignment mode are evenly distributed, and are respectively multiplied by n sub CRC transformation matrix coefficients modulo 2, and r bit CRC remainders RWj [ r-1,0] obtained by each product are obtained, wherein j is 0-n-1. And performing exclusive OR calculation on the n CRC remainders to obtain a second temporary CRC remainder RW [ r-1:0 ].

Among them, RW_j[r-1,0]=LW_j⊙Y[(j+1)*m-1:j*m]^TAnd j is 0 to n-1.

LW_j=[F^(j*m+m-1)G^T,F^(j*m+m-2)G^T…F^(j*m)G^T]Is a constant of r rows/m columnsA matrix of numbers.

G^T=[g_r-1,g_r-2…g₁,g₀]^TAnd is a constant matrix of r rows/1 column, determined by a CRC generator polynomial.

Is a constant matrix of r rows/r columns, determined by the CRC generator polynomial.

Y[(j+1)*m-1:j*m]^TThe m-bit data after the average allocation is represented by a matrix of m rows/1 column.

⊙ denotes the modulo-2 multiplication of the matrix, the power of the F matrix is also the modulo-2 multiplication, F⁰Is an identity matrix.

Step 104, the apparatus performs an exclusive or calculation on the first temporary CRC remainder and the second temporary CRC remainder.

Step 105, when determining that I is equal to I, the device takes the exclusive or result as a CRC check code of the data frame; and when I is determined to be smaller than I, calculating the CRC initial value of the CRC check code by taking the exclusive OR result as the data read for the (I +1) th time.

In this embodiment, it can be seen that no matter the frame data is read for the second time, when the CRC check code of the read data is calculated, only the initial value of the CRC calculated for the second time is updated, and the method of the alignment process is not changed.

In some systems, in order to ensure system performance, particularly throughput performance under the condition of short frame length, when w-bit data read for the first time contains q-bit effective data of a next frame in addition to v-bit effective data of a current frame, the v-bit effective data of the current frame is used for calculating a CRC (cyclic redundancy check) code of the current frame; CRC check code calculation is performed using the q-bit valid data of the next frame as the data of the 1 st reading of the next frame.

When the q-bit effective data is used as a CRC check code of the next frame for calculation, the CRC initial value uses an r-bit preset initial value.

Example two

For the specific implementation that the input data and the first temporary CRC remainder calculated by the higher-order CRC matrix transformation are obtained by alignment processing according to the CRC initial value for the ith read data in step 102 in the first embodiment of the present invention, a different implementation manner is provided in the present invention, specifically as follows:

the data read from the 1 st to the I-1 st times are fixedly aligned, the data read from the I th time are determined by judging the sizes of w, v and r to determine a specific processing method, the processing method combining the fixed alignment and the dynamic alignment can meet the calculation requirement of the data frame with any actual length, and meanwhile, the CRC calculation performance can be greatly improved.

When the device carries out alignment processing on the data read from the 1 st time to the I-1 st time (in specific processing, the data without frame end marks) the CRC initial value and the high r bits in the w bits are subjected to exclusive OR calculation, the exclusive OR calculation result is used as the high r bits of the input data, and the low w-r bits in the w bit data are used as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0.

When the device determines that I is I, processing the data read by the data frame for the last time, and comparing the sizes of v, r and w during alignment processing; the specific treatment is as follows:

In specific implementation, the data can be read for the 1 st time through the obtained frame start identifier and frame end identifier, and the data read for the I-th time can be distinguished.

In this implementation, the device configures n r rows and m columns of parallel sub-CRC transform matrix coefficients, where n = w/n.

EXAMPLE III

For the specific implementation of step 102 and step 103 in the first embodiment, a different implementation manner is given in this embodiment, which is specifically as follows:

the CRC matrix transformation calculation adopts n sub CRC transformation matrix coefficients (numbered 0,1, …, n-1) of r rows and w/n columns which can be parallel, n is an integer larger than 1, and w is an integer multiple of n.

When the device performs CRC check code calculation on data read from the 1 st time to the I-1 st time, the alignment processing and high-order matrix transformation are merged and simplified into fixed CRC matrix transformation, and the specific implementation is as follows:

first, calculating a first temporary CRC remainder, wherein r bits of the first temporary CRC remainder are all set to be 0;

then, equally dividing the read data into n parts, numbering the data from 1 st part to nth part, and performing modulo-2 product calculation on the jth part of data and the jth sub CRC transformation matrix coefficient to obtain n-1 r-bit CRC remainders. J is an integer from 1 to n-1.

And performing modulo-2 product calculation on a matrix formed by the nth equal data and the calculated CRC initial value and a CRC transformation matrix coefficient formed by the nth sub CRC transformation matrix coefficient and the r cases on the left side of the CRC matrix coefficient to obtain an nth r-bit CRC remainder.

And finally, carrying out XOR calculation on the obtained n-1 r-bit CRC remainders and the obtained nth r-bit CRC remainder to obtain a second temporary CRC remainder of the ith read data.

When the device performs CRC check code calculation on the I-th read data, the specific processing procedures of step 102 and step 103 are the same as those in the first embodiment, and are not described in detail here.

Therefore, when all the currently read w bits are valid data, the CRC check code can be calculated in such a simple manner, and if the number of valid bits in the currently read w bit data is not w, the CRC check code cannot be calculated in such a manner, and the specific implementation manners given in the first embodiment and the second embodiment are used for processing.

Example four

The specific implementation manner is, for example, an ethernet CRC32 generation algorithm, that is, a CRC check code calculation method is exemplified for CRC generator polynomial of degree 32+ 1.

In step 1, the device generates a polynomial for CRC32, and reads the DATA frame to be calculated from the frame in 512 bits successively to obtain DATA [511:0], and the number of significant bits of the DATA frame read for the last time is less than or equal to 512 bits.

Where DATA [511] in the convention DATA [511:0] is the highest bit for calculating the CRC remainder; DATA [0] is the lowest bit for which the CRC remainder is calculated.

When reading 512-bit data from a data frame, obtaining a frame start indication mark SoP and a frame end indication mark EoP simultaneously, wherein the effective bit quantity in the 512-bit data is v, and v is an integral multiple of 8.

And step 2, aiming at the ith reading data and the 32-bit CRC initial value, the equipment obtains input data Y [511:0] and a first temporary CRC remainder RP [31:0] calculated by CRC matrix transformation through alignment processing.

When the data read this time is the data accompanied by the start instruction mark SoP, the CRC initial value R^init[31:0]For the configured 32-bit preset initial value, the 32-bit preset initial value may be configured as 32' {1}, i.e., 32 bits are all set to 1.

When the read data is not accompanied by the data of the start indication mark SoP, the CRC remainder R obtained by the last calculation is adopted^i-1[31:0]As an initial value R of the present cycle^init[31:0]。

Where I is an integer from 1 to I, I is the number of times the frame data is read in units of 512 bits, and is an integer greater than or equal to 1.

When v = w =512, R is set to^init[31:0]32 bits DATA [511:480] out of 512 bits]XOR calculated and used as input data Y [511: 480%]The lower 480 bits of the read data of this time are used as the 480 th bit of the input data, that is, Y [479:0]]=DATA[479:0]Setting 32 bits of the first temporary CRC remainder to 0, i.e. RP [31:0]]=32’b0。

When 32 is turned on<=v<At 512, R is added^init[31:0]And the effective number of the readingAccording to the 32 bits DATA [ v-1: v-32 ] among the v bits]Exclusive OR calculation is performed as v-1 to v-32 bits Y [ v-1: v-32 ] of input data]The low v-32 bits in the read data are used as the low 32 bits of the input data, namely Y [ v-32-1: 0]]=DATA[v-32-1:0]Setting the high 512-v bits of the input data to 0, namely Y511: v]= 0; the 32 bits of the first temporary CRC remainder are all set to 0, i.e., RP [31:0]]=32’b0。

When v is<At 32, R is^init[31:0]Middle and high v bits and v bits DATA [ v-1: 0]]Carrying out XOR calculation, and inputting the result of the XOR calculation into the v-th bit of the data; the high 512-v bits of the input data are all set to 0, i.e. Y511: v]= 0; r is to be^init[31:0]The middle and low 32-V bits are used as the high 32-V bits of the first temporary CRC remainder, and the low V bits of the first temporary CRC remainder are all set to 0, namely RP [31:0]]={R^init[31-v:0]，0}。

And step 3, performing CRC high-order matrix transformation calculation on the input data Y [511:0] to obtain a second temporary CRC remainder RW [31:0 ].

In order to better adapt to data transmission with a high-speed structure, for example, 8 parallel sub-CRC transformation matrix coefficients are configured, and when CRC high-order matrix transformation is performed, the configured 8 parallel sub-CRC transformation matrix coefficients (numbered 0,1, ….,7) are adopted.

The device will input the data Y511: 0]The average distribution is 8 shares, each share is 64 bits, the 8 shares are multiplied with the coefficient modulus 2 of the sub CRC transformation matrix, and each product obtains 32 bits CRC remainder RW_j[31,0]Wherein j is an integer of 0 to 7. Performing XOR calculation on 8 CRC remainders to obtain RW [31:0]]。

Wherein,

RW_j[31,0]=LW_j⊙Y[(j+1)*64-1:j*64]^Tand j is an integer of 0 to 7.

LW_j=[F^(j*64+64-1)G^T,F^(j*64+64-2)G^T，…，F^(j*64)G^T]And is a constant matrix of 32 rows/64 columns.

G^T=[g₃₁,g₃₀,…,g₁,g₀]^T=[0,0,0,0,0,1,0,0,1,1,0,0,0,0,0,1,0,0,0,1,1,1,0,1,1,0,1,1,0,1,1,1]^TIs a 32 row/1 column constant matrix whose polynomial is generated by CRC32

G（x）=x³²+x²⁶+x²³+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+ x +1 determination, abbreviated as [04C11DB7]^T。

Is a constant matrix of 32 rows/32 columns determined by the CRC32 generator polynomial.

⊙ denotes the modulo-2 multiplication of the matrix, the power of the F matrix is also the modulo-2 multiplication, F⁰= identity matrix.

Other similar calculations can be made, exemplified by j = 0:

RW₀[31,0]=LW₀⊙Y[63:0]^T

LW₀=[F⁽⁶³⁾G^T,F⁽⁶²⁾G^T,…,F⁽⁰⁾G^T]is a constant matrix of 32 rows/64 columns, and is calculated as follows, wherein LW is the top row_{0_row}[31](ii) a The bottom one action LW₀_row[0]。

LW₀_row[31]=5a72d812fb808b20

LW₀_row[30]=ad396c097dc04590

LW₀_row[29]=d69cb604bee022c8

LW₀_row[28]=eb4e5b025f701164

LW₀_row[27]=f5a72d812fb808b2

LW₀_row[26]=7ad396c097dc0459

LW₀_row[25]=671b1372b06e890c

LW₀_row[24]=b38d89b958374486

LW₀_row[23]=59c6c4dc ac1ba243

LW₀_row[22]=7691ba7c ad8d5a01

LW₀_row[21]=613a052c ad462620

LW₀_row[20]=309d029656a31310

LW₀_row[19]=184e814b2b518988

LW₀_row[18]=c2740a595a8c4c4

LW₀_row[17]=613a052cad46262

LW₀_row[16]=309d029656a3131

LW₀_row[15]=5bf63006493593b8

LW₀_row[14]=adfb1803249ac9dc

LW₀_row[13]=56fd8c01924d64ee

LW₀_row[12]=ab7ec600c926b277

LW₀_row[11]=fcdbb129f13d21b

LW₀_row[10]=dd94059b b409622d

LW₀_row[9]=34b8dadf21843a36

LW₀_row[8]=9a5c6d6f90c21d1b

LW₀_row[7]=175ceea533e185ad

LW₀_row[6]=51dcaf40627049f6

LW₀_row[5]=a8ee57a0313824fb

LW₀_row[4]=8e05f3c2e31c995d

LW₀_row[3]=1d7021f38a0ec78e

LW₀_row[2]=eb810f9c50763c7

LW₀_row[1]=dd2ed06e19033ac3

LW₀_row[0]=b4e5b025f7011641

Step 4, the first temporary CRC remainder RP [31:0]]And a second temporary CRC remainder RW [31:0]]Exclusive OR calculation to obtain R⁽ⁱ⁾[31:0]. If the frame has data to process, I is not I, let I = I +1, R⁽ⁱ⁾[31:0]And (5) as the initial value of CRC, repeating the steps 1-4, and performing the next cycle calculation.

If the frame has no data to be processed, I is I, the calculated R⁽ⁱ⁾[31:0]As the CRC check code for the data frame.

The device may also determine whether there is data to be processed by checking whether the read data processed this time has an end-of-frame flag.

As can be seen from the above processing, when v = w =512, the alignment processing may adopt a fixed alignment processing manner, which is specifically as follows:

when the device calculates the CRC code for the ith read data, the device firstly determines whether the read data is the last read data.

If the DATA is not the last read DATA, the Rinit [31:0] and the 32-bit DATA [511:480] in the 512 bits are subjected to exclusive OR calculation and used as the upper 32 bits of the input DATA Y [511:480], the lower 480 bits of the read DATA are used as the 480-th bits of the input DATA, namely Y [479:0] = DATA [479:0], and the 32 bits of the first temporary CRC remainder are all set to be 0, namely RP [31:0] = 32' b 0.

If it is the last read data, when it is determined that v = w =512, R is set to be^init[31:0]32 bits DATA [511:480] out of 512 bits]XOR calculated and used as input data Y [511: 480%]The lower 480 bits of the read data of this time are used as the 480 th bit of the input data, that is, Y [479:0]]=DATA[479:0]Setting 32 bits of the first temporary CRC remainder to 0, i.e. RP [31:0]]=32’b0。

When determining 32<=v<At 512, R is added^init[31:0]32 bits DATA [ v-1: v-32 ] of the valid DATA v bits read this time]Exclusive OR calculation is performed as v-1 to v-32 bits Y [ v-1: v-32 ] of input data]The low v-32 bits in the read data are used as the low 32 bits of the input data, namely Y [ v-32-1: 0]]=DATA[v-32-1:0]Setting the high 512-v bits of the input data to 0, namely Y511: v]= 0; the 32 bits of the first temporary CRC remainder are all set to 0, i.e., RP [31:0]]=32’b0。

When v is determined<At 32, R is^init[31:0]Middle and high v bits and v bits DATA [ v-1: 0]]Carrying out XOR calculation, and inputting the result of the XOR calculation into the v-th bit of the data; the high 512-v bits of the input data are all set to 0, i.e. Y511: v]= 0; r is to be^init[31:0]The middle and low 32-V bits are used as the high 32-V bits of the first temporary CRC remainder, and the low V bits of the first temporary CRC remainder are all set to 0, namely RP [31:0]]={R^init[31-v:0]，0}。

It can be seen from the above that a fixed calculation is performed on the data read from the 1 st to the I-1 st time, and the magnitude relationship among w, r and v is still compared during the calculation of the I time, so as to determine the calculation method.

When CRC check code calculation is carried out on the data read from the 1 st to the I-1 st times, when the fixed alignment algorithm is used for transformation, namely, dynamic alignment transformation is simplified into fixed high-order CRC matrix transformation, and meanwhile, when a second temporary CRC remainder is obtained by the change of the high-order CRC matrix, the fixed CRC matrix transformation operation can also be simplified into the fixed CRC matrix transformation operation. Specific examples are as follows:

because of Y [479:0]=DATA[479:0]，Y[511:480]=R^init[31:0]^DATA[511:480]Thus, the 8 sub-CRC transform matrix coefficients are as follows:

when j is taken from 0 to 6,

RW_j[31,0]=LW_j⊙DATA[(j+1)*64-1:j*64]^T。

when j takes 7, RW₇[31,0]={LW₇,LW₇The left 32 columns of ⊙ { DATA [ (7+1) × 64-1: j 64 }],R^init[31:0]}^T。

Wherein:

{LW₇,LW₇the left 32 columns of the matrix represent a 32 row/96 column (64 columns + 32 columns) matrix.

{DATA[(7+1)*64-1:7*64],R^init[31:0]}^TRepresenting a 96 row (64 rows + 32 rows)/1 column matrix.

Based on the same inventive concept, the application also provides a device. Referring to fig. 2, fig. 2 is a schematic structural diagram of an apparatus applied to the above technology in an embodiment of the present invention. The device includes: the device comprises a calculating unit, a sending unit, a receiving unit and a processing unit.

the receiving unit is used for receiving a data frame;

and the processing unit is used for judging whether the data frame received by the receiving unit has errors or not by using the CRC code calculated by the calculating unit according to the data frame received by the receiving unit.

The specific implementation of the computing unit is illustrated by example five and example six.

EXAMPLE five

Referring to fig. 3, fig. 3 is a schematic structural diagram of a computing unit in the fifth embodiment of the present invention. The calculation unit includes: an alignment unit, a higher order CRC calculation unit and an exclusive OR unit.

In the first step, an alignment unit reads the data frame sequentially from the frame of the data frame in units of w bits for the CRC generator polynomial of r +1 times.

When reading a data frame in units of w bits, a frame start flag SoP and a frame end flag EoP are read simultaneously, and the number v of significant bits of data read each time. The start of frame identifier SoP and the end of frame identifier EoP are used to identify whether the data is read for the first time or the last time, and naturally, whether the data is read between the first time and the last time can also be known.

And secondly, aiming at the data read for the ith time, the alignment unit obtains the input data and the first temporary CRC remainder calculated by the higher-order CRC matrix transformation through alignment processing according to the CRC initial value.

W is not less than r, I is the number of times of reading the data frame, I is an integer from 1 to I, and when I is 1, the CRC initial value is a preset r-bit initial value; when i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read at the (i-1) th time.

The alignment unit in this step is specifically configured to determine a size relationship between v, w, and r when the input data and the first temporary CRC remainder calculated by the second-order CRC matrix transformation are obtained through alignment processing according to the CRC initial value for the ith read data:

when v is determined to be equal to w, carrying out exclusive OR calculation on the CRC initial value and the high r bits in the w bits during alignment processing, taking the exclusive OR calculation result as the high r bits of the input data, and taking the low w-r bits in the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0;

when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting the r bits of the temporary CRC remainder as 0;

when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

And thirdly, the high-order CRC calculation unit obtains a second temporary CRC remainder after the input data calculated by the alignment unit is subjected to high-order CRC matrix transformation.

In this step, the high-order CRC calculation unit is further configured to configure n parallel sub-CRC transform matrix coefficients, where w/n is an integer not less than 1, and n is an integer not less than 2.

In a high-speed interface, parallel data generally participating in CRC remainder calculation at the same time is wider, and at the moment, in order to improve the speed, n sub-CRC matrix transformation coefficients capable of being parallel can be adopted during high-order CRC matrix transformation calculation.

Specifically, during high-order CRC matrix transformation, input data obtained through alignment processing is equally divided into n parts, modulo-2 product calculation is respectively carried out on the n parts of input data and one matrix coefficient in n sub-CRC transformation matrix coefficients, n r-bit CRC remainders are obtained, and XOR calculation is carried out on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of ith read data.

When CRC matrix transformation is calculated, n sub CRC transformation matrix coefficients (with the serial number of 0,1, …, n-1) of r rows and w/n columns which can be parallel are adopted, n is an integer larger than 1, and w is an integral multiple of n, n parts of data Y [ w-1:0] which are output in a dynamic alignment mode are evenly distributed, and are respectively multiplied by n sub CRC transformation matrix coefficients modulo 2, and r bit CRC remainders RWj [ r-1,0] obtained by each product are obtained, wherein j is 0-n-1. And performing exclusive OR calculation on the n CRC remainders to obtain a second temporary CRC remainder RW [ r-1:0 ].

Among them, RW_j[r-1,0]=LW_j⊙Y[(j+1)*m-1:j*m]^TAnd j is 0 to n-1.

LW_j=[F^(j*m+m-1)G^T,F^(j*m+m-2)G^T…F^(j*m)G^T]And is a constant matrix of r rows/m columns.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating an internal structure of a high-order CRC calculation unit according to an embodiment of the present invention. Fig. 4 shows n logic units for performing modulo-2 product calculation. And performing modulo-2 product calculation on the data of the data and the configured sub CRC matrix coefficient.

In this embodiment, the higher-order CRC calculation unit performs an exclusive-or calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder, and sends the second temporary CRC remainder to the exclusive-or unit.

In a specific implementation, the higher-order CRC calculation unit may also send the obtained n r-bit CRC remainders to the xor unit, and the xor unit performs xor calculation on the n r-bit CRC remainders to obtain a second temporary CRC remainder.

In this embodiment, an xor unit may be added between the high-order CRC calculation unit and the xor unit to complete the calculation of the second temporary CRC remainder.

How this is done, the user can configure it according to the specific application environment and resources.

Fourthly, the XOR unit carries out XOR calculation on the first temporary CRC remainder calculated by the alignment unit and a second temporary CRC remainder obtained by the high-order CRC calculation unit after high-order matrix transformation, and when I is equal to I, the XOR result is used as a CRC check code of the data frame; and when I is smaller than I, returning the exclusive OR result to the alignment unit as a CRC initial value for calculating a CRC check code for the data read at the (I +1) th time.

EXAMPLE six

Referring to fig. 5, fig. 5 is a schematic structural diagram of a computing unit in a sixth embodiment of the present invention. The calculation unit includes: the device comprises a first alignment unit, a first high-order CRC calculation unit, a first exclusive-OR unit, a second alignment unit, a second high-order CRC calculation unit and a second exclusive-OR unit.

First, the first alignment means reads the data frame sequentially from the frame of the data frame in units of w bits for the CRC generator polynomial of r +1 times.

And secondly, aiming at the ith read data, obtaining the input data and the first temporary CRC remainder calculated by the high-order CRC matrix transformation through alignment processing according to the initial value of the CRC.

W is not less than r, I is the number of times of reading the data frame, I is an integer from 1 to I-1, and when I is 1, the CRC initial value is a preset r-bit initial value; when i is not 1, the CRC initial value is a calculation result of calculating the CRC check code for the data read at the (i-1) th time.

And thirdly, the first high-order CRC calculation unit obtains a second temporary CRC remainder after the input data calculated by the first alignment unit is subjected to high-order CRC matrix transformation.

Fourthly, the first exclusive-OR unit performs exclusive-OR calculation on the first temporary CRC remainder calculated by the first alignment unit and the second temporary CRC remainder obtained by the first high-order CRC calculation unit, and when I is smaller than I-1, the exclusive-OR result is used as a CRC initial value of the CRC check code calculated for the data read for the (I +1) th time; performing a first step with i = i + 1; and when I is equal to I-1, sending an exclusive OR result to the second alignment unit as an initial CRC value calculated by the second alignment unit.

When I is smaller than I-1, I = I +1, the later result obtained by the calculation is used as the initial value of CRC, the first step is returned, the data of the frame of the (I +1) th time is read to calculate the CRC of the (I +1) th time, and the fifth step is executed until the calculation of the CRC of the data frame of the I-1 th time is finished.

And fifthly, reading the data left after the I-1 th reading of the first alignment unit by a second alignment unit, and obtaining the input data calculated by the second high-order CRC matrix transformation and the first temporary CRC remainder for the I-1 th reading data through alignment processing according to the effective bit quantity of the data read this time and the XOR result calculated by the first XOR unit aiming at the CRC code of the I-1 th reading data.

And sixthly, a second high-order CRC calculation unit obtains a second temporary CRC remainder aiming at the I-th read data after the input data calculated by the second alignment unit is subjected to high-order CRC matrix transformation.

And seventhly, the second exclusive-or unit performs exclusive-or calculation on the first temporary CRC remainder calculated by the second alignment unit and the second temporary CRC remainder obtained by the second high-order CRC calculation unit, and uses the exclusive-or calculation result as the CRC check code of the data frame.

In a specific implementation, the second alignment unit reads the data in the data frame each time, and calculates the CRC check code of the data frame by using the data output by the second exclusive or unit as the CRC initial value, except that the intermediate data is not the correct CRC check code of the data frame, and the CRC check code obtained by calculating only the data read I time is used as the CRC check code of the data frame.

If the time for one time use calculated by the first alignment unit, the first high-order CRC calculation unit and the first exclusive or unit is 1 cycle, and the time for one time use calculated by the second alignment unit, the second high-order CRC calculation unit and the second exclusive or unit is 3 cycles, when the last data of the data frame is read from the second alignment unit, the CRC check code obtained at an interval of 3 cycles is the check code of the data frame.

In the implementation apparatus, there are two implementation schemes for implementing the calculation of the check code by the first alignment unit, the first high-order CRC calculation unit, and the first exclusive or unit, specifically as follows:

firstly, the first alignment unit adopts a fixed alignment to realize the calculation of input data and the calculation of a first temporary CRC remainder; and the second alignment unit calculates these two parameters using a dynamic alignment approach.

A first alignment unit, configured to perform xor calculation on the CRC initial value and the high r bits among the w bits, use the xor calculation result as the high r bits of the input data, and use the low w-r bits of the w-bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0.

A second alignment unit, configured to perform, when it is determined that the number v of valid bits of the data read this time is equal to w, an exclusive or calculation between the CRC initial value and a higher r bit in the w bits during the alignment processing, use a result of the exclusive or calculation as a higher r bit of the input data, and use a lower w-r bit in the w-bit data as a lower w-r bit of the input data; the r bits of the first temporary CRC remainder are all set to 0; when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting r bits of a first temporary CRC remainder to be 0; when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

The first high-order CRC calculation unit is used for configuring n different parallel sub CRC transformation matrix coefficients, w/n is an integer not less than 1, and n is an integer not less than 2; when the high-order CRC matrix is transformed, equally dividing the input data obtained by the alignment processing of the first alignment processing unit into n parts, respectively carrying out modulo-2 product calculation with one matrix coefficient in n sub-CRC transformation matrix coefficients to obtain n r-bit CRC remainders, and carrying out XOR calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of the ith reading data;

the second high-order CRC calculation unit is used for configuring n different parallel sub CRC transformation matrix coefficients, w/n is an integer not less than 1, and n is an integer not less than 2; and when the high-order CRC matrix is transformed, equally dividing the input data obtained by the alignment processing of the second alignment processing unit into n parts, respectively carrying out modulo-2 product calculation on the n parts of the input data and one matrix coefficient in the n sub-CRC transformation matrix coefficients to obtain n r-bit CRC remainders, and carrying out XOR calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of the I-th read data.

In this case, the first alignment unit, the first high-order CRC calculation unit, and the first exclusive or unit constitute a whole-row cyclic calculation circuit, that is, the CRC check code calculation of the previous I-1 row read data is completed; and the second alignment unit, the second high-order CRC calculation unit and the second exclusive OR unit form a last row calculation circuit to finish the calculation of the CRC check code of the I-th row read data.

The user can know the number of cycles of the delay of the whole calculation unit, for example, the delay of the whole row of the cyclic calculation circuit is one cycle, the delay of the last row of the calculation circuit is 3 cycles, and the XOR result after the last read data is input into the apparatus for 3 clock cycles is the CRC remainder of the frame data.

Secondly, the first alignment unit and the second alignment unit use a dynamic alignment mode to realize the calculation of the input data and the calculation of the first temporary CRC remainder.

A first alignment unit, configured to perform, when it is determined that the number v of valid bits of the data read this time is equal to w, an exclusive or calculation between the CRC initial value and a higher r bit of the w bits during the alignment processing, use a result of the exclusive or calculation as a higher r bit of the input data, and use a lower w-r bit of the w-bit data as a lower w-r bit of the input data; the r bits of the first temporary CRC remainder are all set to 0; when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting r bits of a first temporary CRC remainder to be 0; when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

In this embodiment, the first high-order CRC calculation unit performs an exclusive-or calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder, and sends the second temporary CRC remainder to the exclusive-or unit.

In a specific implementation, the first high-order CRC calculation unit may also send the obtained n r-bit CRC remainders to the xor unit, and the xor unit performs xor calculation on the n r-bit CRC remainders to obtain a second temporary CRC remainder.

In this embodiment, an xor unit may be added between the first high-order CRC calculation unit and the xor unit to complete the calculation of the second temporary CRC remainder.

In this implementation, if the last read data includes data of the next frame, the processing may also be performed.

When the w-bit data read for the ith time contains q-bit effective data of a next frame in addition to v-bit effective data of the current frame, the second alignment unit processes the v-bit effective data of the current frame; and the first alignment unit takes the q-bit effective data of the next frame as the data read for the 1 st time of the next frame to calculate CRC check codes.

When the calculation is performed for the data read for the 1 st time of the next frame, the calculation of the CRC check code is performed using the r-bit preset initial value as the CRC initial value.

In this case, the user can know the number of cycles of the delay of the whole apparatus, for example, when CRC check code calculation is performed on data read each time, the circuit delays for one cycle, the last line calculation circuit also delays for 1 cycle, the whole apparatus delays for 1 cycle, the data read last time is input to the apparatus, and the xor result after 1 clock cycle is the CRC remainder of the data of the frame.

The units of the above embodiments may be integrated into one body, or may be separately deployed; may be combined into one unit or further divided into a plurality of sub-units.

The defect that a table look-up algorithm needs large cache is eliminated by adopting logic-based design to process multi-bit parallel data input one by one; the whole data frame does not need to be cached; meanwhile, the transformation matrix is simplified, and the transformation matrix coefficients can be directly solidified on an FPGA/ASIC logic circuit without adopting a table look-up mode of the transformation matrix coefficients.

The CRC initial value or the CRC remainder and the multi-bit parallel data adopt the same calculation logic circuit, and only one transformation matrix is needed for each block of data, so that the logic complexity is reduced, the logic resource is saved, and the delay is reduced.

The method processes the condition that only part of data bits in the last row of the multi-bit parallel data are effective with small resource cost and processing delay, and simultaneously can keep high working frequency.

Optionally, the situation that the same line of data contains both partial data at the end of the current data frame and partial data at the beginning of the next frame is processed, so that the frame rate of the short data frame is improved.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for generating a check code of a data frame, the method comprising:

when sending the data frame, calculating the Cyclic Redundancy Code (CRC) check code of the data frame, and sending the calculated CRC check code together with the data frame;

wherein, the calculating the CRC check code of the data frame includes:

performing XOR calculation on the first temporary CRC remainder and the second temporary CRC remainder, and when I is determined to be equal to I, taking an XOR result as a CRC check code of the data frame; when I is determined to be smaller than I, calculating a CRC initial value of a CRC check code by taking the XOR result as the data read for the (I +1) th time;

wherein,

the method for obtaining the input data and the first temporary CRC remainder of the ith read data through alignment processing according to the initial value of the CRC and the high-order CRC matrix transformation calculation comprises the following steps:

when the number v of effective bits of the data read at the time is determined to be equal to w, carrying out exclusive OR calculation on a CRC initial value and the high r bits in the w bits during alignment processing, taking the exclusive OR calculation result as the high r bits of the input data, and taking the low w-r bits in the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0;

when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0;

or,

if the I is not determined to be I, carrying out XOR calculation on the CRC initial value and the high r bit in the w bits during alignment processing, taking the XOR calculation result as the high r bit of the input data, and taking the low w-r bit in the w bit data as the low w-r bit of the input data; the r bits of the first temporary CRC remainder are all set to 0;

if the I is determined to be I, when the number v of the effective bits of the data read at the time is determined to be equal to w, carrying out XOR calculation on the CRC initial value and the high r bits in the w bits during alignment processing, taking the XOR calculation result as the high r bits of the input data, and taking the low w-r bits in the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0;

2. The method of claim 1, wherein when the w-bit data read I-th time contains valid v-bit data of a current frame and further contains valid q-bit data of a next frame, the valid v-bit data of the current frame is used to calculate a CRC check code of the current frame; CRC check code calculation is performed using the q-bit valid data of the next frame as the data of the 1 st reading of the next frame.

3. The method according to any one of claims 1-2, wherein the method further comprises: n different parallel r rows and w/n columns of sub CRC transformation matrix coefficients are configured, w/n is an integer not less than 1, and n is an integer not less than 2;

the obtaining a second temporary CRC remainder after the high-order CRC matrix transformation of the calculated input data comprises:

and during high-order CRC matrix transformation, equally dividing input data obtained through alignment processing into n parts, performing modulo-2 product calculation on the n parts of input data and one matrix coefficient in the n sub-CRC transformation matrix coefficients respectively to obtain n r-bit CRC remainders, and performing XOR calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of the ith read data.

4. An apparatus for generating a check code of a data frame, the apparatus comprising: the device comprises a calculation unit, a sending unit, a receiving unit and a processing unit;

the calculating unit is used for calculating the CRC code of the data frame when the sending unit sends the data frame; when the receiving unit receives a data frame, calculating a Cyclic Redundancy Code (CRC) check code of the data frame;

the receiving unit is used for receiving a data frame;

the XOR unit is used for carrying out XOR calculation on the first temporary CRC remainder calculated by the alignment unit and a second temporary CRC remainder obtained by the high-order CRC calculation unit after high-order matrix transformation, and when I is equal to I, the XOR result is used as a CRC check code of the data frame; when I is smaller than I, the XOR result is used as a CRC initial value for calculating a CRC check code aiming at the data read for the (I +1) th time and is returned to the alignment unit;

the alignment unit is specifically configured to, for the ith read data, obtain input data and a first temporary CRC remainder calculated by performing alignment processing on the ith read data according to a CRC initial value, perform xor calculation on the CRC initial value and high r bits among the w bits during alignment processing when it is determined that the number v of valid bits of the data read this time is equal to w, use the xor calculation result as the high r bits of the input data, and use low w-r bits among the w-bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0; when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting the r bits of the temporary CRC remainder as 0; when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

5. The apparatus of claim 4,

the high-order CRC calculation unit is further used for configuring n different parallel sub CRC transformation matrix coefficients, w/n is an integer not less than 1, and n is an integer not less than 2; and when the high-order CRC matrix is transformed, equally dividing the input data obtained by the alignment processing into n parts, respectively carrying out modulo-2 product calculation with one matrix coefficient in the n sub-CRC transformation matrix coefficients to obtain n r-bit CRC remainders, and sending the obtained n r-bit CRC remainders to the XOR unit.

6. An apparatus for generating a check code of a data frame, the apparatus comprising: the device comprises a calculation unit, a sending unit, a receiving unit and a processing unit;

the calculation unit is used for calculating the Cyclic Redundancy Code (CRC) check code of the data frame when the sending unit sends the data frame; when the receiving unit receives a data frame, calculating a CRC (cyclic redundancy check) code of the data frame;

the receiving unit is used for receiving a data frame;

the second exclusive-or unit is configured to perform exclusive-or calculation on the first temporary CRC remainder calculated by the second alignment unit and the second temporary CRC remainder obtained by the second high-order CRC calculation unit, and use the exclusive-or calculation result as a CRC check code of the data frame;

wherein,

the second alignment unit is specifically configured to, when it is determined that the number v of valid bits of the data read this time is equal to w, perform xor calculation on the CRC initial value and the high r bits among the w bits during alignment processing, use the xor calculation result as the high r bits of the input data, and use the low w-r bits among the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0; when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting r bits of a first temporary CRC remainder to be 0; when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0;

the first alignment unit is specifically configured to perform xor calculation on the CRC initial value and the high r bits in the w bits, use the xor calculation result as the high r bits of the input data, and use the low w-r bits in the w-bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0;

or,

the first alignment unit is specifically configured to, when it is determined that the number v of valid bits of the data read this time is equal to w, perform xor calculation on the CRC initial value and the high r bits among the w bits during alignment processing, use the xor calculation result as the high r bits of the input data, and use the low w-r bits among the w bit data as the low w-r bits of the input data; the r bits of the first temporary CRC remainder are all set to 0; when it is determined that r is not greater than v and v is less than w, performing exclusive-or calculation on the CRC initial value and the high r bits in the v bits during alignment processing, taking the exclusive-or calculation result as v to v-r bits of input data, setting the high w-v bits of the input data to be 0, and taking the low v-r bits in the v bit data as the low v-r bits of the input data; setting r bits of a first temporary CRC remainder to be 0; when v is smaller than r, carrying out exclusive OR calculation on high v bits in a CRC initial value and read v bit data during alignment processing, taking an exclusive OR calculation result as low v bits of input data, and setting high w-v bits of the input data to be 0; and taking the low r-v bits in the CRC initial value as the high r-v bits of the first temporary CRC remainder, and setting the low v bits of the first temporary CRC remainder as 0.

7. The apparatus of claim 6,

8. The apparatus according to any one of claims 6 to 7,

the first high-order CRC calculation unit is used for configuring n different parallel sub CRC transformation matrix coefficients, w/n is an integer not less than 1, and n is an integer not less than 2; when the high-order CRC matrix is transformed, equally dividing the input data obtained by the alignment processing of the first alignment unit into n parts, respectively carrying out modulo-2 product calculation with one matrix coefficient in n sub-CRC transformation matrix coefficients to obtain n r-bit CRC remainders, and carrying out XOR calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of the ith reading data;

the second high-order CRC calculation unit is used for configuring n different parallel sub CRC transformation matrix coefficients, w/n is an integer not less than 1, and n is an integer not less than 2; and when the high-order CRC matrix is transformed, equally dividing the input data obtained by the alignment processing of the second alignment unit into n parts, respectively carrying out modulo-2 product calculation on the n parts of the input data and one matrix coefficient in the n sub-CRC transformation matrix coefficients to obtain n r-bit CRC remainders, and carrying out XOR calculation on the obtained n r-bit CRC remainders to obtain a second temporary CRC remainder of the I-th read data.