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CN103779224A - Mosfet的制造方法 - Google Patents

Mosfet的制造方法 Download PDF

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CN103779224A
CN103779224A CN201210407448.6A CN201210407448A CN103779224A CN 103779224 A CN103779224 A CN 103779224A CN 201210407448 A CN201210407448 A CN 201210407448A CN 103779224 A CN103779224 A CN 103779224A
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semiconductor substrate
shallow trench
trench isolation
side wall
layer
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尹海洲
朱慧珑
秦长亮
殷华湘
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/436,892 priority patent/US9691878B2/en
Priority to PCT/CN2012/083750 priority patent/WO2014063381A1/zh
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Abstract

公开了一种MOSFET的制造方法，包括：在半导体衬底中形成用于限定MOSFET的有源区的浅沟槽隔离；以浅沟槽隔离作为硬掩模进行蚀刻，使得半导体衬底的表面暴露并且浅沟槽隔离的一部分从半导体衬底的表面突出以形成突出部分；在浅沟槽隔离的突出部分的侧壁上形成第一侧墙；去除第一侧墙的位于将要形成栅极的区域中的部分；在半导体衬底上形成栅叠层；形成围绕栅叠层的第二侧墙；以浅沟槽隔离、栅叠层、第一侧墙和第二侧墙为硬掩模在半导体衬底中形成开口；以开口的底面和侧壁为生长籽层，外延生长半导体层；以及对半导体层进行离子注入以形成源区和漏区。该方法利用由半导体层形成的源区和漏区对半导体衬底中的沟道区施加应力。

Description

MOSFET的制造方法
技术领域
本发明涉及半导体器件的制造方法，更具体地，涉及应力增强的MOSFET的制造方法。
背景技术
集成电路技术的一个重要发展方向是金属氧化物半导体场效应晶体管(MOSFET)的尺寸按比例缩小，以提高集成度和降低制造成本。然而，在MOSFET的尺寸减小时，半导体材料的性能(例如迁移率)以及MOSFET自身的器件性能(例如阈值电压)均可能变劣。
通过向MOSFET的沟道区施加合适的应力，可以提高载流子的迁移率，从而减小导通电阻并提高器件的开关速度。当形成的器件是n型MOSFET时，应当沿着沟道区的纵向方向对沟道区施加拉应力，并且沿着沟道区的横向方向对沟道区施加压应力，以提高作为载流子的电子的迁移率。相反，当晶体管是p型MOSFET时，应当沿着沟道区的纵向方向对沟道区压应力，并且沿着沟道区的横向方向对沟道区施加拉应力，以提高作为载流子的空穴的迁移率。
采用与半导体衬底的材料不同的半导体材料形成源区和漏区，可以产生期望的应力。对于n型MOSFET，在Si衬底上形成的Si:C源区和漏区可以作为应力源(stressor)，沿着沟道区的纵向方向对沟道区施加拉应力。对于p型MOSFET，在Si衬底上形成的SiGe源区和漏区可以作为应力源，沿着沟道区的纵向方向对沟道区施加压应力。
图1-4示出根据现有技术的方法制造应力增强的MSOFET的各个阶段的半导体结构的示意图，其中在图1a、2a、3a、4a中示出了半导体结构沿沟道区的纵向方向的截面图，在图3b、4b中示出了半导体结构沿沟道区的横向方向的截面图，在图1b、2b、3c、4c中示出了半导体结构的俯视图。在图中，线AA表示沿沟道区的纵向方向的截取位置，线BB表示沿沟道区的横向方向的截取位置。
该方法开始于图1a和1b所示的半导体结构，其中，在半导体衬底101中形成浅沟槽隔离102以限定MOSFET的有源区，在半导体衬底101上形成由侧墙105包围的栅叠层，栅叠层包括栅极电介质103和栅极导体104。
以浅沟槽隔离102、栅极导体104和侧墙105作为硬掩模，蚀刻半导体衬底101，达到期望的深度，从而在半导体衬底101对应于源区和漏区的位置形成开口，如图2a和2b所示。
在半导体衬底101的位于开口内的暴露表面上，外延生长半导体层106，以形成源区和漏区。半导体衬底101的位于栅极电介质103下方以及源区和漏区之间的一部分将作为沟道区。
半导体层106从半导体衬底101的表面开始生长，并且是选择性的。也即，半导体层106在半导体衬底101的不同晶面(crystalline surface)上的生长速率不同。在半导体衬底101由Si组成、以及半导体层106由SiGe组成的示例中，半导体层106在半导体衬底101的{1 1 1}晶面上生长最慢。结果，所形成的半导体层106不仅包括与半导体衬底101的表面平行的(100)主表面，而且在与浅沟槽隔离102和侧墙105相邻的位置还包括{1 1 1}刻面(facet)，这称为半导体层106生长的边缘效应(edgeeffect)，如图3a、3b和3c所示。
然而，半导体层106的小刻面是不期望的，因为这导致其自由表面的增加，使得半导体层106中的应力得以释放，从而减小对沟道区施加的应力。
进一步地，在半导体层106的表面进行硅化以形成金属硅化物层107，如图4a、4b和4c所示。该硅化消耗半导体层106的一部分半导体材料。由于半导体层106的小刻面的存在，硅化可以沿着小刻面进行，最终可能到达半导体衬底101。
然而，半导体衬底101中的硅化是不期望的，因为这可能在结区形成金属硅化物，导致结泄漏的增加。
因此，期望在应力增强的MOSFET抑制用于形成源区和漏区的半导体层的边缘效应。
发明内容
本发明的目的是提供一种提高沟道区应力和/或减小结泄漏的MOSFET的制造方法。
根据本发明，提供一种MOSFET的制造方法，包括：在半导体衬底中形成用于限定MOSFET的有源区的浅沟槽隔离；以浅沟槽隔离作为硬掩模进行蚀刻，使得半导体衬底的表面暴露并且浅沟槽隔离的一部分从半导体衬底的表面突出以形成突出部分；在浅沟槽隔离的突出部分的侧壁上形成第一侧墙；去除第一侧墙的位于将要形成栅极的区域中的部分；在半导体衬底上形成栅叠层；形成围绕栅叠层的第二侧墙；以浅沟槽隔离、栅叠层、第一侧墙和第二侧墙为硬掩模在半导体衬底中形成开口；以开口的底面和侧壁为生长籽层，外延生长半导体层；以及对半导体层进行离子注入以形成源区和漏区。
该方法利用由半导体层形成的源区和漏区对半导体衬底中的沟道区施加应力。由于在外延生长时以开口的底面和侧壁为生长籽层，因此半导体层可以完全填充半导体衬底中的开口。半导体层的{1 1 1}刻面仅仅位于其继续生长部分中，从而抑制了边缘效应的影响。
附图说明
图1-4示出根据现有技术的方法制造应力增强的MSOFET的各个阶段的半导体结构的示意图，其中在图1a、2a、3a、4a中示出了半导体结构沿沟道区的纵向方向的截面图，在图3b、4b中示出了半导体结构沿沟道区的横向方向的截面图，在图1b、2b、3c、4c中示出了半导体结构的俯视图。
图5-15示出根据本发明的方法的实施例制造应力增强的MSOFET的各个阶段的半导体结构的示意图，其中在图5-8、9a、10a、11a、12a、13a、14a、15a中示出了半导体结构沿沟道区的纵向方向的截面图，在图9b、10b、11b、12b、13b、14b、15b中示出了半导体结构的俯视图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在......上面”或“在......上面并与之邻接”的表述方式。
在本申请中，术语“半导体结构”指在制造半导体器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域；术语“沟道区的纵向方向”指从源区到漏区和方向，或相反的方向；术语“沟道区的横向方向”在与半导体衬底的主表面平行的平面内与沟道区的纵向方向垂直的方向。例如，对于在{1 0 0}硅晶片上形成的MOSFET，沟道区的纵向方向通常沿着硅晶片的<110>方向，沟道区的横向方向通常沿着硅晶片的<011>方向。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，MOSFET的各个部分可以由本领域的技术人员公知的材料构成。半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。栅极导体可以由能够导电的各种材料形成，例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅导体或者是其他导电材料，例如为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx|和所述各种导电材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3，氮化物例如包括Si3N4，硅酸盐例如包括HfSiOx，铝酸盐例如包括LaAlO3，钛酸盐例如包括SrTiO3，氧氮化物例如包括SiON。并且，栅极电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
按照本发明的实施例，执行图5至15中所示的以下步骤以制造应力增强的MSOFET，在图中示出了不同阶段的半导体结构的截面图。如果必要，在图中还示出了俯视图，在俯视图中采用线AA表示沿沟道区的纵向方向的截取位置。
该方法开始于图5所示的半导体结构，在半导体衬底201上依次形成衬垫氧化物层202和衬垫氮化物层203。半导体衬底201例如由Si组成。衬垫氧化物层202例如由氧化硅组成，厚度约为2-5nm。衬垫氮化物层203例如由氮化硅组成，厚度约为10-50nm。正如已知的那样，衬垫氧化物层202可以减轻半导体衬底201和衬垫氮化物层203之间的应力。衬底氮化物层205在随后的蚀刻步骤中用作硬掩模。
用于形成上述各层的工艺是已知的。例如，通过热氧化形成衬垫氧化物层202。例如，通过化学气相沉积形成衬垫氮化物层203。
然后，通过旋涂在衬垫氮化物层203上形成光致抗蚀剂层(未示出)，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层形成浅沟槽隔离的图案。利用光致抗蚀剂层作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，从上至下依次去除衬垫氮化物层203和衬垫氧化物层202的暴露部分。该蚀刻在半导体衬底201的表面停止，并且在衬垫氮化物层203和衬垫氧化物层202形成浅沟槽隔离的图案。通过在溶剂中溶解或灰化去除光致抗蚀剂层。
利用衬垫氮化物层203和衬垫氧化物层202一起作为硬掩模，通过已知的干法蚀刻或湿法蚀刻，蚀刻半导体衬底201达期望的深度，从而在半导体衬底201中形成浅沟槽，如图6所示。
然后，通过已知的沉积工艺，在半导体结构的表面上形成绝缘材料层(未示出)。该绝缘材料层填充浅沟槽。通过化学机械抛光(CMP)去除绝缘材料层位于浅沟槽外部的部分。绝缘材料层留在浅沟槽内的部分形成浅沟槽隔离204，如图7所示。浅沟槽隔离204限定MOSFET的有源区。浅沟槽隔离204的第一部分的侧壁是倾斜的。
进一步，利用浅沟槽隔离204作为硬掩模，通过已知的干法蚀刻或湿法蚀刻，去除衬垫氮化物层203和衬垫氧化物层202，从而暴露半导体衬底201的表面，如图8所示。由于蚀刻的选择性，浅沟槽隔离204基本未受蚀刻，从而其一部分从半导体衬底201的表面突出。浅沟槽隔离204的突出部分的长度大致等于衬垫氮化物层203和衬垫氧化物层202的厚度之和。如果需要，可以进一步相对于浅沟槽隔离204蚀刻半导体衬底201以增加浅沟槽隔离204的突出部分的长度。浅沟槽隔离204的突出部分包括暴露的表面和侧面。
然后，通过已知的沉积工艺，在半导体结构的表面上沉积例如10-50纳米的氮化物层，然后通过各向异性蚀刻在浅沟槽隔离204的突出部分的侧壁上形成侧墙205，如图9a、9b所示。与浅沟槽隔离204相类似，侧墙205包围半导体衬底201的有源区。
然后，通过旋涂在半导体结构上形成光致抗蚀剂层206，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层206形成图案，以遮挡将要形成源区和漏区的区域并暴露将要形成栅极的区域。利用光致抗蚀剂层206作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，在将要形成栅极的区域中，选择性地去除侧墙205，如图11a、11b所示。该步骤是优选的，其目的是暴露侧墙205下方的陡直的浅沟槽隔离204。在随后沉积多晶硅层的步骤中，在浅沟槽隔离204上形成的多晶硅层也将具有陡直的界面，从而有利于改善器件的性能。
然后，通过在溶剂中溶解或灰化去除光致抗蚀剂层206。通过已知的沉积工艺，在半导体结构的表面上依次形成电介质层以及多晶硅层，对其进行图案化，从而形成包括栅极电介质207和栅极导体208的栅极叠层。接着，通过上述已知的工艺，在半导体结构的整个表面上沉积例如10-50纳米的氮化物层，然后通过各向异性蚀刻形成包围栅叠层的侧墙209，如图12a、12b所示。
以浅沟槽隔离204、侧墙205、栅极导体208和侧墙209作为硬掩模，蚀刻半导体衬底201，达到期望的深度，从而在半导体衬底201对应于源区和漏区的位置形成开口，如图13a、13b所示。该蚀刻是各向异性的，通过选择合适的蚀刻剂和蚀刻条件，使得开口的形状与硬掩模的图案基本一致。也即，该开口的侧壁是陡直的。利用侧墙205可以保留与浅沟槽隔离204相邻的半导体衬底201的一部分。因此，开口的侧壁和底面基本上由半导体衬底201的材料组成。在栅极叠层附近，由于先前的蚀刻去除了侧墙205的一部分，并且侧墙205的剩余部分可能未与侧墙209交叠(参见图13b)，因此，开口的侧壁的小部分可能是浅沟槽隔离204的材料。
然后，在半导体衬底201的开口内，外延生长半导体层210。半导体层210从半导体衬底201的开口的底面和侧壁开始生长，并且是选择性的。也即，半导体层210在半导体衬底201的不同晶面上的生长速率不同。在半导体衬底201由Si组成、以及半导体层210由SiGe组成的示例中，半导体层210在半导体衬底201的{1 1 1}晶面上生长最慢。然而，与现有技术不同，半导体衬底201的开口的底面和侧壁的大部分均作为生长籽层，结果半导体层210可以完全填充半导体衬底201的开口。
在完全填充该开口之后，半导体层210失去开口侧壁的生长籽层，并继续自由外延生长。结果，半导体层210的继续生长部分不仅包括与半导体衬底201的表面平行的(100)主表面，而且在与侧墙205和侧墙209相邻的位置还包括{1 1 1}刻面，如图14a、14b所示。
半导体层210的{1 1 1}刻面仅仅位于其继续生长部分中。半导体层210的位于半导体衬底201的开口内的部分具有受约束的底面和侧壁。因此，半导体层210的刻面并未不利地影响对沟道区施加的应力。
尽管未示出，在图5-15所示的步骤之后，按照常规的工艺对半导体层210进行离子注入，然后例如在约1000-1080℃的温度下执行尖峰退火(spike anneal)，以激活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤，从而形成源区和漏区。半导体衬底的位于栅极电介质207下方以及源区和漏区之间的一部分作为沟道区。
优选地，在半导体层210的表面进行硅化以形成金属硅化物层211，以减小源区和漏区的接触电阻，如图15a、15b所示。
该硅化的工艺是已知的。例如，首先沉积厚度约为5-12nm的Ni层，然后在300-500℃的温度下热处理1-10秒钟，使得半导体层210的表面部分形成NiSi，最后利用湿法蚀刻去除未反应的Ni。
该硅化消耗半导体层210的一部分半导体材料。由于半导体层210的小刻面的存在，硅化可以沿着小刻面进行。由于半导体层210完全填充半导体衬底201的开口，硅化并未到达半导体衬底201。
在图15所示的步骤之后，在所得到的半导体结构上形成层间绝缘层、位于层间绝缘层中的通孔、位于层间绝缘层上表面的布线或电极，从而完成MOSFET的其他部分。
在替代的实施例中，取代图5-8所示的步骤，在半导体衬底201上形成浅沟槽隔离204，其中半导体衬底201的表面与浅沟槽隔离204的表面齐平。利用浅沟槽隔离204作为硬掩模，通过已知的干法蚀刻或湿法蚀刻，选择性地去除半导体衬底201的一部分。由于蚀刻的选择性，浅沟槽隔离204基本未受蚀刻，从而其一部分从半导体衬底201的表面突出。通过控制蚀刻时间，可以控制半导体衬底201中的蚀刻深度。该蚀刻深度对应于浅沟槽隔离204的突出部分的长度。浅沟槽隔离204的突出部分包括暴露的表面和侧面。
尽管在上述实施例中描述了应力增强的p型MOSFET及其中使用的应力源的材料，但本发明同样适应于应力增强的n型MOSFET。在n型MOSFET中，半导体层210例如由Si:C组成，用于形成源区和漏区，并且作为沿着沟道区的纵向方向对沟道区施加拉应力的应力源。除了应力源的材料不同之外，可以采用与上述方法类似的方法制造应力增强的n型MOSFET。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (12)

1.一种MOSFET的制造方法，包括：
在半导体衬底中形成用于限定MOSFET的有源区的浅沟槽隔离；
以浅沟槽隔离作为硬掩模进行蚀刻，使得半导体衬底的表面暴露并且浅沟槽隔离的一部分从半导体衬底的表面突出以形成突出部分；
在浅沟槽隔离的突出部分的侧壁上形成第一侧墙；
在半导体衬底上形成栅叠层；
形成围绕栅叠层的第二侧墙；
以浅沟槽隔离、栅叠层、第一侧墙和第二侧墙为硬掩模在半导体衬底中形成开口；
以开口的底面和侧壁为生长籽层，外延生长半导体层；以及
对半导体层进行离子注入以形成源区和漏区。
2.根据权利要求1所述的方法，其中形成浅沟槽隔离的步骤包括：
在半导体衬底上形成包括浅沟槽隔离的图案的第一硬掩模；
蚀刻半导体衬底以形成浅沟槽；以及
采用绝缘材料填充浅沟槽，以形成浅沟槽隔离。
3.根据权利要求2所述的方法，其中所述第一硬掩模包括位于半导体衬底上的衬垫氧化物层和位于衬垫氧化物层上的衬垫氮化物层。
4.根据权利要求2或3所述的方法，其中以浅沟槽隔离作为硬掩模进行蚀刻的步骤包括：
相对于浅沟槽隔离和半导体衬底，选择性地去除硬掩模。
5.根据权利要求1所述的方法，其中以浅沟槽隔离作为硬掩模进行蚀刻的步骤包括：
相对于浅沟槽隔离和半导体衬底，选择性地蚀刻半导体衬底达期望的深度。
6.根据权利要求1所述的方法，其中形成开口的步骤包括：
采用各向异性蚀刻在半导体衬底中形成开口，使得该开口具有陡直的侧壁。
7.根据权利要求1所述的方法，其中所述MOSFET为p型MOSFET。
8.根据权利要求7所述的方法，其中所述半导体衬底由Si组成，所述半导体层由SiGe组成。
9.根据权利要求1所述的方法，其中所述MOSFET为n型MOSFET。
10.根据权利要求9所述的方法，其中所述半导体衬底由Si组成，所述半导体层由Si:C组成。
11.根据权利要求1所述的方法，其中在形成第一侧墙和形成栅叠层之间，还包括：
去除第一侧墙的位于将要形成栅极的区域中的部分。
12.根据权利要求1所述的方法，其中在形成源区和漏区之后，还包括：
执行硅化以在源区和漏区的表面形成金属硅化物。
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