CN103777905B - Software-defined fusion storage method for solid-state disc - Google Patents

Abstract

The invention discloses a software-defined fusion storage method for a solid-state disc. An HFSL (host fusion storage layer) is added on a host, physical block characteristics of the solid-state disc and statistical information during usage are obtained directly, complex IO (input/output) scheduling and management of the solid-state disc are conducted in combination with upper-layer data access characteristics, and an address mapping method with variable allocation granularities is used for realizing persistent high performance of the solid-state disc. According to the method, performance optimization of an NAND flash and storage management fusing a PCM (phase change memory) and the NAND flash are realized on the host, and the outstanding performance of the PCM is used for making up performance defects of the NAND flash, so that the read/write performance of the solid-state disc is improved, and the service life of the solid-state disc is prolonged.

Description

A software-defined solid-state disk fusion storage method

technical field

The invention belongs to the field of computer data storage, and in particular relates to a software-defined solid-state disk fusion storage method.

Background technique

In recent years, the rapid development of NAND FLASH-based solid-state disks has gradually replaced traditional mechanical hard disks. The manufacturing process of NAND FLASH chips has been continuously improved, from the 25nm process in 2008 to the current 10nm process, the performance has been continuously improved. However, NAND FLASH has limited wear times, poor lower-write performance, and does not support in-place modification, which still limits its performance.

The existing NAND FLASH-based solid-state disk basically uses the firmware program in the solid-state disk to shield the shortcomings of NAND FLASH, and provides a disk-like block device interface for the host to use. The host side completely regards the SSD as a black box and uses it directly regardless of its physical characteristics. While this is the easiest and fastest way to replace a traditional mechanical hard drive, it has serious drawbacks. For example, the IO scheduling algorithm designed for mechanical disks on the host side will not be applicable to solid-state disks, and the file system designed for mechanical disks will not be applicable to solid-state disks; since the read and write operation unit of NAND FLASH is Page (minimum 2KB) unit , the traditional request in the unit of disk sector size (512B) is sent to the solid-state disk, resulting in the need for additional merging and distribution of processing requests in the solid-state disk, which reduces the storage speed; the host cannot obtain the physical characteristics of the solid-state disk, Wear status and usage information, performance optimization cannot be performed on file management and address space allocation. In addition, because the controller of the solid-state disk needs to shield the shortcomings and optimize the performance of NAND FLASH, it takes up a lot of limited resources of the embedded system, which is very uneconomical, and because the characteristics of the host-side data do not know the performance Ascension is limited. Therefore, it is necessary to reconsider the storage structure design of NAND FLASH-based SSDs, and expose more physical characteristics and usage information to the host, so that the host can no longer completely regard the SSD as a black box, but as a gray box.

Fusion-io company proposed a VSL (Visual Storage Layer) layer, which also regards the solid-state disk as a gray box, and puts the FTL (Flash Translation Layer) under the host-side driver to achieve great performance. improve. However, VSL is a combination of driver and FTL. In fact, the IO request arriving at the driver layer does not have so many data attributes. The driver cannot effectively optimize the physical characteristics of the SSD, and the file system layer is still Statistical information such as the physical characteristics and wear status of solid-state disks cannot be obtained, which limits the performance improvement of solid-state disks.

In addition to the above-mentioned high-performance NAND FLASH memory chips, the development of new non-volatile memory chips is also very fast, especially PCM (Phase Change Memory, phase change memory). Now Micron has produced PCM memory chips with a size of 1GB . Compared with NAND FLASH, PCM has many advantages. The most prominent is that PCM supports read and write operations in units of bytes. The read and write speed is faster than that of NAND FLASH. At the same time, PCM does not need to be erased before writing, and has more possibilities. Wear times. At present, PCM is still in the research stage, and the research on PCM basically uses simulation methods to use PCM as a substitute for memory or to use it in combination with memory. Especially in solid-state disks, many studies use PCM as a cache of NAND FLASH, but this cannot give full play to the performance advantages of PCM to make up for the performance shortcomings of NAND FLASH.

Contents of the invention

In view of this, the purpose of the present invention is to realize the performance optimization of NAND FLASH and the storage management of PCM and NAND FLASH fusion at the host end, to improve the overall performance of the solid state disk; at the same time, use the excellent performance of PCM to make up for the performance shortcomings of NAND FLASH, improve the performance of solid state Disk read and write performance and service life.

The present invention proposes a software-defined solid-state disk fusion storage method, wherein phase-change memory (PCM) is fused in a NAND FLASH-based solid-state disk, and the method includes the following steps:

(1) Read the PCM address mapping table and FLASH address mapping table from the PCM fixed area of the solid-state disk to the host memory when starting up, and open up a cache area of the solid-state disk in the host memory at the same time. When the host has a request to access the solid-state disk Q( lsn, size, op, data), first obtain Q.lsn and Q.size, and judge whether the data requested by Q is in the buffer according to Q.lsn and Q.size, where lsn is the logical address and size is the request Size, op is the read and write flag, data is the address of the data in the host memory, that is, the destination address or source address of the data on the host side,

If it hits, for the read request, copy the data from the cache to the data address, and for the write request, copy the data at the data address to the cache, and go to step (8); if not, for the read request, go to step (2) For a write request, if the cache area is not full, directly copy the data at the data address to the cache area, and then go to step (8); otherwise, replace and update the cache area, and go to step (3);

(2) Obtain the Q.lsn and Q.size of the read request, search the PCM and FLASH address mapping table for address translation, and turn to step (6), wherein, for the read request to access the PCM, generate the optimal write granularity size of the PCM (such as 512B) as a unit of read operation request sequence; for a read request to access FLASH, a read operation request sequence with the size of a FLASH physical page is generated;

(3) Let the request replaced from the buffer be q, and determine the size of q.size. If q.size<NANDPAGE SIZE, go to step (4), otherwise go to step (5);

(4) According to the access times and access time of the requested q.lsn, judge whether the access data of q.lsn is hot or cold: if it is hot data, allocate a physical address with less PCM wear times to q.lsn; otherwise assign q.lsn Allocate physical addresses with more PCM wear times; generate a write request sequence with the optimal PCM write granularity size (such as 512B) as the unit, and turn to step (6);

(5) According to the access times and access time of the requested q.lsn, judge whether the data accessed by q.lsn is hot or cold: if it is hot data, allocate a physical address with less FLASH wear times to q.lsn; otherwise assign q.lsn Allocate physical addresses with more FLASH wear times; generate a write request sequence in units of FLASH page size, and turn to step (6);

(6) Obtain the request sequence generated in (2), (4), and (5), and add the request sequence to the end of the circular request queue on the corresponding channel of the solid state disk according to the physical address in the request. When the timer arrives , send the request on the current channel to the SSD for processing;

(7) Detect whether there is a completion interrupt, if an interruption is detected, it means that the request has been processed, and go to step (8);

(8) Return completion to request Q.

The present invention also proposes a host fusion storage layer (HFSL) system, which is used to manage the request of the file system to access the solid-state disk. The solid-state disk is based on NAND FLASH and incorporates phase-change memory (PCM). The system includes:

The address mapping management module maintains the PCM address mapping table and the NAND FLASH address mapping table in the host memory, and assigns the addresses of the PCM and NAND FLASH to the write request in the request by adopting an address mapping method with variable allocation granularity;

The IO scheduling management module is used to distribute the request to each physical channel of the solid state disk, and the physical channel includes a plurality of channels of PCM and NAND FLASH, wherein a circular request queue is maintained for each physical channel of the solid state disk;

The cache area management module manages the cache area of the solid-state disk opened in the host memory. When the request of the file system to access the solid-state disk arrives, it judges whether the requested data is hit. If it is hit, the data in the cache area is returned to the file. Otherwise, the request is handed over to the address mapping management module for processing. The address mapping management module performs address translation on the request to obtain the actual physical address, and then the IO scheduling management module hangs the request to the end of the circular request queue of the corresponding channel.

Compared with the prior art, the present invention has the following beneficial effects:

(1) The solid-state disk is no longer transparent to the host, and the host can obtain the physical characteristics and data distribution information of the solid-state disk, and optimize its performance;

(2) Using the integrated storage method of PCM and NAND FLASH, PCM is used as the same-level memory of NAND FLASH, storing lowercase data in PCM, metadata information such as address mapping table, or hot data that needs to be accessed quickly and frequently, etc., to improve It not only improves the low-write performance of the solid-state disk, but also improves the startup speed of the solid-state disk. At the same time, PCM acts as the upper-level cache of NANDFLASH in the solid-state disk to improve the performance of the solid-state disk. Compared with traditional solid-state disks that use DRAM as a cache, the fusion storage of PCM and NANDFLASH can also ensure data consistency and improve the reliability of solid-state disks;

(3) Between the host driver and the file system, a layer of fusion storage middle layer——HFSL is implemented. HFSL can obtain the physical characteristics and data distribution information of PCM and NAND FLASH, and aim at the physical characteristics of PCM and NAND FLASH fusion storage. , In HFSL, address mapping, IO scheduling strategy, garbage collection, wear leveling and other efficient storage management are realized, which improves the overall performance of the solid state disk;

(4) In the solid-state disk integrated storage of PCM and NAND FLASH, only simple operations such as reading, writing, and erasing need to be completed without implementing complex IO scheduling and other management strategy algorithms in the firmware, which can simplify the solid-state disk itself The control management facilitates the rapid innovation of the solid-state disk hardware architecture, enabling it to concentrate resources and focus on controlling the basic operations of parallel processing PCM and NANDFLASH, improving the read and write speed of the solid-state disk.

Description of drawings

Fig. 1 is a schematic diagram of the system structure of an embodiment of the present invention;

Fig. 2 is a schematic flow chart of the method of the embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Generally speaking, the present invention is mainly based on two points: one is to implement the fusion storage layer——HFSL (HostFusion Storage Layer) on the host side, realize flexible IO scheduling and management strategies and performance optimization for solid state disks, and simplify the structure of solid state disks; The second is to integrate PCM storage in NAND FLASH-based solid-state disks. Among them, PCM can be used as the same-level memory of NAND FLASH to store metadata information of solid-state disks, and can also be used to store lowercase data or frequently accessed hot data. At the same time, PCM can also be used as the upper-level cache of NAND FLASH to improve the performance of solid-state disks.

Further, the present invention is based on the following principles: the HFSL intermediate layer is implemented between the host driver and the file system, and the request of the host to access the solid-state disk needs to be processed by HFSL, converted into simple operations such as reading, writing, and erasing, and sent to the solid-state disk ; Inside the SSD, only simple requests such as read, write, and erase are processed, and complex scheduling and management algorithms such as excessive address conversion, garbage collection, wear leveling, and redistribution and combination of IO requests are not required. According to the physical characteristics of PCM and NANDFLASH fusion storage, the address mapping and IO scheduling algorithm of fusion management are designed in HFSL. In addition, HFSL also has complex IO scheduling functions such as basic cache management, garbage collection, and wear leveling in traditional SSDs.

FIG. 1 is a schematic diagram of the system structure of an embodiment of the present invention. Among them, the host converged storage layer (HFSL) includes three modules: an address mapping management module, an IO scheduling management module and a cache area management module.

The function of the address mapping management module is mainly to reasonably allocate the addresses of PCM and NAND FLASH to write requests. Among them, since the read request already has the physical address of the solid-state disk, it does not need to be allocated, while the write request only knows the logical address of the solid-state disk, and the specific physical address needs to be allocated by the address mapping module. The PCM address mapping table and the NAND FLASH address mapping table are stored in a fixed area in the PCM of the solid state disk, and the address mapping management module maintains the above address mapping table in the host memory. Read the address mapping table from the PCM fixed area to the host memory when starting up, and write the modified address mapping entry in the address mapping table in the memory back to the PCM fixed area of the solid state disk when shutting down. Except a part of the address physical space is used to store the above-mentioned address mapping table and the accessed metadata information (they are transparent to the host in the host-side converged storage layer), the remaining physical addresses of PCM and NAND FLASH address are uniformly addressed. In a specific embodiment, address allocation is carried out by adopting an address mapping method with a variable distribution granularity: the NAND FLASH address section adopts coarse-grained address mapping, and the physical page size of NAND FLASH is used as the address mapping unit; the PCM address section adopts PCM optimal Fine-grained address mapping with write granularity as the unit, that is, the address mapping unit is smaller than the page (such as 512B).

There are three main factors to consider when performing address mapping:

(1) When receiving a request from the file system to access the SSD, determine whether the size of the requested data is smaller than the threshold. If it is smaller than the threshold, the request is a lowercase request; otherwise, the request is an uppercase request. For a lowercase request, allocate PCM physical Address, assign the physical address of NAND FLASH to the uppercase request;

(2) Count the wear times of PCM and NADN FLASH. When assigning addresses, judge whether the data is hot or cold. If it is cold data, it will be allocated to the physical block address with more wear times, otherwise it will be allocated to the physical block address with less wear times. physical block address;

(3) When address allocation is performed, it is allocated in stripes, and continuous logical addresses are allocated to different physical channels of the solid state disk.

In addition, wear leveling and garbage collection operations can also be integrated into the address mapping management module.

The main function of the IO scheduling management module is to distribute requests to each physical channel of the solid state disk. Physical channels include multiple PCM channels and multiple NAND FLASH channels. The IO scheduling management module maintains a circular request queue for each physical channel of the solid state disk. After the request is mapped, the request for PCM is a request sequence in the unit of PCM optimal write granularity size (such as 512B), and the request for NAND FLASH is a request sequence in the unit of the physical page size of NAND FLASH. For the IO scheduling management module, the channel number is calculated according to the physical address, and the request is added to the tail of the corresponding PCM and NAND FLASH channel circular queue. A timer is set in the IO scheduling management module, and when the timer arrives, the request on the circular request queue is sent to the solid state disk. When it is detected that the solid state disk has a completion interrupt, it will query the completion status of the request on the cyclic request queue, and if it is completed, the request will be deleted from the cyclic request queue.

The cache area management module is used to manage the solid state disk cache area opened in the host memory. Because the reading speed of PCM and NAND FLASH is relatively fast, in a specific embodiment, a write-only cache area can be designed, that is, only those data that are often written are cached. When the request of the file system to access the solid-state disk comes, it can check the balanced binary tree or other methods according to the logical address to determine whether the requested data hits, and if it hits, the data in the cache is returned to the file system. If no data is found in the cache, the request is handed over to the address mapping module for processing. The address mapping module converts the address of the request to obtain the actual physical address, and then the IO scheduling management module hangs the request to the end of the circular queue of the corresponding channel. Wherein, a balanced binary tree may be used to manage cached data. In addition, in a specific embodiment, unlike the internal cache area of traditional solid state disks, the HFSL buffer is managed with a granular size of 512B instead of the traditional physical page size of NAND FLASH. At the same time, because the host has abundant memory resources, the capacity of the cache area can be set as large as possible to be able to cache more write data.

Fig. 2 is a flow chart of the method of the embodiment of the present invention. When starting up, the host fusion storage layer (HFSL) reads the PCM address mapping table and the FLASH address mapping table from the PCM fixed area of the solid state disk into the host memory, and at the same time opens up a cache area of the solid state disk in the host memory.

Assume that the host requests Q(lsn, size, op, data) to access the solid state disk, lsn is the logical address, size is the request size, op is the read and write flag, for example, 0 means write, 1 means read, data means data in the host The address in the memory is the data destination or source address of the host. For request Q, the specific processing process is as follows:

(1) When receiving a request Q from the host to access the solid state disk, first obtain Q.lsn and Q.size, and judge whether the data accessed by request Q is in the cache according to Q.lsn and Q.size. If it hits, for a read request, copy the data from the cache to the data address, and for a write request, copy the data at the data address to the cache, and go to step (8). If there is no hit, for a read request, go to step (2). For a write request, if the cache is not full, directly copy the data at the data address to the cache, and go to step (8), otherwise, replace and update the cache Operation, go to step (3). Wherein, it may be judged whether the requested data is hit by using a search for a balanced binary tree or other methods.

(2) Obtain the Q.lsn and Q.size of the read request, and search the PCM and FLASH address mapping table for address conversion. For a read request to access PCM, generate a read operation request sequence in the unit of PCM optimal write granularity size (such as 512B); for a read request to access FLASH, generate a read operation request sequence in FLASH physical page size, and go to step (6) .

(3) Let the request replaced from the buffer be q, judge the size of q.size, if q.size<NANDPAGE SIZE, go to step (4), otherwise go to step (5).

(4) According to the access frequency and access time recency of the request q.lsn, judge the hotness of the q.lsn access data. If it is hot data, allocate a physical address with less PCM wear times to q.lsn; otherwise, assign a physical address with more PCM wear times to q.lsn. Generate a write request sequence in units of PCM optimal write granularity size (such as 512B), and turn to step (6). Among them, if the PCM does not have enough physical space, copy the data in the PCM to the NANDFLASH, and modify the corresponding address mapping entry.

(5) According to the access frequency and access time recency of the request q.lsn, judge the hotness of the q.lsn access data. If it is hot data, allocate a physical address with less FLASH wear times to q.lsn; otherwise, allocate a physical address with more FLASH wear times to q.lsn. Generate a write request sequence in units of FLASH page size, and turn to step (6).

(6) Obtain the request sequences generated in (2), (4), and (5), and add them to the end of the circular request queue on the corresponding channel of the solid state disk according to the physical address in the request. When the timer arrives, the request on the current channel is sent to the solid state disk for processing.

(7) Check whether there is a completion interrupt, if an interrupt is detected, it means that the request has been processed, and then go to step (8).

(8) Return completion to request Q.

Finally, write the data in the cache area and the modified address mapping entries in the PCM address mapping table and the FLASH address mapping table in the memory back to the corresponding area of the solid state disk when shutting down.

It can be seen that in the method proposed by the present invention, PCM and NAND FLASH are fused for storage, and PCM can not only be used for storage at the same level as NAND FLASH, but also store lowercase data for accessing solid-state disks and metadata information of solid-state disks, or frequently accessed hot data etc. It can also be used as the upper-level cache of NAND FLASH in the solid-state disk, thereby improving the overall performance of the solid-state disk. At the same time, the fusion of storage layer HFSL on the host side aims at the physical characteristics of PCM and NAND FLASH, and optimizes data layout and performance in combination with data request characteristics, simplifies the control and management of SSD itself, facilitates rapid innovation of SSD hardware architecture, and realizes PCM and NAND Flexible, efficient and reliable storage integrated with FLASH.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (10)

1. a kind of solid-state disk of software definition merges storage method, wherein, merge phase in the solid-state disk based on NAND FLASH Transition storage (PCM), and one layer of fusion storage intermediate layer (HFSL), its energy are realized between host side driving and file system The physical characteristic and Data distribution information of PCM and NAND FLASH are obtained, and merges storage for PCM and NAND FLASH Physical characteristic, in fusion storage intermediate layer address of cache, I O scheduling strategy, garbage reclamation, abrasion equilibrium, methods described are realized Comprise the following steps：

(1) PCM address mapping table and FLASH address mapping table are read to host memory from solid-state disk PCM FX when starting shooting In, while open up the buffer area of one section of solid-state disk in host memory, when main frame have access solid-state disk request Q (lsn, size, Op, data) when, Q.lsn and Q.size is obtained first, judged to ask the data of Q access whether to exist according to Q.lsn and Q.size In buffer area, wherein, lsn is logical address, and size is request size, and op is read-write mark, and data is data in host memory In address, i.e. the data destination address or source address of host side,

If hit, for read request, data data addresses is copied to, for write request, data addresses from buffer area Data copy proceeds to step (8) in buffer area；If in recklessly, for read request, proceeding to step (2), for write request, If buffer area is not full, directly step (8) in the data copy at data addresses to buffer area, is proceeded to, otherwise delayed Deposit area and replace and update operation, proceed to step (3)；

(2) Q.lsn and Q.size of read request are obtained, search PCM carries out address conversion with FLASH address mapping table, proceeds to step Suddenly (6), wherein, for access PCM read request, produce by PCM optimums write granule size in units of read operation request sequence； For the read request for accessing FLASH, produce with the read operation request sequence of FLASH physical page sizes；

(3) request for replacing out from buffer area is set as q, the size of q.size is judged, if q.size<NAND PAGE SIZE, proceeds to step (4), otherwise proceeds to step (5)；

(4) according to the access times and access time of request q.lsn, judge that q.lsn accesses the cold and hot property of data：If hot number According to giving the q.lsn distribution PCM abrasion less physical address of number of times；Otherwise distribute PCM abrasion number of times more physics to q.lsn Address；Produce by PCM optimums write granule size in units of write request sequence, and proceed to step (6)；

(5) according to the access times and access time of request q.lsn, judge that q.lsn accesses the cold and hot property of data：If hot number According to giving the q.lsn distribution FLASH abrasion less physical address of number of times；It is otherwise more to q.lsn distribution FLASH abrasion number of times Physical address；Produce with the write request sequence of FLASH page of size unit, and proceed to step (6)；

(6) request sequence produced in (2), (4), (5) is obtained, the physical address in request distinguishes the request sequence The cycle request rear of queue being added in solid-state disk respective channel, when timer arrives, sends the request on current channel Give solid-state disk process；

(7) detected whether to complete to interrupt, if detecting interruption, represented that request has been processed and complete, proceeded to step (8)；

(8) return and complete to give request Q.

2. method according to claim 1, in step (4), if PCM does not have enough physical spaces, in PCM Data duplication changes corresponding address of cache entry in NAND FLASH.

3. method according to claim 1 and 2, also includes after step (8)：During shutdown the data in buffer area with And the address of cache entry that have modified in PCM address mapping table and FLASH address mapping table in internal memory writes back to the phase of solid-state disk In answering region.

4. a kind of main frame merges accumulation layer (HFSL) system, for being managed to the request of file system access solid-state disk, institute Solid-state disk is stated based on NAND FLASH and has merged phase transition storage (PCM), and driven in host side real and file system between Show one layer of fusion storage intermediate layer (HFSL), it can obtain the physical characteristic and Data distribution information of PCM and NAND FLASH, And merge the physical characteristic of storage for PCM and NAND FLASH, realize that address of cache, IO are adjusted in fusion storage intermediate layer Degree strategy, garbage reclamation, abrasion equilibrium, the system includes：

Address of cache management module, maintains PCM address mapping table and NAND FLASH address mapping table in host memory, adopts The variable address mapping method of partition size distributes to the address of PCM and NAND FLASH the write request in the request；

I O scheduling management module, for described each physical channel for asking to be distributed to solid-state disk, the physical channel to include Multiple passages of PCM and NAND FLASH, wherein, it is that each physical channel of solid-state disk maintains a cycle request queue；

Buffer queue management module, the buffer area of the solid-state disk to opening up in host memory is managed, when file system access is consolidated When the request of state disk arrives, whether the data for judging the request hit, and the data in buffer area are returned to text if hit Part system；Otherwise, just give address of cache management module request to process, address of cache management module is to asking into row address to turn Change and obtain actual physical address, then I O scheduling management module is suspended to request the cycle request queue tail of respective channel.

5. system according to claim 4, wherein, the address of cache management module is solid from solid-state disk PCM in start Determine region and read PCM address mapping table and NAND FLASH address mapping table in host memory, address in internal memory during shutdown The address of cache entry that have modified in mapping table is write back in the respective regions of solid-state disk PCM.

6. system according to claim 4, wherein, when the request of file system access solid-state disk is received, describedly Whether location mapping management module judges to ask the size for accessing data less than threshold value, and if less than threshold value, then the request please for small letter Ask, the otherwise request is big write request, for the physical address that little write request distributes PCM, for big write request distributes NAND The physical address of FLASH.

7. system according to claim 4, wherein, the address of cache management module statistics PCM and NADN FLASH's Abrasion number of times, when row address distribution is entered, judges the cold and hot property of data, if cold data is just assigned to abrasion, number of times is more Physical block address, is otherwise just assigned to the less physical block address of abrasion number of times.

8. system according to claim 4, wherein, when the address of cache management module is entered row address and distributed, with band Mode distribute, continuous logical address is assigned on the different physical channels of solid-state disk.

9. system according to claim 4, wherein, for I O scheduling management module, passage is calculated according to physical address Number, and request is added to corresponding PCM and NAND FLASH channel cycle queue tails.

10. system according to claim 4, wherein, timer is set in the I O scheduling management module, when timer is arrived The request in cycle request queue is sent to solid-state disk when coming；When detect solid-state disk complete interrupt when, inquiry circulation please The completion status asked in queue is sought, if it is complete, just deleting the request from cycle request queue.