CN103647553A - Direct current frequency modulation reference source circuit of broadband ultra low phase noise - Google Patents
Direct current frequency modulation reference source circuit of broadband ultra low phase noise Download PDFInfo
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Abstract
The invention provides a direct current frequency modulation reference source circuit of broadband ultra low phase noise. The direct current frequency modulation reference source circuit comprises a digital-to-analog conversion circuit, a data processing and control circuit, a DDS circuit, a band pass filter, a loop filter and an integration frequency synthesis chip. The digital-to-analog conversion circuit controls minimal modulation signals fm to obtain frequency modulation data after conversion of the digital-to-analogue conversion circuit, the frequency modulation data controls the operation with the frequency control words of the DDS circuit through the data processing and control circuit to control the output of the DDS circuit so that modulated signals with ultra low phase noise and ultra low straying, and the modulated signals, after passing through the band pass filter, are sent to the integration frequency synthesis chip to serve as reference signals of a phase-locked loop. By using such a scheme, by use of an analog-to-digital conversion and digital signal processing technologies and DDS and PLL mixing frequency synthesis technologies, direct current frequency modulation of broadband signals by minimal simulation signals can be realized.
Description
Technical field
The invention belongs to phase noise technical field of measurement and test, in particular the ultralow phase noise in a kind of broadband can direct current frequency modulation reference source circuit.
Background technology
In phase noise field tests, frequency discrimination/phase demodulation method is one of main method of measuring phase noise, has features such as measuring highly sensitive, measuring range is wide, separable AM noise and is used widely.But the sensitivity of measuring is subject to the restriction of the phase noise of reference source own, reference signal must be selected equal frequency according to measured signal, and reference signal phase noise is better than the phase noise of measured source, so reference source signal must be the synthesized frequency signal of the ultralow phase noise in broadband; In addition, in frequency discrimination/phase demodulation method, measure in phase noise process, measured signal and reference source signal mixing phase demodulation, the small noise signal that phase discriminator extracts is by digital sample, after processing, digital filter removes to drive the tuning end of reference source, form closed loop phase-locked loop, this just requires reference source to possess the function of being carried out direct current frequency modulation by small noise signal.
Frequency synthesis technique has experienced three generations, i.e. Direct Digital Frequency Synthesizer Technology (DS, Direct Frequency Synthesis), phase-locked Frequency Synthesis Technique Controlled (PLL) and direct digital frequency synthesis technology DDS (Direct Digital Synthesis).
Direct Digital Frequency Synthesizer Technology be with a crystal oscillator as with reference to source, through mixing, frequency division, frequency multiplication and bandpass filtering etc., obtain more multifrequency frequency content.At Direct Digital Frequency Synthesizer Technology aspect low phase noise frequency synthesis, there is outstanding advantage, but adopt this art designs reference source resolution low, and cannot realize direct current frequency modulation.
Phase-locked Frequency Synthesis Technique Controlled is to utilize one or several reference frequency source, by modes such as mixing or frequency divisions, produces a series of combination frequency, then use phase-locked loop the frequency locker of voltage controlled oscillator in reference frequency.Its advantage is that phase-locked loop is equivalent to a narrow band tracking filter, therefore can well select the signal of required frequency, suppresses spuious component, is conducive to integrated and miniaturization.Fractional Frequency-Dividing Technology was widely used on frequency of phase locking is synthetic in recent years, and direct current frequency modulation is achieved in phase-locked Frequency Synthesis Technique Controlled.
DDS is a kind of novel frequency, phase waveform synthetic technology, it take full advantage of large scale integrated circuit fast, the feature such as low-power consumption, large capacity, volume be little, compare with traditional frequency synthesizer, have that phase noise is low, frequency resolution is high, change the advantages such as rapid, its frequency, phase place changes continuity can be for phase place and frequency modulation(FM).But DDS output band is limited, actual maximum operating frequency will be obeyed Nyquist law, only has half of clock frequency, generally gets 40% left and right of clock frequency; The DDS's bringing due to the non-ideal characteristic of phase truncation, amplitude quantization error and digital-to-analogue conversion is spuious many.
The appearance of DDS technology makes to develop high performance frequency source becomes possibility, that is exactly thereby that DDS and front two generations synthetic technology mixing are used to comprehensively their advantage, and this frequency synthesizer is called hybrid frequency synthesizer (Hybrid Frequency Synthesis).DDS mixes use scheme with PLL is a lot, and different schemes has different features, is applicable to different requirement of engineering.
Figure 1 shows that existing solution, its utilization has the synthetic required frequency range of phase-locked loop and the frequency resolution of decimal frequency divider, and modulation signal is carried out after analog to digital conversion, and the fractional frequency division that is added to is than upper, the frequency that recently changes composite signal by changing fractional frequency division, realizes direct current frequency modulation.This fractional frequency-division phase-locked loop circuit comprises: reference clock, phase discriminator, integrator, voltage controlled oscillator, prescalar, sigma-delta decimal frequency divider and modulation signal modulate circuit.
The output signal of voltage controlled oscillator, directly export on one tunnel, another route prescalar and sigma-delta decimal frequency divider are realized frequency division, the signal of phase discriminator after to frequency division and the reference signal of reference clock output are carried out phase demodulation, integrator carries out integral filtering to the phase demodulation error signal of phase discriminator output, generate voltage controlled oscillator tuning error controling signal, control the output signal of voltage controlled oscillator and it is locked on reference clock frequency.Sigma-delta decimal frequency divider is FPGA circuit.Modulation signal is controlled modulation signal gain and biasing by the control module that gains, setovers, and realizes analog-to-digital conversion through analog to digital converter, and output 16 position digital signals are to sigma-delta decimal frequency divider.Sigma-delta decimal frequency divider also comprises register, storage fractional frequency division ratio.Modulation signal is loaded on the relevant position of register by 16 position datawires after 16 analog to digital converter conversions, thereby changed the frequency dividing ratio of fractional frequency division, because the frequency dividing ratio of decimal frequency divider changes according to the variation of modulation signal, the output signal of voltage controlled oscillator also changes by this rule, thereby has realized direct current frequency modulation.
Adopting FPGA circuit to realize the resolution that fractional frequency division can be subject to device operating frequency and fractional frequency division limits, the higher frequency of cannot working, can only under lower phase demodulation frequency, work, and higher phase demodulation frequency has improvement effect to the phase noise of phase-locked loop frequency synthesizer, therefore mentioned prior art cannot make the phase noise of composite signal reach best.
Adopt single phase-locked loop to carry out frequency synthesis, in the situation that reference frequency is lower, if improve the output frequency of composite signal, just the frequency dividing ratio of loop must be improved, and improve frequency dividing ratio, the deterioration of phase noise of composite signal can be caused and the improper reference source that is used as phase noise test.
If further improve the phase noise of composite signal on prior art basis, need to adopt the nested structure of a plurality of phase-locked loops, can make like this frequency synthesis scheme become very complicated, and increase cost.
Therefore, there is defect in prior art, needs to improve.
Summary of the invention
Technical problem to be solved by this invention is for the deficiencies in the prior art, and what the ultralow phase noise in a kind of broadband was provided can direct current frequency modulation reference source circuit.
Technical scheme of the present invention is as follows:
The ultralow phase noise in broadband can a direct current frequency modulation reference source circuit, wherein, comprise D/A converting circuit, data processing and control circuit, DDS circuit, band pass filter, loop filter and integrated frequency synthesis chip; Described D/A converting circuit is controlled small modulation signal fm and obtain frequcny modulation data after analog to digital conversion circuit conversion, frequcny modulation data is through data processing and control circuit is controlled and the frequency control word of DDS circuit carries out computing, control the output of DDS circuit, produce the ultralow spuious transferred signal of ultralow phase noise, described transferred signal sends to integrated frequency synthesis chip after band pass filter, as the reference signal of phase-locked loop.
Described reference source circuit, wherein, described D/A converting circuit comprises gain bias control circuit and A/D change-over circuit; Described gain bias control circuit consists of difference ADC driver AD8138 and resistance, electric capacity, inductance component, and small noise signal Sm is input to after gain bias control circuit after direct current biasing and amplitude are adjusted to the state that is applicable to the conversion of A/D change-over circuit and is input to A/D change-over circuit; Described A/D change-over circuit consists of 1.8V, 12,250Msps analog to digital converter MAX1215EGK and Resistor-Capacitor Unit, and A/D change-over circuit carries out output signal DATA1 after digital-to-analogue conversion by input signal.
Described reference source circuit, wherein, described Digital Signal Processing and control circuit, by digital signal processor, clock treatment circuit and Resistor-Capacitor Unit, formed, described digital signal processor is for carrying out digital filtering processing to 12 position digital signal DATA1, to meet the desired characteristics of signals of different test conditions, carry out digital filtering output signal DATA2; Described clock treatment circuit is that the clock signal fclk of input is carried out to frequency and amplitude conversion, reaches the instructions for use that meets digital signal processor.
Described reference source circuit, wherein, described DDS circuit is comprised of the direct synthesizer AD9912 of two spuious inhibition passages, 1000MHz ultra-low noise reference signal fref is connected to AD9912 as system clock through single-ended after the conversion of both-end, frequency control word CtrlDATA1 is produced and is delivered to FPGA through interface circuit by CPU, inner at FPGA, frequcny modulation data DATA2 and frequency control word CtrlDATA1 are added and obtain the output that new frequency control word CtrlDATA2 controls AD9912; Wherein, frequency control word CtrlDATA1 is set rear constant, frequcny modulation data DATA2 does not stop to be received under synchronised clock effect, and do computing with frequency control word CtrlDATA1, ceaselessly produce new frequency control word CtrlDATA2, frequency control word CtrlDATA2 does not stop to change the output frequency of AD9912 under synchronised clock effect, has realized the modulation to AD9912 output frequency, output signal f1.
Described reference source circuit, wherein, described phase-locked loop is for extending to 1.6～2.4GHz to the reference frequency output of DDS circuit; Described phase-locked loop adopts integrated frequency synthesizer HMC830, its inner integrated VCO, variable frequency divider, phase discriminator, charge pump; Described DDS circuit output signal f1 is after band pass filter, filter output f2 links the reference input of phase-locked loop phase discriminator, carry out phase demodulation with the signal f3 of variable frequency divider output, the error signal of charge pump output is connected with low pass filter, low pass filter filters the radio-frequency component in error signal, regulate the output frequency of VCO, make phase-locked loop obtain the final output signal fout of 1.6～2.4GHz; Described bandwidth of phase lock loop is set to 450-550kHz, and the band stray that DDS circuit carries and phase demodulation are spuious to be suppressed by loop.
Adopt such scheme: 1, adopt analog-to-digital conversion and Digital Signal Processing and DDS and PLL hybrid frequency synthetic technology, can realize the direct current frequency modulation of minute analog signal to wide-band microwave signal.2, adopt the ultralow phase noise reference signal of the synthetic upper frequency of advanced DDS integrated chip, adopt high phase comparison frequency to carry out phase-locked, reduced the deterioration of phase-locked loop to reference signal phase noise, guaranteed the ultralow phase noise characteristic of synthetic broadband signal.3, the phase-locked loop circuit that adopts superior performance, its inside is integrated with the circuit such as phase discriminator, charge pump, frequency divider and VCO, and VCO reference frequency output is high, can directly obtain higher composite signal frequency after phase-locked without frequency multiplication.
Accompanying drawing explanation
Fig. 1 realizes the circuit diagram of direct current frequency modulation by changing frequency dividing ratio in prior art.
Fig. 2 be the ultralow phase noise in broadband of the present invention can direct current frequency modulation reference source circuit figure.
Fig. 3 is DDS circuit diagram in the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Of the present inventionly realize principle as shown in Figure 2, mainly comprise D/A converting circuit, data processing and control, DDS circuit, band pass filter, loop filter and integrated frequency synthesis chip totally 6 parts, integrated frequency synthesis chip consists of phase discriminator, charge pump, voltage controlled oscillator and variable frequency divider.
Small modulation signal fm carries out computing with the frequency control word of DDS after analog-to-digital conversion, control the output of DDS, produce ultralow phase noise, ultralow spuious transferred signal, transferred signal is given phase-locked loop phase discriminator after band pass filter, as the reference signal of phase-locked loop.By controlling the variable frequency divider of phase-locked loop, realize broadband signal frequency synthesis.
Wherein, the major function of D/A converting circuit is that small noise signal fm is carried out to digital to analog conversion, is transformed to 12 position digital signals.In this circuit, comprise gain, biasing control and A/D conversion two parts, gain, biasing are controlled small noise signal fm are adjusted to the state that is applicable to A/D conversion, improve to greatest extent the effective utilization of A/D converter, the A/D device of walking around uses low distortion, difference ADC driver AD8138 and 1.8V, 12,250Msps analog to digital converter MAX1215EGK and Resistor-Capacitor Unit formation.
The effect of Digital Signal Processing and control circuit is that 12 position digital signals are processed and the data after processing are delivered to DDS module to obtaining.This circuit consists of digital signal processor, clock treatment circuit and relevant Resistor-Capacitor Unit.The effect of digital signal processor is that 12 position digital signals are carried out to digital filtering processing, to meet the desired characteristics of signals of different test conditions; Clock treatment circuit is that the clock signal of input is carried out to frequency and amplitude conversion, reaches the instructions for use that meets digital signal processor.
Be illustrated in figure 3 high-purity DDS module principle block diagram.For realizing ultralow phase noise, ultralow spuious, high-purity DDS module is selected the direct synthesizer AD9912 with two spuious inhibition passages.1000MHz ultra-low noise reference signal fref is connected to AD9912 as system clock through single-ended after the conversion of both-end, frequency control word 1 is delivered to FPGA by CPU through interface circuit, inner at FPGA, frequcny modulation data and frequency control word 1 are added and obtain the output that new frequency control word 2 is controlled AD9912.Frequency control word 1 is set rear constant, frequcny modulation data is ceaselessly received under synchronised clock effect, and do computing with frequency control word 1, ceaselessly produce new frequency control word 2, frequency control word 2 does not stop to change the output frequency of AD9912 under synchronised clock effect, has realized the modulation to AD9912 output frequency.
Phase-locked loop is that the reference frequency output of high-purity DDS module is extended to 1.6～2.4GHz.Phase-locked loop adopts integrated frequency synthesizer HMC830, its inner integrated functional unit such as VCO, variable frequency divider, phase discriminator, charge pump.High-purity DDS module output signal is linked the input of phase-locked loop phase discriminator after band pass filter, carries out phase demodulation with the signal of variable frequency divider output.The error signal of charge pump output is connected with low pass filter, and low pass filter filters the radio-frequency component in error signal, regulates the output frequency of VCO, makes VCO output frequency be locked in 1.6～2.4GHz.Phase-locked loop bandwidth is set to 500kHz left and right, and the band stray that DDS signal carries and phase demodulation are spuious to be suppressed by loop.
Embodiment 2
On the basis of above-described embodiment, further, as shown in Fig. 2-Fig. 3, the ultralow phase noise in a kind of broadband can direct current frequency modulation reference source circuit, wherein, comprise D/A converting circuit, data processing and control circuit, DDS circuit, band pass filter, loop filter and integrated frequency synthesis chip; Described D/A converting circuit is controlled small modulation signal fm and obtain frequcny modulation data after analog to digital conversion circuit conversion, frequcny modulation data is through data processing and control circuit is controlled and the frequency control word of DDS circuit carries out computing, control the output of DDS circuit, produce the ultralow spuious transferred signal of ultralow phase noise, described transferred signal sends to integrated frequency synthesis chip after band pass filter, as the reference signal of phase-locked loop.
Described D/A converting circuit comprises gain, bias control circuit and A/D change-over circuit; Described gain, bias control circuit consist of difference ADC driver AD8138 and resistance, electric capacity, inductance component, and small noise signal Sm is input to after gain bias control circuit after direct current biasing and amplitude are adjusted to the state that is applicable to the conversion of A/D change-over circuit and is input to A/D change-over circuit; Described A/D change-over circuit consists of 1.8V, 12,250Msps analog to digital converter MAX1215EGK and Resistor-Capacitor Unit, and A/D change-over circuit carries out output signal DATA1 after digital-to-analogue conversion by input signal.
Described Digital Signal Processing and control circuit, by digital signal processor, clock treatment circuit and Resistor-Capacitor Unit, formed, described digital signal processor is for carrying out digital filtering processing to 12 position digital signal DATA1, to meet the desired characteristics of signals of different test conditions, carry out digital filtering output signal DATA2; Described clock treatment circuit is that the clock signal fclk of input is carried out to frequency and amplitude conversion, reaches the instructions for use that meets digital signal processor.
Described DDS circuit is comprised of the direct synthesizer AD9912 of two spuious inhibition passages, 1000MHz ultra-low noise reference signal fref is connected to AD9912 as system clock through single-ended after the conversion of both-end, frequency control word CtrlDATA1 is produced and is delivered to FPGA through interface circuit by CPU, inner at FPGA, frequcny modulation data DATA2 and frequency control word CtrlDATA1 are added and obtain the output that new frequency control word CtrlDATA2 controls AD9912; Wherein, frequency control word CtrlDATA1 is set rear constant, frequcny modulation data DATA2 does not stop to be received under synchronised clock effect, and do computing with frequency control word CtrlDATA1, ceaselessly produce new frequency control word CtrlDATA2, frequency control word CtrlDATA2 does not stop to change the output frequency of AD9912 under synchronised clock effect, has realized the modulation to AD9912 output frequency, output signal f1.
Described phase-locked loop is for extending to 1.6～2.4GHz to the reference frequency output of DDS circuit; Described phase-locked loop adopts integrated frequency synthesizer HMC830, its inner integrated VCO, variable frequency divider, phase discriminator, charge pump; Described DDS circuit output signal f1 is after band pass filter, filter output f2 links the reference input of phase-locked loop phase discriminator, carry out phase demodulation with the signal f3 of variable frequency divider output, the error signal of charge pump output is connected with low pass filter, low pass filter filters the radio-frequency component in error signal, regulate the output frequency of VCO, make phase-locked loop obtain the final output signal fout of 1.6～2.4GHz; Described bandwidth of phase lock loop is set to 450-550kHz, and the band stray that DDS circuit carries and phase demodulation are spuious to be suppressed by loop.
Adopt such scheme: 1, adopt analog-to-digital conversion and Digital Signal Processing and DDS and PLL hybrid frequency synthetic technology, can realize the direct current frequency modulation of minute analog signal to wide-band microwave signal.2, adopt the ultralow phase noise reference signal of the synthetic upper frequency of advanced DDS integrated chip, adopt high phase comparison frequency to carry out phase-locked, reduced the deterioration of phase-locked loop to reference signal phase noise, guaranteed the ultralow phase noise characteristic of synthetic broadband signal.3, the phase-locked loop circuit that adopts superior performance, its inside is integrated with the circuit such as phase discriminator, charge pump, frequency divider and VCO, and VCO reference frequency output is high, can directly obtain higher composite signal frequency after phase-locked without frequency multiplication.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection range of claims of the present invention.
Claims (5)
- The ultralow phase noise in broadband can a direct current frequency modulation reference source circuit, it is characterized in that, comprise D/A converting circuit, data processing and control circuit, DDS circuit, band pass filter, loop filter and integrated frequency synthesis chip; Described D/A converting circuit is controlled small modulation signal fm and obtain frequcny modulation data after analog to digital conversion circuit conversion, frequcny modulation data is through data processing and control circuit is controlled and the frequency control word of DDS circuit carries out computing, control the output of DDS circuit, produce the ultralow spuious transferred signal of ultralow phase noise, described transferred signal sends to integrated frequency synthesis chip after band pass filter, as the reference signal of phase-locked loop.
- 2. reference source circuit as claimed in claim 1, is characterized in that, described D/A converting circuit comprises gain, bias control circuit and A/D change-over circuit; Described gain, bias control circuit consist of difference ADC driver AD8138 and resistance, electric capacity, inductance component, small noise signal Sm is input to gain, bias control circuit, and direct current biasing and amplitude are input to A/D change-over circuit after being adjusted to the state that is applicable to the conversion of A/D change-over circuit; Described A/D change-over circuit consists of 1.8V, 12,250Msps analog to digital converter MAX1215EGK and Resistor-Capacitor Unit, and A/D change-over circuit carries out output signal DATA1 after digital-to-analogue conversion by input signal.
- 3. reference source circuit as claimed in claim 1, it is characterized in that, described Digital Signal Processing and control circuit, by digital signal processor, clock treatment circuit and Resistor-Capacitor Unit, formed, described digital signal processor is for carrying out digital filtering processing to 12 position digital signal DATA1, to meet the desired characteristics of signals of different test conditions, carry out digital filtering output signal DATA2; Described clock treatment circuit is that the clock signal fclk of input is carried out to frequency and amplitude conversion, reaches the instructions for use that meets digital signal processor.
- 4. reference source circuit as claimed in claim 1, it is characterized in that, described DDS circuit is comprised of the direct synthesizer AD9912 of two spuious inhibition passages, 1000MHz ultra-low noise reference signal fref is connected to AD9912 as system clock through single-ended after the conversion of both-end, frequency control word CtrlDATA1 is produced and is delivered to FPGA through interface circuit by CPU, inner at FPGA, frequcny modulation data DATA2 and frequency control word CtrlDATA1 are added and obtain the output that new frequency control word CtrlDATA2 controls AD9912; Wherein, frequency control word CtrlDATA1 is set rear constant, frequcny modulation data DATA2 does not stop to be received under synchronised clock effect, and do computing with frequency control word CtrlDATA1, ceaselessly produce new frequency control word CtrlDATA2, frequency control word CtrlDATA2 does not stop to change the output frequency of AD9912 under synchronised clock effect, has realized the modulation to AD9912 output frequency, output signal f1.
- 5. reference source circuit as claimed in claim 1, is characterized in that, described phase-locked loop circuit is for extending to 1.6～2.4GHz to the reference frequency output of DDS circuit; Described phase-locked loop adopts integrated frequency synthesizer HMC830, its inner integrated VCO, variable frequency divider, phase discriminator, charge pump; Described DDS circuit output signal f1 is after band pass filter, filter output f2 links the reference input of phase-locked loop phase discriminator, carry out phase demodulation with the signal f3 of variable frequency divider output, the error signal of charge pump output is connected with low pass filter, low pass filter filters the radio-frequency component in error signal, regulate the output frequency of VCO, make phase-locked loop obtain the final output signal fout of 1.6～2.4GHz; Described phase-locked loop circuit bandwidth is set to 450-550kHz, and the band stray that DDS circuit carries and phase demodulation are spuious to be suppressed by loop.
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| CN105515575A (en) * | 2015-12-05 | 2016-04-20 | 青岛盛嘉信息科技有限公司 | Sinusoidal signal frequency generator |
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| CN109936363A (en) * | 2019-03-06 | 2019-06-25 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency-division phase-locked loop system and its spuious optimization method |
| CN109936363B (en) * | 2019-03-06 | 2023-08-04 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency division phase-locked loop system and spurious optimization method thereof |
| CN110504962A (en) * | 2019-07-17 | 2019-11-26 | 晶晨半导体(上海)股份有限公司 | Digital compensation simulates fractional frequency-division phase-locked loop and control method |
| CN112073014A (en) * | 2020-09-09 | 2020-12-11 | 青岛青源峰达太赫兹科技有限公司 | Phase-locked amplifier for terahertz system and phase-locked amplifier signal demodulation method |
| CN112073014B (en) * | 2020-09-09 | 2024-07-09 | 青岛青源峰达太赫兹科技有限公司 | Phase-locked amplifier for terahertz system and phase-locked amplifier signal demodulation method |
| CN112653459A (en) * | 2020-12-28 | 2021-04-13 | 成都美数科技有限公司 | Radio frequency signal source capable of being calibrated in real time |
| CN113271140A (en) * | 2021-05-17 | 2021-08-17 | 东南大学 | Method for realizing precise phase shift by using digital switch mode |
| CN115425967A (en) * | 2022-08-31 | 2022-12-02 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
| CN115425967B (en) * | 2022-08-31 | 2023-11-14 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
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