CN103544992A - Nonvolatile high-speed storage unit as well as storage device and inner data unloading control method of storage device - Google Patents
Nonvolatile high-speed storage unit as well as storage device and inner data unloading control method of storage device Download PDFInfo
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Abstract
The invention provides a nonvolatile high-speed storage unit as well as a storage device containing the nonvolatile high-speed storage unit and an inner data unloading control method of the storage device. The nonvolatile high-speed storage unit comprises a double-stable-state latch circuit, a nonvolatile storage circuit and a loading control switch, wherein the nonvolatile storage circuit comprises a first transistor, a programmable second transistor and a third transistor. The nonvolatile high-speed storage unit is high in accessing speed, short in control flow and simple in structure; the problems in the prior art can be solved very well; only an insulating grid electrode control end FG is connected to the double-stable-state latch circuit when programming or loading is not carried out; the isolation performance between a volatile high-speed storage unit and the nonvolatile high-speed storage unit is good.
Description
Technical field
The present invention relates to a kind of semiconductor memory, relate in particular to the nonvolatile memory that comprises volatile memory cell.
Background technology
In existing semiconductor memory, mainly use the storer of two types, volatibility (volatile) storer and non-volatile (non-volatile) storer.Nonvolatile memory common are ROM (read-only memory) (read-only memory, ROM), EPROM (Erasable Programmable Read Only Memory) (electrically programmable read-only memory for example, EPROM), EEPROM (Electrically Erasable Programmable Read Only Memo) (electrically erasable-programmable read-only memory, EEPROM) and flash ROM (flash read-only memory) etc., these storeies do not need external power source can maintain the data that it is preserved.Volatile memory mainly comprises dynamic RAM (dynamic random access memory, DRAM) and static RAM (static random accessmemory, SRAM), the writing speed of these storeies is fast compared with nonvolatile memory, is therefore generally used for the data of temporary high speed processing.Different in nonvolatile memory, volatile memory is not in the situation that powering, and data can not be preserved, and therefore, when maintaining data for a long time, need external power source.
[citing document 1]: U.S. Patent number 5065362
[citing document 2]: Chinese Patent Application No. 200910170438.3
Along with scientific and technological development, the transmission speed of data is greatly improved, can storing data permanently in order to realize, can rapidly data preservation not affected to the processing speed of system again, proposed at first a nonvolatile memory and a volatile memory to combine use, mainly that way is first to utilize volatile memory that the data of system are saved, then under the power supply of accessory power supply, then by the data conversion storage of volatile memory in nonvolatile memory.Afterwards, discovery is in the process of data conversion storage, need the data in first erasable nonvolatile memory, consuming time longer, and to configure jumbo accessory power supply, in the situation that accessory power supply is electric capacity, when the power-on time of system too short, and capacitor charging is when not enough, easily there is the situation that data conversion storage is imperfect or failed.For these defects, U.S. Patent number is that 5065362 instructions discloses a kind of Nonvolatile static random access memory (non-volatile static random access memory, NVSRAM), as shown in Figure 1, its each bit (bit) memory circuit is mainly comprised of three parts, is respectively the volatile memory cell of bi-stable latch circuit 12 formations and the non-volatile memory cells that three transistor circuits 14 form.The conducting when volatile memory cell is worked due to transistor 40c and 42c, does not keep apart non-volatile memory cells and volatile memory cell.
Yet two non-volatile memory cells and volatile memory cell form the mode of a bit storage circuit, relatively take circuit area, are unfavorable for reducing costs.For this reason, the instructions of Chinese Patent Application No. 200910170438.3 discloses non-volatile memory cells of a kind of use and a volatile memory cell just can form the scheme of a bit storage circuit, as shown in Figure 2, this memory circuit is mainly by bi-stable latch circuit 200, negative circuit 310 and three transistor circuits 320 form, the grid voltage of transistor T 23 is independently controlled by VSTR, can isolate well non-volatile memory cells and volatile memory cell.When the non-volatile memory cells forming from three transistor circuits 320 is written into data to bi-stable latch circuit 200, need first the voltage of VCCI to be connect to VSS current potential, bit line BT and BC are set in earthing potential, then by word line WL is set in to noble potential and node DT and DC are discharged into earthing potential, after electric discharge, word line WL is set to earthing potential again.Follow turn-on transistor T21 and T23, non-volatile memory cells is connected to volatile memory cell, grid voltage VSE by setting T22 is to noble potential, just the data of non-volatile memory cells can be written into bi-stable latch circuit 200, even T22 conducting, node DC can be charged to noble potential by VCC, opens transistor T 12 node DC is maintained to earthing potential thereby control phase inverter 310 cuts out transistor T 11; On the contrary, if not conducting of T22, node DC maintains earthing potential, thereby by phase inverter, node DT is charged to noble potential.
From above-mentioned analysis, memory circuit shown in Fig. 2 relates to very many control signals when being written into the data of non-volatile memory cells, flow process is complicated, out of order probability strengthens, but also there is a collision problem: at node DT and DC, be all discharged into after earthing potential, if VCC, VRCL, VSE and VSTR are set to noble potential simultaneously, if T22 conducting, consider the response time of T22, node DT can first be charged to noble potential, then node DC is charged to noble potential, under the effect of phase inverter 310, again node DT is discharged to earthing potential again, after this VCCI connects noble potential bi-stable latch circuit 200 and just can enter stable state, even if VRCL, VSE and VSTR are set to noble potential prior to VCC, node DT and DC also need a period of time just can enter stable state, and more complicated on controlling.Visible this circuit speed when being written into data is desirable not.While disconnecting for externally powering, from volatile memory cell unloading data to non-volatile memory cells, the grid of transistor T 22 need to apply one from earthing potential to negative potential, then to noble potential, needs more complicated charge pump circuit.
Therefore, how to provide a kind of circuit area of more saving, control simplyr, speed faster nonvolatile memory is research topic of the present invention.
Summary of the invention
The invention provides a kind of Nonvolatile storage unit in high speed, it comprises bi-stable latch circuit, non-volatile memory and is written into gauge tap, this non-volatile memory comprises the first transistor, programmable transistor seconds and the 3rd transistor, and described the first transistor comprises:
Control end, accepts to store the control voltage of data;
First end, is connected to the first stable state end of bi-stable latch circuit;
The second end;
Described programmable transistor seconds comprises:
Control end, is connected to the second stable state end of bi-stable latch circuit;
First end, is connected to the second end of the first transistor;
The second end;
Described the 3rd transistor comprises:
Control end, acceptance is written into the auxiliary control voltage of data;
First end, is connected to the second end of described programmable transistor seconds;
The second end, is connected to earthing potential;
Described one end that is written into gauge tap is connected to the second stable state end of bi-stable latch circuit, and the other end is connected to the first end of programmable transistor seconds, and its control end accepts to be written into the control voltage of data.
Further, described Nonvolatile storage unit in high speed also comprises the first presetting bit gauge tap, one end of described the first presetting bit gauge tap is connected to the first stable state end of bi-stable latch circuit, and the other end is connected to earthing potential, and its control end is accepted the control voltage of presetting bit.
Further, described Nonvolatile storage unit in high speed also comprises the second presetting bit gauge tap, one end of described the second presetting bit gauge tap is connected to the second stable state end of bi-stable latch circuit, and the other end is connected to noble potential, and its control end is accepted the control voltage of presetting bit.
The present invention also provides a kind of Nonvolatile storage unit in high speed, it comprises bi-stable latch circuit and non-volatile memory, described non-volatile memory comprises the 4th transistor, programmable the 5th transistor and the 6th transistor, and described the 4th transistor comprises:
Control end, accepts to store the control voltage of data;
First end, is connected to the first stable state end of bi-stable latch circuit;
The second end;
Described programmable the 5th transistor comprises:
Control end, is connected to the second stable state end of bi-stable latch circuit;
First end, is connected to the 4th transistorized the second end;
The second end;
Described the 6th transistor comprises:
Control end, acceptance is written into the control voltage of data;
First end, is connected to programmable the 5th transistorized the second end;
The second end, is connected to noble potential.
The present invention also provides a kind of nonvolatile memory, it is characterized in that, it comprises a plurality of above-mentioned Nonvolatile storage unit in high speed.
The present invention also provides a kind of control method of memory inside data conversion storage, and this storer comprises arbitrary above-mentioned Nonvolatile storage unit in high speed, and described control method comprises programmed method and loading method, and described programmed method comprises:
Transformation step, raises to meet programming by the supply voltage of described bi-stable latch circuit;
Unsettled step, closes the 3rd transistor by the 3rd transistorized control end is put to earthing potential;
Programming step, by send into the first transistor described in a high-voltage pulse conducting toward the control end of the first transistor, described programmable transistor seconds is carried out programming according to the voltage of its first end and its control end;
Described loading method comprises:
Set step, is set to noble potential by the second stable state end of described bi-stable latch circuit;
Conducting step, by setting high the 3rd transistorized control end in current potential conducting the 3rd transistor;
Be written into step, by sending into a high-voltage pulse conducting toward the control end that is written into gauge tap, be written into gauge tap, the second stable state end of described bi-stable latch circuit is discharged to earthing potential when programmable transistor seconds conducting, maintains noble potential when programmable transistor seconds is closed.
Accompanying drawing explanation
Technical scheme of the present invention is described for convenience; below provide several enforcement illustrations; can predict, those of ordinary skill in the art can make other accompanying drawings in the situation that not departing from aim of the present invention, and to this, should not understand these accompanying drawings is limiting the scope of the invention.
It shown in Fig. 1, is the storage unit circuit of a kind of nonvolatile memory of the prior art;
It shown in Fig. 2, is the storage unit circuit of another kind of nonvolatile memory of the prior art;
Shown in Fig. 3 is the Nonvolatile storage unit in high speed of first embodiment of the invention;
Shown in Fig. 4 is the Nonvolatile storage unit in high speed of second embodiment of the invention;
Shown in Fig. 5 is the Nonvolatile storage unit in high speed of third embodiment of the invention;
Shown in Fig. 6 is the Nonvolatile storage unit in high speed of fourth embodiment of the invention.
embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in detail.
Through the inventor, in conjunction with advantages more of the prior art, cost-saving, reduce aspects such as controlling difficulty and done further research, propose following technical scheme.
Embodiment mono-
Referring to Fig. 3, it is the Nonvolatile storage unit in high speed circuit structure diagram of embodiments of the invention one.
This Nonvolatile storage unit in high speed comprises bi-stable latch circuit, non-volatile memory and is written into gauge tap, in Fig. 3, bi-stable latch circuit is comprised of transistor T 1, T2, T3 and T4, binding crystal pipe T5 and T6, just formed common 6T (transistor, transistor) structure SRAM, certainly, bi-stable latch circuit can also have other circuit structure, its structure composition and working principle can be with reference to [citing document 2], and it belongs to prior art, does not repeat them here.In Fig. 3, this non-volatile memory comprises the first transistor T8, programmable transistor seconds T9 and the 3rd transistor T 10, is written into gauge tap and consists of transistor T 7.
Described the first transistor T8 comprises: control end STORE, accepts to store the control voltage of data; First end, is connected to the first stable state end DC of bi-stable latch circuit; The second end, is connected to the first end of transistor seconds T9;
Described programmable transistor seconds T9 comprises: control end FG, is connected to the second stable state end DT of bi-stable latch circuit; First end, is connected respectively to and is written into one end of gauge tap and the second end of the first transistor; The second end, be connected to the first end of the 3rd transistor T 10, because programmable transistor seconds T9 will realize record data, T9 is generally programmable transistor, floating boom tunnel oxide transistor (floating gate tunnel oxide, FLOTOX) for example, as prior art, can, with reference to [citing document 2], at this, no longer the type of T9 be repeated;
Described the 3rd transistor T 10 comprises: control end SET2, and acceptance is written into the auxiliary control voltage of data; First end, is connected to the second end of programmable transistor seconds T9; The second end, is connected to earthing potential;
Described one end that is written into gauge tap is connected to the second stable state end DT of bi-stable latch circuit, and the other end is connected to the first end of programmable transistor seconds T9, and its control end RECALL accepts to be written into the control voltage of data.
The following describes the control method of its principle of work and internal data unloading, the programmable transistor seconds T9 of only take is that N-type FLOTOX is example.
1.1 from volatile memory cell toward non-volatile memory cells unloading data, the i.e. method of " programming ".
Starting, " programming " is front, the control end RECALL that is written into gauge tap T7 connects earthing potential, T7 is closed, the control end SET2 of the 3rd transistor T 10 puts earthing potential, close T10, now the source electrode of programmable transistor seconds T9 is unsettled, then by means such as charge pumps, VCC voltage is raise to meet programming, and the current potential of the control end FG of transistor seconds T9 is consistent with the second stable state end DT current potential.Suppose that at " programming " front bi-stable latch circuit first stable state end DC be earthing potential, i.e. " 0 ", the second stable state end DT is noble potential, i.e. " 1 ", enter " programming " stage, now the control end STORE toward the first transistor T8 sends into a high-voltage pulse, the first transistor T8 conducting, the drain electrode of programmable transistor seconds T9 is connected to the first stable state end DC, T9 connects programming high pressure at control end FG, during drain electrode termination earthing potential, no matter the state of original T9 how, capital is programmed, electronics is pulled in suspended grid, now be equivalent to write data " 1 " in T9, consistent with the second stable state end DT.
On the contrary, if be noble potential at " programming " front bi-stable latch circuit first stable state end DC, i.e. " 1 ", the second stable state end DT is earthing potential, i.e. " 0 ",, after starting program, T9 connects earthing potential at control end FG, during drain electrode termination programming high pressure, no matter the state of original T9 is how, all can be eliminated, the electronics in suspended grid is withdrawn in drain electrode, now be equivalent to write data " 0 " in T9, consistent with the second stable state end DT.
As can be seen here, Nonvolatile storage unit in high speed of the present invention is when record data arrive non-volatile memory, speed is fast, control flow is short, simple in structure, can solve well problems of the prior art, and when not carrying out " programming ", only have the grid control end FG of insulation to be connected to bi-stable latch circuit, the isolation performance of volatile memory cell and non-volatile memory cells is good.
1.2 from non-volatile memory cells toward volatile memory cell unloading data, the method " being written into ".
Starting, " being written into " is front, first carry out initialization, the second stable state end DT of bi-stable latch circuit is set to noble potential, i.e. " 1 ", the second stable state end DT set is had to several different methods, for example, by method of the prior art, by control word line WL and bit line BL, BLC, the mode of directly past SRAM data writing " 1 ", or by the method for electric discharge, the current potential of the first stable state end DC is discharged to earthing potential (embodiment bis-is described in detail) below, or by the method for charging, the current potential of the second stable state end DT is charged to noble potential (embodiment tri-is described in detail) below, because the control end FG of transistor seconds T9 is identical with the current potential of the second stable state end DT, for noble potential.Starting, " being written into " is front, and the control end SET2 of the 3rd transistor T 10 sends into high level, with conducting T10.Enter " being written into " stage, now toward the control end RECALL that is written into gauge tap T7, send into a high-voltage pulse, T7 conducting.Suppose before initialization, programmable transistor seconds T9 has write data " 0 ", transistor seconds T9 conducting when control end FG is noble potential, the second stable state end DT is by the T7 being connected in series, programmable transistor seconds T9 and the 3rd transistor T 10 ground connection, be discharged to earthing potential, the second stable state end DT has been written into data " 0 ", consistent with programmable transistor seconds T9 recorded data.
At the second stable state end DT by the T7 being connected in series, transistor seconds T9 and the 3rd transistor T 10 are discharged in earthing potential process, the voltage of the control end FG of programmable transistor seconds also and then declines, the velocity of discharge of the second stable state end DT is slack-off, but because the control of Electric potentials of the second stable state end DT the grid of T1, T1 opens gradually, VCC promotes the current potential of the first stable state end DC by T1, because the grid of T4 connects the first stable state end DC, the current potential of the first stable state end DC promotes opens T4 conversely gradually, the second stable state end DT also can discharge by T4, finally make the current potential of the second stable state end DT reach rapidly earthing potential.
On the contrary, suppose before initialization, programmable transistor seconds T9 has write data " 1 ", when control end FG is noble potential, transistor seconds T9 still maintains and closes, the second stable state end DT can not discharge by transistor seconds T9, now the second stable state end DT maintains noble potential, is equivalent to the second stable state end DT and has been written into data " 1 ", consistent with programmable transistor seconds T9 recorded data.
As can be seen here, Nonvolatile storage unit in high speed of the present invention is when being written into data to volatile memory circuit, control flow is short, simple in structure, can solve well problems of the prior art, and when not carrying out " being written into ", only have the grid control end FG of insulation to be connected to bi-stable latch circuit, the isolation performance of volatile memory cell and non-volatile memory cells is good.
Embodiment bis-
Initialization bi-stable latch circuit, can also, by the method for electric discharge, be discharged to earthing potential by the current potential of the first stable state end DC by the second stable state end DT set.Shown in Figure 4, non-volatile high speed storing list provided by the invention can also comprise the first presetting bit gauge tap, in Fig. 4, this first presetting bit gauge tap is transistor T 11, one end of T11 is connected to the first stable state end DC of bi-stable latch circuit, the other end is connected to earthing potential, and its control end SET1 accepts the control voltage of presetting bit.
When initialization, toward control end SET1, send into a high-voltage pulse so, by transistor T 11 conductings, the first stable state end DC is just by transistor T 11 ground connection, and the first stable state end DC is discharged to earthing potential.Principle by bi-stable latch (T1, T2, T3 and T4 form) is known, and the second stable state end DT will be charged to noble potential by VCC, i.e. set.
Such initialization mode, steering logic is simple, and shortcoming is to increase a transistor, has taken circuit area.In application, can be according to the design of physical circuit, on steering logic and circuit area, according to cost is lower aspect which, accept or reject.
Embodiment tri-
Initialization bi-stable latch circuit, except above-mentioned method, can also, by the method for charging, charge to noble potential by the current potential of the second stable state end DT by the second stable state end DT set.Shown in Figure 5, non-volatile high speed storing list provided by the invention can also comprise the second presetting bit gauge tap, in Fig. 5, this second presetting bit gauge tap is transistor T 11, one end of T11 is connected to the second stable state end DT of bi-stable latch circuit, the other end is connected to noble potential VCC, and its control end SET1 accepts the control voltage of presetting bit.
When initialization, toward control end SET1, send into a high-voltage pulse so, by transistor T 11 conductings, the second stable state end DT is just connected to noble potential VCC by transistor T 11, and the second stable state end DT is charged to noble potential, i.e. set.Principle by bi-stable latch (T1, T2, T3 and T4 form) is known, and the first stable state end DC will be discharged to earthing potential.
Such initialization mode, steering logic is simple, and shortcoming is to increase a transistor, has taken circuit area.In application, can be according to the design of physical circuit, on steering logic and circuit area, according to cost is lower aspect which, accept or reject.
Embodiment tetra-
Referring to Fig. 6, it is the Nonvolatile storage unit in high speed circuit structure diagram of embodiments of the invention four.
This Nonvolatile storage unit in high speed comprises bi-stable latch circuit and non-volatile memory, and in Fig. 6, bi-stable latch circuit and embodiment's mono-is consistent, does not repeat them here.In Fig. 6, this non-volatile memory comprises the 4th transistor T 12, programmable the 5th transistor T 13 and the 6th transistor T 14.
Described the 4th transistor T 12 comprises: control end STORE, accepts to store the control voltage of data; First end, is connected to the first stable state end DC of bi-stable latch circuit; The second end, is connected to the first end of programmable the 5th transistor T 13;
Described programmable the 5th transistor T 13 comprises: control end FG, is connected to the second stable state end DT of bi-stable latch circuit; First end, is connected to the second end of the 4th transistor T 12; The second end, is connected to the first end of the 6th transistor T 14, and because the 5th transistor T 13 will be realized record data, the type of T13 is consistent with the T9 in embodiment mono-, does not repeat them here;
Described the 6th transistor T 14 comprises: control end RECALL, and acceptance is written into the control voltage of data; First end, is connected to the second end of programmable the 5th transistor T 13; The second end, is connected to noble potential.
The following describes the control method of its principle of work and internal data unloading, programmable the 5th transistor T 13 of only take is that N-type FLOTOX is example.
4.1 from volatile memory cell toward non-volatile memory cells unloading data, the i.e. method of " programming ".
Starting, " programming " is front, the control end RECALL of the 6th transistor T 14 connects earthing potential, T14 is closed, now the source electrode of programmable the 5th transistor T 13 is unsettled, then by means such as charge pumps, VCC voltage is raise to meet programming, and the current potential of the control end FG of programmable the 5th transistor T 13 is consistent with the second stable state end DT current potential.Suppose that at " programming " front bi-stable latch circuit first stable state end DC be earthing potential, i.e. " 0 ", the second stable state end DT is noble potential, i.e. " 1 ", enter " programming " stage, now the control end STORE toward the 4th transistor T 12 sends into a high-voltage pulse, the 4th transistor T 12 conductings, the drain electrode of programmable the 5th transistor T 13 is connected to the first stable state end DC, T13 connects programming high pressure at control end FG, during drain electrode termination earthing potential, no matter the state of original T13 how, capital is programmed, electronics is pulled in suspended grid, now be equivalent to write data " 1 " in T13, consistent with the second stable state end DT.
On the contrary, if be noble potential at " programming " front bi-stable latch circuit first stable state end DC, i.e. " 1 ", the second stable state end DT is earthing potential, i.e. " 0 ",, after starting program, T13 connects earthing potential at control end FG, during drain electrode termination programming high pressure, no matter the state of original T13 is how, all can be eliminated, the electronics in suspended grid is withdrawn in drain electrode, now be equivalent to write data " 0 " in T13, consistent with the second stable state end DT.
As can be seen here, Nonvolatile storage unit in high speed of the present invention is when record data arrive non-volatile memory, speed is fast, control flow is short, simple in structure, can solve well problems of the prior art, and when not carrying out " programming ", only have the grid control end FG of insulation to be connected to bi-stable latch circuit, the isolation performance of volatile memory cell and non-volatile memory cells is good.
4.2 from non-volatile memory cells toward volatile memory cell unloading data, the method " being written into ".
Starting, " being written into " is front, first carry out initialization, the second stable state end DT of bi-stable latch circuit is set to noble potential, i.e. " 1 ", the second stable state end DT set is had to several different methods, can be referring to embodiment mono-above, the description of embodiment bis-and embodiment tri-, for example, by method of the prior art, by control word line WL and bit line BL, BLC, the mode of directly past SRAM data writing " 1 ", or by the method for electric discharge, the current potential of the first stable state end DC is discharged to earthing potential, or by the method for charging, the current potential of the second stable state end DT is charged to noble potential, because the control end FG of transistor seconds T9 is identical with the current potential of the second stable state end DT, for noble potential.Starting, " being written into " is front, and the control end STORE of the 4th transistor T 12 sends into high level, with conducting T12.Enter " being written into " stage, now the control end RECALL toward the 6th transistor T 14 sends into a high-voltage pulse, T14 conducting.Suppose before initialization, programmable the 5th transistor T 13 has write data " 0 ", the 5th transistor T 13 conductings when control end FG is noble potential, the first stable state end DC is connected to noble potential VCC by T12, T13 and the T14 being connected in series, the first stable state end DC can be charged to noble potential, under the effect of bi-stable latch, the second stable state end DT can be discharged to earthing potential, the second stable state end DT has been written into data " 0 ", consistent with programmable the 5th transistor T 13 recorded data.
At the first stable state end DC by the T12 being connected in series, T13 and T14 are charged in the process of noble potential, effect due to bi-stable latch, the voltage of the control end FG of programmable transistor seconds is the and then current potential of the second stable state end DT decline also, so that the charging rate of the first stable state end DC is slack-off, but because the control of Electric potentials of the first stable state end DC the grid of T4, T4 opens gradually, the second stable state end DC discharges by T4, current potential declines gradually, because the grid of T1 connects the second stable state end DT, the current potential of the second stable state end DT declines and opens gradually conversely T1, VCC charges to the first stable state end DC by T1, finally make the current potential of the first stable state end DC reach rapidly noble potential.
On the contrary, suppose before initialization, programmable the 5th transistor T 13 has write data " 1 ", when control end FG is noble potential, transistor seconds T13 still maintains and closes, the first stable state end DC can not be by the 5th transistor T 13 chargings, now the first stable state end DC maintains earthing potential, effect due to bi-stable latch, the second stable state end DT maintains noble potential, be equivalent to the second stable state end DT and be written into data " 1 ", consistent with programmable the 5th transistor T 13 recorded data.
As can be seen here, Nonvolatile storage unit in high speed of the present invention is when being written into data to volatile memory circuit, control flow is short, simple in structure, can solve well problems of the prior art, and when not carrying out " being written into ", only have the grid control end FG of insulation to be connected to bi-stable latch circuit, the isolation performance of volatile memory cell and non-volatile memory cells is good.
Embodiment five
The present invention also provides a kind of nonvolatile memory, and this nonvolatile memory comprises any one Nonvolatile storage unit in high speed in a plurality of above-mentioned each embodiment.
Variation one
In digital circuit, noble potential (or high level) generally refers to 3.5-5V (voltage, volt); Electronegative potential (or low level) refers generally to 0-1.5V, has comprised earthing potential; Generally refer to-3.5V of negative level (negative voltage) is to-5V; Programming high pressure generally refers to 13V-36V, but as the common practise of persons skilled in the art, different technique, element, and needed high and low, negative level and programming high pressure are different, the present invention is not limited this.
Variation two
When the control end FG of transistor seconds T9 not being connected to bi-stable latch circuit, but while being controlled by external signal, can write the data in the SRAM that reads bi-stable latch circuit formation by memory read/write control circuit of the prior art, then according to data, generate control signal and input to control end FG, but such method can increase by one to be read the time, while causing toward non-volatile memory cells unloading data, speed is slack-off.
Variation three
In the above embodiments, transistor T 5 to T14 in Fig. 3 to Fig. 6 is all described with N-type field effect transistor, the feature of N-type field effect transistor is when grid applies high level, conducting between the source electrode of field effect transistor and drain electrode, these transistors play a part controlled switch in circuit, common practise as one of ordinary skill in the art, transistor T 5 to T14 in Fig. 3 to Fig. 6 can also be P type field effect transistor, between its source electrode of needs and drain electrode during conducting, just on its grid, apply low level or negative level (negative voltage), to utilize electronics to conduct electricity different from N-type field effect transistor, P type field effect transistor utilizes hole to conduct electricity, as common practise, repeat no more here.Known, when above-mentioned transistor adopts P type field effect transistor, while applying low level or negative level pulse on control end RECALL, control end STORE, control end SET1 and control end SET2, its transistor of controlling of conducting momently just.For programmable transistor T 9 and T13, while adopting P type FLOTOX, its while writing " 1 ", be on its grid, apply low level or negative level with the hole of drawing drain electrode to suspended grid, while writing " 0 ", be on its grid, to apply high level so that the hole on suspended grid is withdrawn in drain electrode.Known in embodiment corresponding to earlier figures 3 to Fig. 6, the method that the data of non-volatile memory cells is written into volatile memory cell is first by the second stable state end DT set, and the object of set is to make the programmable transistorized control end of N-type connect high level, when programmable transistor T 9 and T13 employing P type FLOTOX, its control end FG should set low level or negative level, first by the second stable state end DT reset.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a Nonvolatile storage unit in high speed, it comprises bi-stable latch circuit, non-volatile memory and is written into gauge tap, this non-volatile memory comprises the first transistor, programmable transistor seconds and the 3rd transistor, and described the first transistor comprises:
Control end, accepts to store the control voltage of data;
First end, is connected to the first stable state end of bi-stable latch circuit;
The second end;
Described programmable transistor seconds comprises:
Control end, is connected to the second stable state end of bi-stable latch circuit;
First end, is connected to the second end of the first transistor;
The second end;
Described the 3rd transistor comprises:
Control end, acceptance is written into the auxiliary control voltage of data;
First end, is connected to the second end of described programmable transistor seconds;
The second end, is connected to earthing potential;
Described one end that is written into gauge tap is connected to the second stable state end of bi-stable latch circuit, and the other end is connected to the first end of programmable transistor seconds, and its control end accepts to be written into the control voltage of data.
2. Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, described Nonvolatile storage unit in high speed also comprises the first presetting bit gauge tap, one end of described the first presetting bit gauge tap is connected to the first stable state end of described bi-stable latch circuit, the other end is connected to earthing potential, and its control end is accepted the control voltage of presetting bit.
3. Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, described Nonvolatile storage unit in high speed also comprises the second presetting bit gauge tap, one end of described the second presetting bit gauge tap is connected to the second stable state end of described bi-stable latch circuit, the other end is connected to noble potential, and its control end is accepted the control voltage of presetting bit.
4. a storer, is characterized in that, it comprise a plurality of as described in as arbitrary in claim 1-3 Nonvolatile storage unit in high speed.
5. the control method of a memory inside data conversion storage, it is characterized in that, described storer comprises a plurality of Nonvolatile storage unit in high speed as described in as arbitrary in claim 1-3, and described control method comprises programmed method and loading method, and described programmed method comprises:
Transformation step, raises to meet programming by the supply voltage of described bi-stable latch circuit;
Unsettled step, closes the 3rd transistor by the 3rd transistorized control end is put to earthing potential;
Programming step, by send into the first transistor described in a high-voltage pulse conducting toward the control end of the first transistor, described programmable transistor seconds is carried out programming according to the voltage of its first end and its control end;
Described loading method comprises:
Set step, is set to noble potential by the second stable state end of described bi-stable latch circuit;
Conducting step, by setting high the 3rd transistorized control end in current potential conducting the 3rd transistor;
Be written into step, by sending into a high-voltage pulse conducting toward the control end that is written into gauge tap, be written into gauge tap, the second stable state end of described bi-stable latch circuit is discharged to earthing potential when programmable transistor seconds conducting, maintains noble potential when programmable transistor seconds is closed.
6. control method according to claim 5, is characterized in that, described set step realizes by writing " 1 " toward bi-stable latch circuit.
7. control method according to claim 5, it is characterized in that, described set step realizes by utilizing the first presetting bit gauge tap that the voltage of described the first stable state end is discharged to earthing potential, one end of described the first presetting bit gauge tap is connected to the first stable state end of described bi-stable latch circuit, the other end is connected to earthing potential, and its control end is accepted the control voltage of presetting bit.
8. control method according to claim 5, it is characterized in that, described set step realizes by utilizing the second presetting bit gauge tap that the voltage charging of described the second stable state end is set high to current potential, one end of described the second presetting bit gauge tap is connected to the second stable state end of described bi-stable latch circuit, the other end is connected to noble potential, and its control end is accepted the control voltage of presetting bit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105046158A (en) * | 2014-04-19 | 2015-11-11 | Nlt科技股份有限公司 | Control apparatus |
| CN106796814A (en) * | 2014-08-12 | 2017-05-31 | 国立研究开发法人科学技术振兴机构 | Storage circuit |
| CN115660251A (en) * | 2022-10-28 | 2023-01-31 | 广州智算信息技术有限公司 | Enterprise health degree evaluation system based on AI big data |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4651303A (en) * | 1985-09-23 | 1987-03-17 | Thomson Components--Mostek Corporation | Non-volatile memory cell |
| US5606523A (en) * | 1994-01-31 | 1997-02-25 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit |
| US6469930B1 (en) * | 2000-10-30 | 2002-10-22 | Cypress Semiconductor Corporation | Compact nonvolatile circuit having margin testing capability |
| CN1809894A (en) * | 2003-06-17 | 2006-07-26 | 皇家飞利浦电子股份有限公司 | Non-volatile static memory cell |
| US20110044109A1 (en) * | 2009-08-18 | 2011-02-24 | Ping-Chia Shih | Non-volatile static random access memory (nvsram) device |
| CN101996677A (en) * | 2009-08-26 | 2011-03-30 | 联华电子股份有限公司 | Nonvolatile static random access memory |
-
2012
- 2012-07-10 CN CN201210256531.8A patent/CN103544992A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4651303A (en) * | 1985-09-23 | 1987-03-17 | Thomson Components--Mostek Corporation | Non-volatile memory cell |
| US5606523A (en) * | 1994-01-31 | 1997-02-25 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit |
| US6469930B1 (en) * | 2000-10-30 | 2002-10-22 | Cypress Semiconductor Corporation | Compact nonvolatile circuit having margin testing capability |
| CN1809894A (en) * | 2003-06-17 | 2006-07-26 | 皇家飞利浦电子股份有限公司 | Non-volatile static memory cell |
| US20110044109A1 (en) * | 2009-08-18 | 2011-02-24 | Ping-Chia Shih | Non-volatile static random access memory (nvsram) device |
| CN101996677A (en) * | 2009-08-26 | 2011-03-30 | 联华电子股份有限公司 | Nonvolatile static random access memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105046158A (en) * | 2014-04-19 | 2015-11-11 | Nlt科技股份有限公司 | Control apparatus |
| CN105046158B (en) * | 2014-04-19 | 2019-04-05 | Nlt科技股份有限公司 | Control device |
| CN106796814A (en) * | 2014-08-12 | 2017-05-31 | 国立研究开发法人科学技术振兴机构 | Storage circuit |
| CN106796814B (en) * | 2014-08-12 | 2019-04-16 | 国立研究开发法人科学技术振兴机构 | Storage circuit |
| CN115660251A (en) * | 2022-10-28 | 2023-01-31 | 广州智算信息技术有限公司 | Enterprise health degree evaluation system based on AI big data |
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