CN103531487B - The formation method of semiconductor package - Google Patents
The formation method of semiconductor package Download PDFInfo
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- CN103531487B CN103531487B CN201310456566.0A CN201310456566A CN103531487B CN 103531487 B CN103531487 B CN 103531487B CN 201310456566 A CN201310456566 A CN 201310456566A CN 103531487 B CN103531487 B CN 103531487B
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
- H01L2224/02126—Collar structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
- H01L2224/11902—Multiple masking steps
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
A formation method for semiconductor package, comprising: provide semiconductor base, semiconductor base is formed with soldering pad layer; Form the passivation layer covering described semiconductor base and soldering pad layer surface, there is in passivation layer the first opening exposing soldering pad layer surface; First opening forms convex lower metal layer; Convex lower metal layer forms metal column; Etching removes the convex lower metal layer of metal column both sides, and bottom metal column, the edge of remaining convex lower metal layer has the undercut flaw to metal column bottom notch; Form sacrifice layer, sacrifice layer fills described undercut flaw; Form the second mask layer covering sacrifice layer, passivation layer and metal column, there is in described second mask layer the 3rd opening exposing sacrifice layer end surface; Remove described sacrifice layer along the 3rd opening, form cavity, described cavity and the 3rd open communication; Form the layer of compensation filling up described undercut flaw, the material of described layer of compensation is metal.Method of the present invention improves the reliability and stability of encapsulating structure.
Description
Technical field
The present invention relates to field of semiconductor package, particularly a kind of formation method of semiconductor package.
Background technology
Semiconductor packages refers to process wafer being obtained individual chips according to product type and functional requirement processing.Existing semiconductor packages comprises the mode such as wire bond package and Flip-Chip Using.Compared with wire bond package mode, it is high that Flip-Chip Using mode has packaging density, excellent radiation performance, the high and high reliability of I/O (I/O) port density.
Flip-Chip Using mode comparatively early arranges weld pad on chip, and utilizes the salient point be arranged on weld pad (comprising I/O weld pad) to weld with base plate for packaging, realizes chip package.Along with semicon industry is to microminiaturized future development, be formed at the density of chip on wafer increasing, accordingly, on wafer, the density of weld pad and salient point is increasing, distance between salient point is more and more less, only utilize the salient point of larger volume directly to carry out welding the problem easily occurring salient point bridge joint with base plate for packaging, namely adjacent salient point is short-circuited connection.
For solving salient point bridge joint problem, industry proposes intraconnections copper column technology (copperinterconnectposttechnology).In intraconnections copper column technology, chip is connected on base plate for packaging by copper post and the salient point be positioned on copper post.Due to the introducing of copper post, the thickness of salient point can significantly reduce, and can have less spacing between salient point, and therefore salient point bridge joint problem is weakened, and the introducing of copper post simultaneously also reduces electric capacity carrying (capacitanceload) of encapsulated circuit.
Prior art discloses a kind of chip packaging method adopting Flip-Chip Using mode, comprising:
With reference to figure 1, provide semiconductor base 100, described semiconductor base 100 is formed with soldering pad layer 101; Form the passivation layer 102 covering described semiconductor base 100 and part of solder pads layer 101 surface, described passivation layer 102 has the opening 104 exposing soldering pad layer 101 part surface; Passivation layer 102 is formed polymeric layer 103.
With reference to figure 2, form the convex lower metal layer (UnderBumpMetal, referred to as UBM) 105 covering described polymeric layer 103 and part of solder pads layer 101 surface, described convex lower metal layer 105 is as conductive layer during follow-up plating formation metal column and Seed Layer; Described convex lower metal layer 105 forms mask layer 106, there is in described mask layer 106 opening 107 exposing the convex lower metal layer 105 of soldering pad layer 101 upper part.
With reference to figure 3, adopt electroplating technology at opening 107(with reference to figure 2) the full metal of middle filling, form metal column 108; Solder layer 109 is formed on metal column 108 surface.
With reference to figure 4, remove described mask layer 106(with reference to figure 3); Remove the convex lower metal layer 105 on polymeric layer 103 surface of metal column 108 both sides, remove convex lower metal layer 105 without mask wet etching and can reduce the damage of plasma etching to metal column 108, and convex lower metal layer material remaining on polymeric layer 103 surface can be reduced; Reflux technique is carried out to solder layer, forms salient point 110.
But the reliability of the encapsulating structure of existing formation is poor, easily loses efficacy.
Summary of the invention
The problem that the present invention solves how to improve the reliability and stability of device in packaging technology.
For solving the problem, present invention also offers a kind of formation method of semiconductor package, comprising: semiconductor base is provided, described semiconductor base is formed with soldering pad layer; Form the passivation layer covering described semiconductor base and part of solder pads layer surface, there is in described passivation layer first opening on expose portion soldering pad layer surface; The sidewall of the first opening and bottom and passivation layer form convex lower metal layer; Form the first mask layer covering described convex lower metal layer, described first mask layer has the second opening of the convex lower metal layer of part on exposure first opening; Form metal column in the second opening; Remove described first mask layer; Etching removes the convex lower metal layer of metal column both sides, and bottom metal column, the edge of remaining convex lower metal layer has the undercut flaw to metal column bottom notch; The partial deactivation layer of metal column both sides forms sacrifice layer, and described sacrifice layer fills described undercut flaw; Form the second mask layer covering described sacrifice layer, passivation layer and metal column, have in described second mask layer and expose three opening of sacrifice layer away from metal column end surface; Remove described sacrifice layer along the 3rd opening, form cavity, described cavity and the 3rd open communication, and expose undercut flaw; Form the layer of compensation filling up described undercut flaw, the material of described layer of compensation is metal; Remove described second mask layer.
Optionally, the material of described sacrifice layer is all not identical with convex lower metal layer material, metal column material, the second mask material.
Optionally, the material of described sacrifice layer is SiO
2, SiN, SiON, polysilicon or amorphous carbon.
Optionally, the thickness of described sacrifice layer is more than or equal to the thickness of convex lower metal layer, and the width of sacrifice layer is greater than the width of undercut flaw.
Optionally, described layer of compensation is single or multiple lift stacked structure.
Optionally, described layer of compensation is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and the filling metal level of filling undercut flaw.
Optionally, described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Optionally, the formation process of described layer of compensation is selective chemical plating.
Optionally, described passivation layer surface is also formed with polymeric layer.
Optionally, also comprise: on metal column top surface, form diffusion impervious layer; Form salient point on the diffusion barrier.
Compared with prior art, technical scheme of the present invention has the following advantages:
After convex lower metal layer forms undercut flaw, layer of compensation is formed at undercut flaw place, the material of layer of compensation is metal, layer of compensation fills described undercut flaw, contact area between metal column and convex lower metal layer is increased and adhesion property enhancing, prevent metal column from coming off and produce gap at the contact-making surface of metal column and convex lower metal layer, improve stability and the reliability of semiconductor package.
Further, when the thickness of sacrifice layer is greater than the thickness of convex lower metal layer, the part surface of the bottom sidewall of corresponding cavity meeting exposing metal post after removing sacrifice layer, when adopting selective chemical plating to form layer of compensation, layer of compensation is made not only to fill undercut flaw, described layer of compensation also can the part surface of bottom sidewall of covering metal post, and therefore layer of compensation not only plays the effect of filling undercut flaw, and described layer of compensation also plays the effect supporting metal column and enlarge active surface.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of prior art encapsulating structure forming process;
Fig. 5 ~ Figure 15 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor package.
Embodiment
Find after deliberation, existing employing is removed without mask wet etching, easy generation undercut flaw, specifically please refer to Fig. 3 and Fig. 4, when with metal column 108 for mask, when wet etching removes the convex lower metal layer 105 on the polymeric layer 103 of metal column 108 both sides, due to isotropism when wet method is carved, when removing convex lower metal layer 105, easily over etching is produced to the convex lower metal layer 105 of the part under metal column 108, remaining convex lower metal layer 105 under metal column 108 is caved inward, forms undercut flaw 112.The existence of undercut flaw 112 can make the base section of metal column 108 unsettled, metal column 108 is reduced with the contact area of convex lower metal layer 105, metal column 108 and the poor adhesion between convex lower metal layer 105 and soldering pad layer, and the conducting resistance between metal column 108 and soldering pad layer is increased, when metal column 108 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact-making surface with convex lower metal layer, have impact on stability and the reliability of encapsulating structure.
The invention provides a kind of semiconductor package and forming method thereof, after convex lower metal layer forms undercut flaw, layer of compensation is formed at undercut flaw place, the material of layer of compensation is metal, layer of compensation fills described undercut flaw, contact area between metal column and convex lower metal layer is increased and adhesion property enhancing, prevent metal column from coming off and produce gap at the contact-making surface of metal column and convex lower metal layer, improve stability and the reliability of semiconductor package.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 5 ~ Figure 15 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor package.
First, please refer to Fig. 5, semiconductor base 200 is provided, described semiconductor base 200 is formed with soldering pad layer 201; Form the passivation layer 202 covering described semiconductor base 200 and part of solder pads layer 201 surface, there is in described passivation layer 202 first opening 204 on expose portion soldering pad layer 201 surface.
Be formed with some inside chip (not shown)s in described semiconductor base 200, described soldering pad layer 201 is connected with the inside chip in semiconductor base 200, described soldering pad layer 201 interface be connected with external chip as inside chip.
Described semiconductor base 200 is single or multiple lift stacked structure, when Semiconductor substrate 200 is multilayer lamination structure, comprises Semiconductor substrate and is positioned at least one deck dielectric layer in Semiconductor substrate.Described semiconductor substrate materials can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as GaAs etc. III-V compounds of group.
The material of described soldering pad layer 201 can be the combination of one or more in aluminium, copper, silver, gold, nickel, tungsten.Described soldering pad layer 201 is for connecting inside chip in semiconductor base and outer enclosure parts.
The material of described passivation layer 202 can be one or more in silicon nitride, silicon oxynitride, silica, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass.Described passivation layer 202 for the protection of below semiconductor device and there is the effect of electric isolation.
In the present embodiment, described passivation layer 202 is also formed with polymeric layer 203, described polymeric layer 203 is the organic materials such as epoxy resin (Epoxy), polyimides (PI), benzocyclobutene, polyphenyl oxazole.Described polymeric layer 203 is for the isolation between encapsulating structure and external environment condition.
Then, please refer to Fig. 6, at the first opening 204(with reference to figure 5) sidewall and bottom and polymeric layer 203 on form convex lower metal layer 205; Form the first mask layer 206 covering described convex lower metal layer 205, described first mask layer 206 has the second opening 207 of the convex lower metal layer 205 of part on exposure first opening.
Conductive layer when described convex lower metal layer 205 forms metal column as follow-up plating or Seed Layer, and as the adhesion layer between metal column and soldering pad layer.
Described convex lower metal layer 205 can be one or more in aluminium, nickel, copper, titanium, chromium, tantalum, gold, silver.Such as, convex lower metal layer 205 can be the double stacked structure of ambrose alloy, titanium, nickel aluminium.
The second opening 207 in described first mask layer 206 defines the position of the metal column of follow-up formation.In the present embodiment, the material of described first mask layer 206 is photoresist, forms the second opening 207 in the photoresist by exposure and developing process.
Then, please refer to Fig. 7, at the second opening 207(with reference to figure 6) middle formation metal column 208.
Form described metal column 208 and adopt electroplating technology, described metal column 208 material is copper or the copper alloy containing other metals.Other metals described can be one or more in tantalum, indium, tin, zinc, manganese, chromium or nickel.Described metal column 208 also can be other suitable metal materials.
The top surface of metal column 208 can be equal to or less than the surface of the first mask layer 206.
It should be noted that, the formation of described metal column 208 also can adopt other suitable techniques.
With reference to figure 8, remove described first mask layer 206(with reference to figure 7); Etching removes the convex lower metal layer 205 of metal column 208 both sides, and bottom metal column 208, the edge of remaining convex lower metal layer 205 has the undercut flaw 212 to metal column 208 bottom notch.
Remove described first mask layer 206 and can adopt cineration technics.
Remove the convex lower metal layer 205 of described metal column 208 both sides, adopt wet-etching technology, when adopting wet-etching technology to remove convex lower metal layer 205, to metal column 208 and polymeric layer 203(or passivation layer 202) damage less, and the residual of convex lower metal layer material can't be produced on polymeric layer 203.But due to isotropic during wet etching, thus remove metal column 208 both sides passivation layer 202 on convex lower metal layer time, under metal column 208, remaining convex lower metal layer 205 can produce undercut flaw 212.The existence of undercut flaw 212, metal column 208 can be reduced with the contact area of remaining convex lower metal layer 205, make metal column 208 and the poor adhesion between remaining convex lower metal layer 205 and soldering pad layer, and the conducting resistance between metal column 208 and soldering pad layer is increased, when metal column 208 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact-making surface with convex lower metal layer, have impact on stability and the reliability of encapsulating structure.
Then with reference to figure 9, the partial deactivation layer 202 of metal column 208 both sides forms sacrifice layer 213, described sacrifice layer 213 fills described undercut flaw 212(with reference to figure 8).
Described sacrifice layer 213 is follow-up removes the cavity being formed and expose undercut flaw, then can be formed the layer of compensation of filling undercut flaw by selective chemical plating.
The material of described sacrifice layer 213 and convex lower metal layer 205 material, metal column 208 material, polymeric layer 203 material are all not identical with the second mask material of follow-up formation.When follow-up removal sacrifice layer 213 forms cavity, sacrifice layer 213 is made to have high etching selection ratio relative to metal level 205 material, metal column 208 material, polymeric layer 203 material and the second mask layer.In the embodiment of the present invention, the existence of sacrifice layer 213, after making follow-up formation second mask layer, sacrifice layer 213 can be removed by the 3rd opening in the second mask layer, and then form the cavity of undercut flaw 212 or convex lower metal layer 205 sidewall, due to the metal column sidewall on metal column 208 top surface and cavity, and the convex lower metal layer 205 outside cavity is all covered by the second mask layer, thus the passage consisted of the 3rd opening and cavity optionally can form the layer of compensation of filling undercut flaw 212 on the sidewall of convex lower metal layer 205, improve the precision that bottom metal layer is formed.
The material of described sacrifice layer 213 can be SiO
2, SiN, SiON, polysilicon or amorphous carbon.The material of sacrifice layer 213 described in the present embodiment is SiO
2.
The thickness of described sacrifice layer 213 equals the thickness of convex lower metal layer 205, the width of described sacrifice layer 213 is greater than undercut flaw 212(with reference to figure 8) width, during follow-up formation the second mask layer, make the second mask layer can the sidewall of covering metal post 208, the 3rd opening in second mask layer exposes the surface of one end away from metal column of sacrifice layer, and the 3rd opening can not expose the sidewall surfaces of metal column 208.
In other embodiments of the invention, the thickness of described sacrifice layer is greater than the thickness (or height of undercut flaw) of convex lower metal layer, make the partial sidewall of the bottom of sacrifice layer covering metal post, the layer of compensation of follow-up formation is except filling undercut flaw, the partial sidewall of all right covering metal column bottom, the contact area of the bottom of metal column and convex lower metal layer is increased, improves adhesiveness between the two.
The formation method of described sacrifice layer 213 is: form sacrificial material layer on the sidewall of described convex lower metal layer 205, metal column 208 sidewall and surface and polymeric layer 203 surface; Without sacrificial material layer described in mask etching, form sacrifice layer 213 at the sidewall of convex lower metal layer 205.
In other embodiments of the invention, the forming process of described sacrifice layer 213 can also be: form the sacrificial material layer covering described metal column 208 and polymeric layer 203 surface; Return the described sacrificial material layer of etching, make the thickness of remaining sacrificial material layer be more than or equal to the thickness of convex lower metal layer 205; Form mask layer, the sacrificial material layer of the top of described mask layer covering metal post 208 and sidewall surfaces and the some residual near convex lower metal layer 205 sidewall; Remove not by the remaining sacrificial material layer that mask layer covers, form sacrifice layer 213.
Then, please refer to Figure 10, formed and cover described sacrifice layer 213, passivation layer 202(polymeric layer 203) and the second mask layer 214 of metal column 208, there is in described second mask layer 214 the 3rd opening 215 away from metal column 208 end surface of exposure sacrifice layer 213.
The material of described second mask layer 214 is photoresist, forms the 3rd opening 215 by exposure and developing process in the second mask layer 214.
Described second mask layer 214 covers surface and the sidewall of described metal column, follow-up after removal sacrifice layer 213, and selective chemical depositing process can be adopted to form the layer of compensation of filling undercut flaw.
Then, please refer to Figure 11, remove described sacrifice layer 213(with reference to Figure 10 along the 3rd opening 215), form cavity 216, described cavity 216 is communicated with the 3rd opening 215, and exposes undercut flaw 212.
Remove described sacrifice layer 213 and adopt wet-etching technology, in the present embodiment, adopt hydrofluoric acid solution to remove described sacrifice layer 213.
After removal sacrifice layer 213, form cavity 216, described cavity 216 exposes the sidewall of undercut flaw 212 or convex lower metal layer 205.
In other embodiments of the invention, when the thickness of described sacrifice layer 213 is greater than the thickness of convex lower metal layer 205, described cavity also exposes the partial sidewall of the bottom of metal column 208.
Then, please refer to Figure 12, along the 3rd opening 215 and cavity 216(with reference to Figure 11) formed and fill up described undercut flaw 212(with reference to Figure 11) layer of compensation 217, the material of described layer of compensation 217 is metal.
The material of described layer of compensation 217 can be one or more in nickel, titanium, tantalum, aluminium, tungsten, copper, silver, tin, platinum, gold.
The technique forming described layer of compensation 217 is selective chemical plating, and selective chemical plating can optionally form metal level (layer of compensation 217) at metallic surface.In other embodiments of the invention, suitable technique also can be adopted to form described layer of compensation.
Before carrying out selective chemical plating, also comprise oil removing and activating process.Described oil removing process is for removing oily matter and the oxide layer of convex lower metal layer 205 sidewall surfaces, convex lower metal layer 205 sidewall surfaces is made to keep cleannes, oil removing process can adopt acid solution to clean, in other embodiments, also oil removing process can not be comprised, aforementioned remove sacrifice layer time, can proper extension remove time, convex lower metal layer 205 surface is cleaned; After carrying out oil removing process, carry out activating process, to form nuclearing centre when being used for chemical plating in the sidewall surfaces of convex lower metal layer 205, described activating process can be zinc activating process.
Described layer of compensation 217 can be single or multiple lift stacked structure.
In the present embodiment, described layer of compensation 217 is double stacked structure, described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and the filling metal level of filling undercut flaw, described infiltration metal level is for the adhesion improving described convex lower metal layer and fill between metal level, and can as diffusion impervious layer, the metallic atom phase counterdiffusion preventing convex lower metal layer and fill in metal level.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
In the embodiment of the present invention, by forming layer of compensation 217, described layer of compensation 217 fills undercut flaw, the contact area of metal column 208 and convex lower metal layer 205 is increased, improve adhesiveness, and the material of layer of compensation 217 is metal, reduce the conducting resistance between metal column 208 and soldering pad layer.
Then, please refer to Figure 13 and Figure 14, remove described second mask layer 214(and please refer to Figure 12); Metal column 208 top surface forms diffusion impervious layer 209; Diffusion impervious layer 209 is formed salient point 211.
Remove described second mask layer 214 and adopt cineration technics or other suitable technique.
Described diffusion impervious layer 209 is for preventing the Metal Phase counterdiffusion in metal column 208 and salient point 211, and the adhesiveness improved between salient point 211 and metal column, the material of described diffusion impervious layer 209 is one or more in nickel, tin, tin lead, gold, silver, palladium and indium.
The material of described salient point 211 can be one or more in the metals such as tin, Xi Yin, tin lead, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony.After described diffusion impervious layer 209 forms solder layer, reflux technique is carried out to solder layer, form salient point.
It should be noted that, the formation of described diffusion impervious layer 209 and solder layer after formation metal column 208, can be formed before removing the first mask layer.
In other embodiments of the invention, please refer to Figure 15, when the thickness of sacrifice layer is greater than the thickness of convex lower metal layer 205, the part surface of the bottom sidewall of corresponding cavity meeting exposing metal post 208 after removing sacrifice layer, therefore when adopting selective chemical plating to form layer of compensation 217, layer of compensation 217 is made not only to fill undercut flaw, described layer of compensation 217 also can the part surface of bottom sidewall of covering metal post 208, therefore layer of compensation 217 not only plays the effect of filling undercut flaw, described layer of compensation 217 also plays the effect supporting metal column 208 and enlarge active surface, when metal column 108 is when being subject to the stress of outside pressure or inside, metal column is made to be not easy to come off from convex lower metal layer 205 or metal column 108 not easily produces gap with the contact-making surface of convex lower metal layer 205.
The semiconductor package that said method is formed, please refer to Figure 14, comprise: semiconductor base 200, described semiconductor base 200 has soldering pad layer 201, cover the passivation layer 202 of described semiconductor base 200 and part of solder pads layer 201, there is in described passivation layer 202 first opening of expose portion soldering pad layer 201.
Be positioned at the metal column 208 of the first opening;
Convex lower metal layer 205 between metal column 208 and soldering pad layer 201, the edge of described convex lower metal layer 205 has the undercut flaw to metal column 208 bottom notch;
Fill up the layer of compensation 217 of described undercut flaw, the material of described layer of compensation 217 is metal.
Concrete, the width of described layer of compensation 217 is equal to or greater than the width of described undercut flaw, and the thickness of described layer of compensation 217 equals the thickness of convex lower metal layer 205.
In other embodiments of the invention, with reference to Figure 15, described layer of compensation 217 thickness is greater than the thickness (being greater than the height of undercut flaw) of convex lower metal layer 205, and layer of compensation 217 covers the partial sidewall bottom described metal column 208.
The material of layer of compensation 217 is identical with the material of convex lower metal layer 205 or not identical, and the material of described layer of compensation 217 is identical with metal column 208 material or not identical.
Described layer of compensation 217 is single or multiple lift stacked structure.
In a specific embodiment, described layer of compensation 217 at least comprises the infiltration metal level contacted with convex lower metal layer.
In another specific embodiment, described layer of compensation 217 is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and the filling metal level of filling undercut flaw.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Also comprise: be positioned at the polymeric layer 203 on passivation layer 202.
Also comprise: be positioned at the diffusion impervious layer 209 on surface, metal column top 208, the salient point 211 be positioned on diffusion impervious layer 209.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for semiconductor package, is characterized in that, comprising:
Semiconductor base is provided, described semiconductor base is formed with soldering pad layer;
Form the passivation layer covering described semiconductor base and part of solder pads layer surface, there is in described passivation layer first opening on expose portion soldering pad layer surface;
The sidewall of the first opening and bottom and passivation layer form convex lower metal layer;
Form the first mask layer covering described convex lower metal layer, described first mask layer has the second opening of the convex lower metal layer of part on exposure first opening;
Form metal column in the second opening;
Remove described first mask layer;
Etching removes the convex lower metal layer of metal column both sides, and bottom metal column, the edge of remaining convex lower metal layer has the undercut flaw to metal column bottom notch;
The partial deactivation layer of metal column both sides forms sacrifice layer, and described sacrifice layer fills described undercut flaw;
Form the second mask layer covering described sacrifice layer, passivation layer and metal column, have in described second mask layer and expose three opening of sacrifice layer away from metal column end surface;
Remove described sacrifice layer along the 3rd opening, form cavity, described cavity and the 3rd open communication, and expose undercut flaw;
Form the layer of compensation filling up described undercut flaw, the material of described layer of compensation is metal;
Remove described second mask layer.
2. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is all not identical with convex lower metal layer material, metal column material, the second mask material.
3. the formation method of semiconductor package as claimed in claim 2, it is characterized in that, the material of described sacrifice layer is SiO
2, SiN, SiON, polysilicon or amorphous carbon.
4. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, the thickness of described sacrifice layer is more than or equal to the thickness of convex lower metal layer, and the width of sacrifice layer is greater than the width of undercut flaw.
5. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, described layer of compensation is single or multiple lift stacked structure.
6. the formation method of semiconductor package as claimed in claim 5, it is characterized in that, described layer of compensation is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and the filling metal level of filling undercut flaw.
7. the formation method of semiconductor package as claimed in claim 6, it is characterized in that, described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
8. the formation method of semiconductor package as claimed in claim 5, it is characterized in that, the formation process of described layer of compensation is selective chemical plating.
9. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, described passivation layer surface is also formed with polymeric layer.
10. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, also comprise: after described second mask layer of removal or after formation metal column and before removal first mask layer, metal column top surface forms diffusion impervious layer; Form salient point on the diffusion barrier.
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| CN106334506B (en) * | 2016-10-25 | 2019-08-02 | 新奥环保技术有限公司 | A kind of supercritical reaction device and supercritical processing system |
| CN113725165B (en) * | 2021-08-30 | 2023-07-11 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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|---|---|---|---|---|
| US6541366B1 (en) * | 2002-01-08 | 2003-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a solder bump adhesion bond to a UBM contact layer |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
| CN103219305A (en) * | 2013-04-18 | 2013-07-24 | 南通富士通微电子股份有限公司 | Salient point bottom protection structure |
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| TWI298204B (en) * | 2005-11-21 | 2008-06-21 | Advanced Semiconductor Eng | Structure of bumps forming on an under metallurgy layer and method for making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541366B1 (en) * | 2002-01-08 | 2003-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a solder bump adhesion bond to a UBM contact layer |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
| CN103219305A (en) * | 2013-04-18 | 2013-07-24 | 南通富士通微电子股份有限公司 | Salient point bottom protection structure |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |