CN103491336B - The LVDS video signal of single LINK is converted to MIPI video signal method - Google Patents

Abstract

The LVDS video signal that the invention discloses a kind of single LINK is converted to MIPI video signal method, and the LVDS video signal including: step 1, to single LINK is received demodulation, produces LVDS parallel demodulation data and LVDS pixel clock；Step 2, parallel demodulation data carrying out video decoding, generate LVDS video source data and LVDS video source synchronizing signal, LVDS pixel clock is converted into LVDS video source pixel clock；Step 3, with LVDS video source pixel clock LVDS video source signal sampled and cache, LVDS video source signal is converted to rgb video signal；LVDS video source signal is converted to the process of rgb video signal and includes: generate rgb video clock, the frequency making rgb video clock is identical with LVDS video source pixel clock, with rgb video clock read output signal from buffer area, isolate rgb video source data and rgb video synchronizing signal, Sequential output respectively, thus form rgb video signal together with rgb video clock；Step 4, rgb video signal is converted to MIPI video signal.

Description

The LVDS video signal of single LINK is converted to MIPI video signal method

Technical field

The present invention relates to display field and the field tests of liquid crystal module, the LVDS video in particular to a kind of single LINK is believed Number be converted to MIPI video signal method.

Background technology

Liquid crystal display module (Liquid Crystal Display Module, hereinafter referred to as liquid crystal module) is liquid crystal Showing the critical component that equipment can normally show, it is made up of liquid crystal display screen, backlight original paper, display process chip and circuit.Liquid crystal mould Group precise structure, processing procedure are complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need by special liquid crystal mould Group test device produces various test video signals and is input in liquid crystal module display, strictly, comprehensively detects its display effect. Its display interface of common liquid crystals module on TV, display product and internal display at present processes circuit and uses LVDS (Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module What test device exported the most accordingly is that LVDS video signal is to realize the test of module.Due to common liquid crystals module production time For a long time, yield big, therefore its module test device uses the most in a large number.

Along with people constantly pursue more fine definition, display effect more true to nature on mobile device, portable equipment, commonly Liquid crystal module the most gradually cannot meet this needs.Then occur in that on market that one has ultrahigh resolution and very-high solution The novel liquid crystal module of density meets the demand of people.The interface of this liquid crystal module and internal display process circuit and use MIPI (Mobile Industry Processor Interface moves Industry Processor Interface) signaling interface.This interface is Formulated by the MIPI alliance including the company such as including ARM, Samsung, Intel, it is therefore an objective to mobile, internal each group of portable equipment The part such as nuclear interface standardizing such as photographic head, display screen, processor and opening each other, thus improve performance, reduce cost and Power consumption.MIPI interface can not only support ultrahigh resolution and refresh rate, and has farther transmission range, and more preferable electromagnetism is held concurrently Capacitive, the liquid crystal module thus with MIPI interface has become development trend.

But the test device of MIPI liquid crystal module needs to export same MIPI and tests signal, but existing common liquid crystals Module test device does not has this function, and common liquid crystals module also continues to produce, and its test device is also introduced into generation The cycle of changing will be continuing with.Although module manufacturer also produces MIPI liquid crystal module, but in order to protect investment, reduction to produce into This, it is impossible to eliminate existing equipment, again make a big purchase in large quantities costliness MIPI module Special testing device.In order to enable in the short term The production in enormous quantities MIPI liquid crystal module of low cost also ensures its yields, the most still reuse on a large scale existing commonly Module test device.

Accordingly, it would be desirable to the LVDS video signal of single LINK can be converted to MIPI video signal by a kind of technical scheme, make general MIPI module can be tested by logical liquid crystal module testing device by this conversion equipment.

Summary of the invention

The LVDS video signal that it is an object of the invention to provide a kind of single LINK is converted to MIPI video signal method, its Have simple to operate, detection efficiency is high, the feature of low cost.

For achieving the above object, the LVDS video signal of the single LINK designed by the present invention is converted to MIPI video signal side Method, it is characterized in that, comprises the following steps:

Step 1, LVDS video signal to single LINK are received demodulation, produce LVDS parallel demodulation data and LVDS picture Element clock；

Step 2, described parallel demodulation data are carried out video decoding, generate LVDS video source signal, described LVDS video Source signal includes LVDS video source data and LVDS video source synchronizing signal, and described LVDS pixel clock is converted into LVDS video Source pixel clock；

Step 3, described LVDS video source signal is sampled and cached with described LVDS video source pixel clock, by institute State LVDS video source signal and be converted to rgb video signal；Described LVDS video source signal is converted to the process bag of rgb video signal Include: generating rgb video clock, the frequency making described rgb video clock is identical, with described with described LVDS video source pixel clock Rgb video clock read output signal from buffer area, isolates rgb video source data and rgb video synchronizing signal, and order is defeated respectively Go out, thus form described rgb video signal together with described rgb video clock；

Step 4, described rgb video signal is converted to MIPI video signal.

Preferably, the LVDS video signal of described single LINK includes that LVDS receives clock and LVDS data, described LVDS number According to by LVDS data bus transmission, described LVDS data/address bus includes that some holding wires, every holding wire transmit serial code Signal；Described MIPI video signal shows module for the MIPI of 4LANE type.

Preferably, before in described step 1, video signal to single LINK is received demodulation, according to list to be received The characteristic of the LVDS video signal of LINK, arranges LVDS video signal decoding parametric, synchronous mode control parameter；Receive MIPI to regard Frequently conversion configurations parameter, the configuration operation and the MIPI that perform MIPI conversion process show module initialization operation；According to described LVDS video signal decoding parametric produces LVDS coding standard control signal, LVDS video color range bit wide control signal；According to institute State synchronous mode and control parameter generation LVDS synchronous mode control signal；Produce according to described MIPI video conversion configuration parameter MIPI transition initialization order and MIPI module initialization command.

Preferably, the process being received demodulating to the video signal of single LINK in described step 1 includes: to the institute received State the serial code signal in the LVDS video signal of single LINK be terminated respectively, demodulate, dynamic calibration, produce LVDS parallel Demodulating data；The process of described termination includes: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with Postemphasis, signal damping and reconstruction；The process of described demodulation includes: described LVDS is received clock and is demodulated, produce demodulation Enabling signal, the serial code signal of described LVDS data is individually demodulated to parallel data respectively simultaneously, described LVDS receives Clock is demodulated into described LVDS pixel clock simultaneously.

Preferably, the process in described step 2, described parallel demodulation data being carried out video decoding includes: compile according to LVDS Code standard control signal and LVDS video color range bit wide control signal, by LVDS pixel clock to described LVDS parallel demodulation number The operation of sequential logic according to this is decoded, and recovers LVDS video source synchronizing signal and LVDS video source data signal.

Preferably, after described step 3 forms described rgb video signal, receive described LVDS synchronous mode control signal, Detect whether described rgb video signal is Low level effective, if described rgb video signal is Low level effective, by described RGB Signal exports；If described rgb video signal to be high level effective, described rgb signal is transferred to described after Low level effective Rgb signal exports, and sends MIPI video conversion enabling signal during output.

Preferably, configuration operation and the MIPI display module initialization operation of described execution MIPI conversion process includes receiving Perform the configuration operation of MIPI conversion process after MIPI transition initialization order, confirm that configuration operation performs after completing described again MIPI module initialization command, and MIPI module initialization command is transferred to MIPI display module with the form of MIPI order, Complete module initialization operation, send MIPI video conversion afterwards when receiving described MIPI video conversion enabling signal and start life Order.

Preferably, during being exported by described rgb signal, the process carrying out described rgb video clock includes: to institute The phase place stating rgb video clock is adjusted so that it is effective edge edge can be in the immediate vicinity of described rgb video source data, then Carry out de-jitter, when described rgb signal exports, compare effective edge and the institute of the described rgb video clock after Key dithering State the deviation between rgb video source data center, and utilize time delay to do trim process so that effective edge of described rgb video clock Alignment is remained with described rgb video source data center.

Preferably, the process that described rgb video signal is converted in described step 4 MIPI video signal includes: perform When receiving the startup of described MIPI video conversion after the configuration operation of MIPI conversion process and MIPI display module initialization operation Start during order that the described rgb video signal received is converted to MIPI video signal transmission and show module to described MIPI.

The beneficial effects of the present invention is:

(1) the LVDS video signal of single LINK can be converted to MIPI video signal by the present invention.The present invention is by arranging, right The different qualities such as the multiple color range of LVDS video signal, transmission means, coded system all can well mate.

(2) the LVDS video signal of convertible 6,8,10 color ranges of the present invention, convertible based on VESA and JEIDA biography The LVDS signal of defeated coding, can change the LVDS transmission mode of single LINK, it is adaptable to the MIPI liquid crystal mould of 4LANE type Group.

(3) present invention the most manually changes toggle switch state and is i.e. applicable to different LVDS video letter Number；Need to receive MIPI video conversion configuration parameter by jtag interface before the different MIPI liquid crystal module of application.

(4) present invention can be achieved with described repertoire with single FPGA (field programmable logic array) chip；FPGA It is a kind of programmable semicustom chip, the synchronization process of multilink video data, Parallel transformation can be realized, can reach higher Performance, not only working stability, realize easily, and low price, it is to avoid the design caused because using various special chips The problems such as complexity, poor stability, design cost are high.

(5) video resolution that the present invention supports is higher, and not only integrated level is high, and reliable operation, capacity of resisting disturbance are strong, and Simple to operate, economical and practical, the detection efficiency of MIPI liquid crystal module can not only be promoted, reduce its equipment cost and production cost, Also will further improve the universal of MIPI display device.

Accompanying drawing explanation

Fig. 1 is the flow chart of the present invention；

Fig. 2 is block diagram of the present invention；

Fig. 3 a is LVDS video reception unit and the LVDS video signal decoding unit of single LINK of single LINK in Fig. 2 Circuit block diagram；

Fig. 3 b is rgb video signal converting unit in Fig. 2, MIPI video signal converting unit and video conversion dispensing unit Circuit block diagram；

Fig. 4 is the circuit diagram of rgb video modular converter in Fig. 3 b；

Fig. 5 is the signal graph that the LVDS video signal of single LINK is converted to rgb video signal；

In figure: 1. the LVDS video reception unit of single LINK, 1-1.LVDS video signal interface, 1-2.LVDS video Signal receiving end connection module, 1-3.LVDS clock signal demodulation module, 1-4.LVDS demodulated data signal module, 1-5.LVDS solves Transfer state calibration module；

2. the LVDS video signal decoding unit of single LINK, 2-1.LVDS video data decoding module, 2-2.LVDS video Synchronizing signal decoder module；

3.RGB video signal converting unit, 3-1.RGB video clock generation module, 3-2.RGB video conversion module, 3- 2-1.LVDS signal sampling, 3-2-2.DC-FIFO caches, 3-2-3.RGB signal sampling, and the output of 3-3.RGB video clock adjusts Module, 3-4.RGB video signal output module；

4.MIPI video signal converting unit, 4-1.MIPI register module, 4-2.MIPI video signal modular converter, 4- 3.MIPI liquid crystal display module connector；

5. video conversion dispensing unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configures Module.

Detailed description of the invention

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

As shown in Figures 1 to 5, the LVDS video signal of a kind of single LINK of the present invention is converted to MIPI video signal method, Comprise the following steps:

The LVDS video signal of single LINK includes that LVDS receives clock and LVDS data, and LVDS data are by LVDS data/address bus Transmission, LVDS data/address bus includes that some root holding wires, every holding wire transmit serial code signal；MIPI video signal is used Module is shown in the MIPI of 4LANE type.

LVDS video signal refers to the general name of the signal with LVDS electrical characteristic for characterizing, and has different video pixel color The combination of the signal of string of coding standard, signal transmission link mode is transmitted on rank, signal.The LVDS of single LINK to be received Video signal characteristic includes: the color range of the LVDS video source pixel (being made up of tri-kinds of color components of RGB) of single LINK to be received Can have 6 or 8 or 10, each pixel is all according to VESA or the JEIDA coding standard of LVDS transmission of video, by string and compile Code becomes the data signal line of one group of homochromy component level number corresponding 3 or 4 or 5 to form one group of data/address bus, with LVDS's Electrical form is transmitted.

The characteristic of the LVDS video signal according to single LINK to be received, arrange LVDS video signal decoding parametric, with Step mode controls parameter；Receiving MIPI video conversion configuration parameter, the configuration operation and the MIPI that perform MIPI conversion process show Module initialization operation；LVDS coding standard control signal, LVDS video color range is produced according to LVDS video signal decoding parametric Bit wide control signal；Control parameter according to synchronous mode and produce LVDS synchronous mode control signal；Join according to MIPI video conversion Put parameter and produce MIPI transition initialization order and MIPI module initialization command.

LVDS video signal decoding parametric includes: LVDS video signal transmission coding standard has VESA and JEIDA；LVDS regards Frequently the pixel color component level in source is wide 6,8,10；Synchronous mode controls parameter and includes that high level is effectively and Low level effective； MIPI video conversion configuration parameter includes: the signal sequence of MIPI modular converter, transmission frequency, group pack mode, MIPI liquid crystal Show the display sequential of module, time delay Synchronization Control, initialization directive.Opened by the manual dial-up in video conversion dispensing unit 5 Close 5-1 and LVDS video signal decoding parametric is set, regarded according to the type reception MIPI of MIPI display module by jtag interface 5-2 Frequently conversion configurations parameter.

The configuration operation and the MIPI display module initialization operation that perform MIPI conversion process include that video conversion configuration is single MIPI video conversion configuration module 5-3 in unit 5 performs the configuration of MIPI conversion process after receiving MIPI transition initialization order Operation, confirms that configuration operation performs MIPI module initialization command after completing again, and by MIPI module initialization command with MIPI The form of order is transferred to MIPI and shows module, completes module initialization operation, configures module 5-3 when MIPI video conversion afterwards Receive when the MIPI video conversion enabling signal that rgb video signal converting unit 3 transmits to MIPI video signal converting unit 4 Send MIPI video conversion and start order.

Reception MIPI transition initialization order is first write MIPI depositor mould by MIPI video conversion configuration module 5-3 one by one In block 4-1, after often writing an order, read the state value of MIPI register module 4-1, to guarantee that order has performed, when really Recognize and write MIPI display module after MIPI video signal modular converter 4-2 completes configuration and starts normal work again and initialize and deposit Device order, MIPI video signal modular converter 4-2 is then converted into the form of MIPI order and is transferred to MIPI display module, complete Become module initialization operation.

Before the LVDS video signal receiving single LINK, complete decoding parametric, the configuration of conversion parameter and produce corresponding control Signal processed.

Step 1, LVDS video signal to single LINK are received demodulation, produce LVDS parallel demodulation data and LVDS picture Element clock；

The process being received demodulating to the LVDS video signal of single LINK in step 1 includes: to the single LINK's received Serial code signal in LVDS video signal is terminated respectively, demodulates, dynamic calibration, produces LVDS parallel demodulation data； Termination process include: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with postemphasis, signal delay Punching and reconstruction；The process of demodulation includes: LVDS is received clock and is demodulated, and produces demodulation and enables signal, to LVDS data Serial code signal is individually demodulated to parallel data respectively simultaneously, and LVDS receives clock and is demodulated into LVDS pixel clock simultaneously.

The LVDS video signal of single LINK is by the LVDS video signal in the LVDS video reception unit 1 of single LINK Interface 1-1 receives, and is then terminated by LVDS video reception termination module 1-2.To LVDS video signal termination Purpose is: guarantee that the LVDS video signal quality of single LINK received is high, noiseless.The process of termination includes: single receiving ESD (Electro Static Discharge static discharge) protective treatment is carried out to eliminate wink before the LVDS video signal of LINK Between strong discharge impact interference, then carry out common-mode noise Filtering Processing with suppression line noise, improve anti-electromagnetic interference capability. The impedance matching that is terminated when a signal is received processes the distortion caused to eliminate signal to transmit, and eliminates the attached of signal the most further Adding interference, equalize signal simultaneously and postemphasis process, the signal attenuation caused because of loss with elimination.The most again Signal damping is amplified, and reconstructs the LVDS video signal of high-quality single LINK through the judgement of reference level.

LVDS clock signal demodulation module 1-3 receives clock to the LVDS of the LVDS video signal of the single LINK by termination Through being demodulated, LVDS data are demodulated through LVDS demodulated data signal module 1-4.LVDS is received clock demodulator mistake Journey includes: LVDS receives clock and carries out frequency multiplication operation and high-frequency clock conversion process after speed buffering, produce and LVDS number According to the LVDS demodulation clock of same frequency and demodulate gating signal with LVDS reception clock with LVDS pixel clock, the LVDS of frequency, and Export in high-frequency clock network, make them have the lowest delay and jitter, the strongest driving force, it is ensured that can be reliable and stable LVDS data are demodulated.The dynamic calibration of clock jitter removing it is also carried out while clock carries out frequency multiplication operation LVDS is received, Think what subsequent operation generation was not affected by input jiffer, stable frequency-doubled signal.

The LVDS data demodulation process of single LINK is included: to each figure place in the LVDS serial data bus of single LINK According to demodulation independently, by each LVDS data signal its Phase delay half-bit position week after speed buffering inputs Phase so that what LVDS demodulation clock can be correct at the center of each LVDS data bit samples this data value, and according to demodulation It is periodically blocked bunchiness data by gating signal, then does string with LVDS pixel clock and turn and process and obtain this LVDS The parallel demodulation data of signal, are merged into LVDS demodulating data by each LVDS demodulating data.Each LVDS holding wire is equal The demodulation run simultaneously so that each holding wire the most all will not interfere regardless of data and cause demodulating mistake.To LVDS number According to being demodulated being also carried out data dithering removal calibration simultaneously, do not affected by input jiffer to produce, reliable and stable demodulation number According to.Phase delay process in data input is controlled by LVDS data stream phase alignment signal all the time, when demodulation clock and When phase place between LVDS data has deviation, phase alignment signal makes itself and phase deviation on the basis of data delay half period Contrary delay adjusts so that data center all the time with the sampling of demodulation clock along keeping alignment, it is ensured that correctly sample data. While demodulation gating signal carries out blocking serial data, moved calibration signal by the bit of byte-aligned and control, make The start bit by the parallel data of segmentation move on next serial data position.

For guaranteeing that bits per inch, according to correctness during demodulation and reliability, receives clock to LVDS and each LVDS data exists Demodulation carries out dynamic calibration by LVDS demodulation dynamic calibration module 1-5 respectively.

Step 2, parallel demodulation data are carried out video decoding, generate LVDS video source signal, LVDS video source signal bag Including LVDS video source data and LVDS video source synchronizing signal, LVDS pixel clock is converted into LVDS video source pixel clock；

The process that parallel demodulation data carry out in step 2 video decoding includes: during by LVDS pixel clock by the overall situation Clock path integration becomes LVDS video source pixel clock.LVDS audio video synchronization in the LVDS video signal decoding unit 2 of single LINK Signal decoder module 2-2 and LVDS video data decoding module 2-1 regard according to LVDS coding standard control signal and LVDS respectively LVDS parallel demodulation data are solved with the operation of sequential logic by color range bit wide control signal frequently by LVDS pixel clock Code, recovers LVDS video source synchronizing signal and LVDS video source data signal.

Owing to LVDS video signal transmission coding standard (VESA or JEDIA standard) all supports 6 bits, 8 bits, 10 bits The coding of pixel color range, its LVDS video synchronization signal is also together encoded with video pixel data, and its respective coding rule It is then unique, therefore can get unique LVDS according to LVDS video standard control signal and LVDS video bit wide control signal Decoded video data, is thus decoded with the operation of sequential logic demodulating data, recovers LVDS video source synchronizing signal With LVDS video source data signal.LVDS video source synchronizing signal includes video level line synchronising signal (Hsync), video vertical Field sync signal (Vsync), video data useful signal (DE).

Step 3, with LVDS video source pixel clock LVDS video source signal sampled and cache, by LVDS video source Signal is converted to rgb video signal；LVDS video source signal is converted to the process of rgb video signal and includes: when generating rgb video Clock, the frequency making rgb video clock is identical with LVDS video source pixel clock, reads letter with rgb video clock from buffer area Number, isolate rgb video source data and rgb video synchronizing signal, respectively Sequential output, thus shape together with rgb video clock Become rgb video signal；

Rgb video modular converter 3-1 in rgb video signal converting unit 3 is by LVDS video source synchronizing signal and LVDS Video source data is combined into parallel data according to the form of " data, synchronizing signal ", samples also with LVDS video source pixel clock Write in DC-FIFO and cache.Rgb video clock generation module 3-2 produces the RGB with LVDS video source pixel clock same frequency Video clock, samples in LVDS signal sampling 3-2-1 with LVDS video source pixel clock, and writes DC-FIFO caching 3-2-2 Middle caching；Rgb signal sampling 3-2-3 rgb video clock reads parallel data, and isolates rgb video source data and RGB regards Vertical synchronizing signal, thus complete conversion process.

When with DC-FIFO caching 3-2-2 caching, need to cache certain data volume with canceling DC-FIFO id reaction Postpone and LVDS signal transfer rate occurs that the read-write speed caused by fluctuation has fine difference (this fluctuation only causes current video The data transmission rate change of row, at line blanking period without impact).

After forming rgb video signal, receiving LVDS synchronous mode control signal, whether detection rgb video signal is low electricity Flat effective, if rgb video signal is Low level effective, rgb signal is exported；If it is effective that rgb video signal is high level, After rgb signal is transferred to Low level effective, rgb signal is exported, during output, send MIPI video conversion enabling signal.

During being exported by rgb signal, export what rgb video clock was carried out by adjusting module 3-3 with rgb video clock Process, including: the phase place of rgb video clock is adjusted so that it is effective edge is attached along the center that can be in rgb video source data Closely, then carrying out de-jitter, when rgb signal exports, the effective edge and the RGB that compare the rgb video clock after Key dithering regard Frequently the deviation between source data center, and utilize time delay to do trim process so that effective edge of rgb video clock and rgb video source Data center remains alignment.

Owing to rgb video data and rgb video clock synchronize, therefore by the rgb video clock phase delay half of input Clock cycle exports clock signal as RGB so that it is effectively edge can be in the immediate vicinity of rgb video data, so that it is guaranteed that after Continuous conversion operation is correctly sampled RGB data by this clock, and this signal carries out de-jitter more afterwards, and is regarded by RGB Frequently the high speed signal interface assembly of signal output module 3-4 outputs it, with guarantee this output clock have higher stability and Preferably signal quality.

When starting to export RGB data and synchronizing signal, produce MIPI video conversion after postponing some rgb video clocks and open Dynamic signal, starts follow-up MIPI video signal converting unit 4 and works, this is done to make MIPI video signal converting unit 4 receive normal video data at the very start, improve the reliability of MIPI conversion.

Step 4, rgb video signal is converted to MIPI video signal.

The process that rgb video signal is converted in step 4 MIPI video signal includes: MIPI video conversion configuration module After 5-3 performs configuration operation and the MIPI display module initialization operation of MIPI conversion process, MIPI video conversion configuration module 5-3 sends MIPI video conversion and starts order, MIPI video signal converting unit 4 after receiving MIPI video conversion enabling signal In MIPI register module 4-1 receive MIPI video conversion start order after, MIPI video signal modular converter 4-2 start by The rgb video signal received is converted to MIPI video signal, is transferred to MIPI by MIPI liquid crystal display module connector and shows Show module.

Transformation process includes: when proceeding by MIPI conversion configurations, and MIPI video signal modular converter 4-2 is according to write MIPI register command carry out configuration operation, these MIPI register command include: MIPI conversion configurations order, MIPI show Module initialization command, MIPI conversion and control order；After configuration is complete, show at the beginning of module according to the MIPI of write depositor Beginningization is ordered, and MIPI video signal modular converter 4-2 converts such commands into MIPI command signal respectively and is transferred to MIPI The MIPI that liquid crystal display module connector is connected shows module, makes MIPI display module carry out initialization operation；Work as afterwards During MIPI video conversion control command write MIPI register module 4-1, MIPI video signal modular converter 4-2 is by input Rgb video signal is converted to MIPI video signal transmission and shows module to the MIPI being connected with MIPI liquid crystal display module connector Display.

The present invention is not limited to above-mentioned embodiment, for those skilled in the art, according to this Bright know-why and scheme or the some improvement made under the enlightenment of the present invention, change, retouch, deform, replace and also regard Within protection domain for patent of the present invention.

The content that is not described in detail in this specification, write a Chinese character in simplified form, term belongs to existing known to professional and technical personnel in the field There is technology.

Claims (8)

1. the LVDS video signal of a single LINK is converted to MIPI video signal method, it is characterised in that: comprise the following steps:

Step 1, LVDS video signal to single LINK are received demodulation, when producing LVDS parallel demodulation data and LVDS pixel Clock；

Step 2, described parallel demodulation data carrying out video decoding, generate LVDS video source signal, described LVDS video source is believed Number include LVDS video source data and LVDS video source synchronizing signal, when LVDS pixel clock is converted into LVDS video source pixel Clock, the process that described parallel demodulation data are carried out video decoding includes: regard according to LVDS coding standard control signal and LVDS Frequently color range bit wide control signal, by LVDS video source pixel clock to described LVDS parallel demodulation data with the behaviour of sequential logic It is decoded；

Step 3, described LVDS video source signal is sampled and cached with described LVDS video source pixel clock, by described LVDS video source signal is converted to rgb video signal；Described LVDS video source signal is converted to the process bag of rgb video signal Include: generating rgb video clock, the frequency making described rgb video clock is identical, with described with described LVDS video source pixel clock Rgb video clock read output signal from buffer area, isolates rgb video source data and rgb video synchronizing signal, and order is defeated respectively Go out, thus form described rgb video signal together with described rgb video clock；

Step 4, described rgb video signal is converted to MIPI video signal.

The LVDS video signal of single LINK the most according to claim 1 is converted to MIPI video signal method, and its feature exists In: the LVDS video signal of described single LINK includes that LVDS receives clock and LVDS data, and described LVDS data are by LVDS data Bus transfer, described LVDS data/address bus includes that some holding wires, every holding wire transmit serial code signal；Described MIPI Video signal shows module for the MIPI of 4LANE type.

The LVDS video signal of single LINK the most according to claim 1 is converted to MIPI video signal method, and its feature exists In: before in described step 1, video signal to single LINK is received demodulation, regard according to the LVDS of single LINK to be received Frequently the characteristic of signal, arranges LVDS video signal decoding parametric, synchronous mode control parameter；Receive MIPI video conversion configuration ginseng Number, the configuration operation and the MIPI that perform MIPI conversion process show module initialization operation；According to described LVDS video signal solution Code parameter produces LVDS coding standard control signal, LVDS video color range bit wide control signal；Control according to described synchronous mode Parameter produces LVDS synchronous mode control signal；MIPI transition initialization life is produced according to described MIPI video conversion configuration parameter Order and MIPI module initialization command.

The LVDS video signal of single LINK the most according to claim 2 is converted to MIPI video signal method, and its feature exists In: the process being received demodulating to the LVDS video signal of single LINK in described step 1 includes: to the described single LINK received LVDS video signal in serial code signal be terminated respectively, demodulate, dynamic calibration, produce LVDS parallel demodulation number According to；The process of described termination includes: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with postemphasis, Signal damping and reconstruction；The process of described demodulation includes: described LVDS is received clock and is demodulated, and produces demodulation and enables letter Number, the serial code signal of described LVDS data is individually demodulated to parallel data respectively simultaneously, it is same that described LVDS receives clock Time be demodulated into described LVDS pixel clock.

The LVDS video signal of single LINK the most according to claim 3 is converted to MIPI video signal method, and its feature exists In: after described step 3 forms described rgb video signal, receive described LVDS synchronous mode control signal, detect described RGB Whether video signal is Low level effective, if described rgb video signal is Low level effective, is exported by described rgb signal；As The most described rgb video signal is that high level is effective, is exported by described rgb signal after transferring described rgb signal to Low level effective, MIPI video conversion enabling signal is sent during output.

The LVDS video signal of single LINK the most according to claim 3 is converted to MIPI video signal method, and its feature exists In: it is initial that the configuration operation of described execution MIPI conversion process and MIPI display module initialization operation include receiving MIPI conversion Perform the configuration operation of MIPI conversion process after changing order, confirm that configuration operation performs described MIPI module again after completing and initializes Order, and MIPI module initialization command is transferred to MIPI display module with the form of MIPI order, complete module and initialize Operation, sends MIPI video conversion afterwards and starts order when receiving described MIPI video conversion enabling signal.

The LVDS video signal of single LINK the most according to claim 6 is converted to MIPI video signal method, and its feature exists In: during being exported by described rgb signal, the process carrying out described rgb video clock includes: during to described rgb video The phase place of clock is adjusted so that it is effective edge edge can be in the immediate vicinity of described rgb video source data, then carries out at Key dithering Reason, when described rgb signal exports, compares effective edge and the described rgb video source number of the described rgb video clock after Key dithering According to the deviation between center, and time delay is utilized to do trim process so that effective edge of described rgb video clock and described rgb video Source data center remains alignment.

The LVDS video signal of single LINK the most according to claim 6 is converted to MIPI video signal method, and its feature exists In: the process that described rgb video signal is converted in described step 4 MIPI video signal includes: perform MIPI conversion process Configuration operation and MIPI display module initialization operation after when receive described MIPI video conversion start order time start by The described rgb video signal received is converted to MIPI video signal transmission and shows module to described MIPI.