CN103487734A - Full-digitalization multi-channel real-time synchronous partial discharge detector - Google Patents
Full-digitalization multi-channel real-time synchronous partial discharge detector Download PDFInfo
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- CN103487734A CN103487734A CN201310439146.1A CN201310439146A CN103487734A CN 103487734 A CN103487734 A CN 103487734A CN 201310439146 A CN201310439146 A CN 201310439146A CN 103487734 A CN103487734 A CN 103487734A
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Abstract
The invention belongs to the field of detecting and measuring instruments and discloses a full-digitalization multi-channel real-time synchronous partial discharge detector. The detector comprises signal input units of eight channels. The signal output end of each signal input unit is connected with the signal input end of an A/D conversion circuit through a coarse tuning circuit, a prefixed amplifying circuit, a fine tuning circuit, a low-pass and high-pass filtering circuit and a main amplifying circuit. Each A/D conversion circuit is connected with the signal input end of an FPGA circuit, the FPGA circuit is in data communication with an upper computer, eight cache units corresponding to the channels are connected to the FPGA circuit, the output end of each of the main amplifying circuits on the channels is correspondingly connected with one A/D conversion circuit, the signal output end of each A/D conversion circuit is correspondingly connected with the signal input end of an optical coupling isolation circuit, and the signal output end of each optical coupling isolation circuit is connected with the signal input end of the FPGA circuit. The full-digitalization multi-channel real-time synchronous partial discharge detector improves the capacity of resisting disturbance in the signal transmission process, and can be used in a partial discharge test.
Description
Technical field
The present invention relates to a kind of measuring instrument, particularly a kind of Partial discharge detector.
Background technology
Along with progressively raising and standard that more and more industry product insulation technologies such as motor, transformer, wire require, the usable range of Partial discharge detector is also more extensive, and the user has also had higher requirement to the performance of Partial discharge detector.Existing domestic some aspect of Partial discharge detector is urgently improved, specific as follows:
1) local discharge signal input channel capacity is inadequate.Existing maximum can only arrive 4 passages, although what have is hyperchannel, because the A/D that adopts the simulating signal timesharing gathers, real real-time synchronization is not accomplished in the collection of hyperchannel local discharge signal, but can only timesharing show, be not hyperchannel truly, can't meet the synchronous requirement simultaneously shown of the more signalling channels of some industry needs;
2) antijamming capability is not strong, at present in order to improve the local discharge signal signal to noise ratio (S/N ratio), high-potting ground with digitally be connected, along with the electric pressure of this series products use occasion is more and more higher, even more serious high pressure common mode interference can directly have influence on the normal stable operation of Partial discharge detector.
Summary of the invention
The purpose of this invention is to provide a kind of totally digitilized hyperchannel real-time synchronization Partial discharge detector, solved the problem that hyperchannel of the prior art can not simultaneous display, improve the antijamming capability of Partial discharge detector.
The object of the present invention is achieved like this: a kind of totally digitilized hyperchannel real-time synchronization Partial discharge detector, comprise eight channel signal input end unit, the signal output part of each signal input unit is successively through the coarse adjustment circuit, pre-amplification circuit, the fine tuning circuit, the low pass high-pass filtering circuit, main amplifying circuit is connected with the signal input part of A/D change-over circuit, described A/D change-over circuit is connected with the signal input part of FPGA circuit, described FPGA and host computer carry out data communication, also be connected with eight buffer units corresponding with passage on described FPGA circuit, it is characterized in that, the equal correspondence of the output terminal of the main amplifying circuit on each passage is connected with an A/D change-over circuit, the signal input part that the signal output part correspondence of each described A/D change-over circuit is connected with optical coupling isolation circuit is connected, the signal output part of each described optical coupling isolation circuit all is connected with the signal input part of FPGA circuit.
When the present invention works, detection signal is inputted from signal input unit, the simulating signal of this detection signal stable output after coarse adjustment circuit, pre-amplification circuit, fine tuning circuit, low pass high-pass filtering circuit, main amplifying circuit are processed is to the A/D converting unit, the A/D converting unit can be by the FPGA circuitry stores in buffer unit after optical coupling isolation circuit is processed by the digital signal changed into, and the FPGA circuit communicates the signal and the host computer that detect.Compared with prior art, beneficial effect of the present invention is: the present invention is by configuring independently A/D converting unit for each passage correspondence, guaranteed the synchronism of channel signal transmission, shown when having guaranteed signal, really realized that hyperchannel shows, simultaneously, by optical coupling isolation circuit is set, play Noise Reduction, guaranteed the stability of signal transmission, improve the antijamming capability of signals transmission, guaranteed Partial discharge detector's stable operation.The present invention can be used in partial discharge test.
In order to improve the automaticity of control procedure of the present invention, also be connected with main control microprocessor on described FPGA circuit, be connected with eight sub-control microprocessors on described main control microprocessor, each sub-control microprocessor correspondence is connected on the coarse adjustment circuit, pre-amplification circuit, fine tuning circuit, low pass high-pass filtering circuit, main amplifying circuit of respective channel.Make office put the coarse adjustment of simulating signal, fine tuning, low pass selection, high pass selection etc. and all control by the upper computer software interface button, realize the total digitalization management.
In order further to guarantee the stability of signal transmission to realize the real-time processing of maximum eight passage Partial discharge signals, between described FPGA circuit and host computer, through the PCI-E interface, complete exchanges data.The data that assurance collects can be uploaded in time, for upper dynamo-electric brain analysis, processing, demonstration, preservation.
The accompanying drawing explanation
Fig. 1 is control principle block diagram of the present invention.
The circuit theory diagrams that Fig. 2 is coarse adjustment circuit in the present invention.
The circuit theory diagrams that Fig. 3 is pre-amplification circuit in the present invention.
The circuit theory diagrams that Fig. 4 is fine tuning circuit in the present invention.
The circuit theory diagrams that Fig. 5 is low pass high-pass filtering circuit in the present invention.
The circuit theory diagrams that Fig. 6 is main amplifying circuit in the present invention.
Embodiment
A kind of totally digitilized hyperchannel real-time synchronization Partial discharge detector as shown in Figure 1, comprise eight channel signal input end unit, the signal output part of each channel signal input block is successively through the coarse adjustment circuit, pre-amplification circuit, the fine tuning circuit, the low pass high-pass filtering circuit, main amplifying circuit is connected with the signal input part of A/D change-over circuit, the A/D change-over circuit is connected with the signal input part of FPGA circuit, FPGA and host computer carry out data communication, also be connected with eight buffer units corresponding with passage on the FPGA circuit, it is characterized in that, the equal correspondence of the output terminal of the main amplifying circuit on each passage is connected with an A/D change-over circuit, the signal input part that the signal output part correspondence of each A/D change-over circuit is connected with optical coupling isolation circuit is connected, the signal output part of each optical coupling isolation circuit all is connected with the signal input part of FPGA circuit, also be connected with main control microprocessor on the FPGA circuit, be connected with eight sub-control microprocessors on main control microprocessor, each sub-control microprocessor correspondence is connected to the coarse adjustment circuit of respective channel, pre-amplification circuit, the fine tuning circuit, the low pass high-pass filtering circuit, on main amplifying circuit, complete exchanges data through the PCI-E interface between FPGA circuit and host computer.
When the present invention works, as shown in Figure 2, the Partial discharge signal come from input block is entering signal gain coarse adjustment circuit at first, this part forms 6 grades of gain adjustment circuits by JD1-JD4 relay and a series of high-precision resistance in conjunction with the JD5-JD6 of preposition amplifier section, between adjacent gear, gain differs 10 times, therefore input signal is had to the setting range of 60dB, effectively increase the examination scope of Partial discharge signal, the synchronism while guaranteeing eight passage work.The corresponding relation of gear and relay work is as follows:
In the coarse adjustment circuit, D1, D2 fast recovery diode play the signal limiter effect, avoid, because signal is excessive, late-class circuit is caused to hardware damage.
As shown in Figure 3, the signal coarse adjustment outputs to preposition input, at first through 10 times of amplifications of L2 transformer, adopts transformer to boost here and can effectively improve signal to noise ratio (S/N ratio); Q1, Q2, tri-triodes of Q3 form negative feedback amplifier circuit with capacitance resistance ware, and it is in order to improve the input impedance of signal that elementary Q1 adopts fet, further improves the stability of circuit working; The feedback resistance of rear class IC4 amplifier and JD5, JD6 Control forms the adjustable amplifying circuit of three gain per stages, in conjunction with the coarse adjustment circuit, realizes wide region input signal regulatory function.
As shown in Figure 4, although the coarse adjustment circuit is subject to the impact of working environment by selecting resistance that precision is high to improve the accuracy of every grade of gain, also have the inconsistency of other device parameters, be necessary to add a gain per stage fine tuning circuit.For realizing automatic regulating function, adopt the electronic potentiometer AD5231 of 1 1024 in this circuit, the MCU simulated on plate by 3 high speed photo coupling 6N137 controls, and realizes isolation rapid adjustment function.In conjunction with R39 resistance, can guarantee that the setting range of signal reaches 10dB.
As shown in Figure 5, enter filtering circuit after signal fine tuning output; Containing low pass, high pass, respectively being divided into third gear in this circuit, is passive filter circuit, and by the filtering combination of Control gating individual features, specific works frequency filtering characteristic is as follows to the action relationships of relevant relay:
The optional performance that high pass, lowpass frequency characteristic have been arranged, can make Partial discharge detector's various electromagnetic interference signals of the on-the-spot surrounding environment of filtering in actual use, real Partial discharge signal detected easily.
As shown in Figure 6, from with logical next signal, entering the final stage wideband amplification circuit formed by the IC6 amplifier, in this circuit, produced the voltage-reference of 2.5V by TL431, thereby allow the AC signal of input be lifted to the 2.5V benchmark from 0 benchmark, be convenient to the A/D conversion of rear class.The ZV1 stabilivolt plays the amplitude limit effect, the protection late-class circuit.
The present invention is not limited to above-described embodiment; on the basis of technical scheme disclosed by the invention; those skilled in the art is according to disclosed technology contents; do not need performing creative labour just can make some replacements and distortion to some technical characterictics wherein, these replacements and distortion are all in protection scope of the present invention.
Claims (3)
1. a totally digitilized hyperchannel real-time synchronization Partial discharge detector, comprise eight channel signal input end unit, the signal output part of each signal input unit is successively through the coarse adjustment circuit, pre-amplification circuit, the fine tuning circuit, the low pass high-pass filtering circuit, main amplifying circuit is connected with the signal input part of A/D change-over circuit, described A/D change-over circuit is connected with the signal input part of FPGA circuit, described FPGA and host computer carry out data communication, also be connected with eight buffer units corresponding with passage on described FPGA circuit, it is characterized in that, the equal correspondence of the output terminal of the main amplifying circuit on each passage is connected with an A/D change-over circuit, the signal input part that the signal output part correspondence of each described A/D change-over circuit is connected with optical coupling isolation circuit is connected, the signal output part of each described optical coupling isolation circuit all is connected with the signal input part of FPGA circuit.
2. a kind of totally digitilized hyperchannel real-time synchronization according to claim 1 Partial discharge detector, it is characterized in that, also be connected with main control microprocessor on described FPGA circuit, be connected with eight sub-control microprocessors on described main control microprocessor, each sub-control microprocessor correspondence is connected on the coarse adjustment circuit, pre-amplification circuit, fine tuning circuit, low pass high-pass filtering circuit, main amplifying circuit of respective channel.
3. a kind of totally digitilized hyperchannel real-time synchronization according to claim 1 and 2 Partial discharge detector, is characterized in that, between described FPGA circuit and host computer, through the PCI-E interface, completes exchanges data.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105319490A (en) * | 2015-12-04 | 2016-02-10 | 重庆臻远电气有限公司 | Partial discharge data acquisition circuit and equipment |
| CN105353287A (en) * | 2015-12-04 | 2016-02-24 | 重庆臻远电气有限公司 | Partial discharge data acquisition circuit and apparatus |
| CN108594708A (en) * | 2018-04-24 | 2018-09-28 | 苏州赛腾精密电子股份有限公司 | I/O control cards and I/O method for transmitting signals |
| CN110161308A (en) * | 2019-05-22 | 2019-08-23 | 重庆国翰能源发展有限公司 | A kind of electric energy metering device for alternating-current charging pile |
| CN110687407A (en) * | 2019-09-30 | 2020-01-14 | 南澳电气(武汉)有限公司 | Automatic positioning system for detecting and analyzing ultrasonic waves of eight-channel partial discharge tester |
| CN111596183A (en) * | 2020-06-11 | 2020-08-28 | 合肥工业大学 | Multichannel gain controllable photoelectric detection system and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105353287A (en) * | 2015-12-04 | 2016-02-24 | 重庆臻远电气有限公司 | Partial discharge data acquisition circuit and apparatus |
| CN108594708A (en) * | 2018-04-24 | 2018-09-28 | 苏州赛腾精密电子股份有限公司 | I/O control cards and I/O method for transmitting signals |
| CN110161308A (en) * | 2019-05-22 | 2019-08-23 | 重庆国翰能源发展有限公司 | A kind of electric energy metering device for alternating-current charging pile |
| CN110687407A (en) * | 2019-09-30 | 2020-01-14 | 南澳电气(武汉)有限公司 | Automatic positioning system for detecting and analyzing ultrasonic waves of eight-channel partial discharge tester |
| CN111596183A (en) * | 2020-06-11 | 2020-08-28 | 合肥工业大学 | Multichannel gain controllable photoelectric detection system and method thereof |
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