CN103474417B - A kind of three-dimensional interconnection structure and preparation method thereof - Google Patents
A kind of three-dimensional interconnection structure and preparation method thereof Download PDFInfo
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- CN103474417B CN103474417B CN201310456142.4A CN201310456142A CN103474417B CN 103474417 B CN103474417 B CN 103474417B CN 201310456142 A CN201310456142 A CN 201310456142A CN 103474417 B CN103474417 B CN 103474417B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 535
- 229910052751 metal Inorganic materials 0.000 claims abstract description 535
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 238000000227 grinding Methods 0.000 claims abstract description 17
- 238000001459 lithography Methods 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 230000004888 barrier function Effects 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 19
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 15
- 239000010931 gold Substances 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 15
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- 238000001465 metallisation Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 21
- 230000011514 reflex Effects 0.000 abstract description 5
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- 238000000034 method Methods 0.000 description 47
- 238000012545 processing Methods 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 101100242304 Arabidopsis thaliana GCP1 gene Proteins 0.000 description 8
- 101100412054 Arabidopsis thaliana RD19B gene Proteins 0.000 description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
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- 230000001154 acute effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
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- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 235000012239 silicon dioxide Nutrition 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
The invention provides a kind of three-dimensional interconnection structure and preparation method thereof, by forming dovetail groove in the front of Semiconductor substrate, then on the inclined-plane of dovetail groove, lay at least one of which front metal wiring layer, then, the grinding semiconductor back side makes to be positioned at each layer front metal wiring layer bottom the close described dovetail groove on described dovetail groove inclined-plane and exposes, then at the front metal wiring layer at least one of which formed below back metal wiring layer of semiconductor back surface and exposure.The metal wiring layer being positioned at quasiconductor front and the metal wiring layer being positioned at semiconductor back surface achieve electrical connection by the metal wiring layer on dovetail groove.In the three-dimensional interconnection structure that the present invention provides, the front metal wiring layer being positioned on dovetail groove inclined-plane is equivalent to transmission belt, can be implemented in quasiconductor front, between dovetail groove inclined-plane and semiconductor back surface, form the interconnection line that impedance is same or like, it is possible to overcome the problem that the signaling reflex caused due to impedance mismatch is big.
Description
Technical field
The present invention relates to Electronic Packaging field, particularly relate to a kind of three-dimensional interconnection structure and preparation method thereof.
Background technology
Along with the characteristic size of integrated circuit constantly reduces, the complexity of chip is continuously increased, interconnection density
Improve constantly.Wire bonding is relatively low due to interconnection density, can not meet the requirement of multi-chip high-density packages.
For meeting high interconnection density, shorten interconnection path, solve three-dimensional stacked interconnection bottleneck, new encapsulation technology,
Three dimensional integrated circuits (3D-IC) technology i.e. utilizing silicon through hole (Through-Silicon-Via, TSV) should
Transport and give birth to.
3D-TSV integrated technology is one of microelectronics core technology, and 3D-TSV interconnection provides and surmounts " mole "
Method, be most advanced, the most complicated encapsulation technology, it is possible to obtain preferably electrical property, low-power consumption,
Noise, less package dimension, low cost and multifunction.3D-TSV technology will be widely used in micro-
The consumer electronics products such as electronic applications, especially smart mobile phone, including smart mobile phone, Internet appliances,
The high-end products such as sensor, memorizer, solaode, LED, power device.
TSV has two kinds of structures, one be on silicon chip make, referred to as TSV interposer, one be
Making on chip with active area, its Main Function is perpendicular interconnection.At present, TSV interposer is
Main TSV structure.The overall structure of this TSV interposer is as it is shown in figure 1, TSV hole 07 through-silicon serves as a contrast
The front and back at the end 01, is provided with front metal wiring layer in the front of this TSV interposer structure
RDL02, is additionally provided with the Cu/Sn UBM pad 04 for chip package, in structure in the front of this structure
The back side be provided with insulating barrier 03 and back metal wiring layer 05, be additionally provided with overleaf for substrate package
Cu Pillar Bump06.
TSV technology is the most complicated, the most difficult a kind of Advanced Electronic Encapsulating, is not only embodied in TSV work
Skill is more embodied in on TSV active chip or TSV interposer microwave assembly technology on manufacturing.For reality
Existing narrow pitch interconnection, high-aspect-ratio TSV hole is limited by equipment and technique again, need chip or
Interposer carries out being thinned to the thickness of tens microns, this just for follow-up holding, the technique such as assembling bring huge
Challenge.It addition, in order to reduce cost, TSV technique is all based on greatly low-resistance silicon.The characteristic of semiconductor of low-resistance silicon
Cause dielectric loss relatively big, TSV pass structure characteristic impedance and metal wiring layer line characteristic impedance mismatch
Also signaling reflex be can cause, the high speed of TSV, high-frequency transmission poor-performing caused.
Summary of the invention
In order to solve above-mentioned high speed, the technical problem of high-frequency transmission poor-performing, the invention provides a kind of new
Three-dimensional interconnection structure and preparation method thereof.
In order to solve above-mentioned technical problem, present invention employs following technical scheme:
The preparation method of a kind of three-dimensional interconnection structure, described three-dimensional interconnection structure at least includes the first front metal
Wiring layer and the first back metal wiring layer, described preparation method includes,
Dovetail groove is formed in the front of Semiconductor substrate;
Front insulating barrier is formed above described Semiconductor substrate front and described dovetail groove；
Above the insulating barrier of described front, form the first front lighting photoresist, and described first front lighting photoresist is entered
Row lithographic patterning, to form the first front metal wiring layer pattern；
According to described first front metal wiring layer pattern, above the insulating barrier of described front, form the first front
Metal wiring layer；
Forming the first front dielectric layer above described first front metal wiring layer, wherein, described first just
Multiple prodefined opening it is formed with on the dielectric layer of face；
Use metal filled described prodefined opening, with the front metal wiring layer formed and below the dielectric layer of front
The interconnection of connection；
Grinding the back side of described Semiconductor substrate, make to be positioned at above described dovetail groove inclined-plane is close described trapezoidal
The described front metal wiring layer of trench bottom exposes, until the front metal wiring layer bottom dovetail groove all goes
Remove；
Described Semiconductor substrate lower rear after grinding forms insulating backside layer；
Described insulating backside layer is carried out lithographic patterning, and etches described insulating backside according to photoengraving pattern
Layer, to form prodefined opening on described insulating backside layer, it is oblique that described prodefined opening makes to be positioned at described dovetail groove
Described front metal wiring layer bottom close described dovetail groove above face exposes；
The front metal wiring layer back side formed below above the inclined-plane of described insulating backside layer and exposure
Photoresist, and described back light photoresist is carried out lithographic patterning, to form the first back metal wiring layer figure
Case；Wherein, described first back metal wiring layer pattern includes multiple breaking part；
According to described first back metal wiring layer pattern, on the inclined-plane of described insulating backside layer and exposure
The front metal wiring layer first back metal wiring layer formed below of side；Described first back metal wiring layer
The first back metal wiring sublayer including multiple disconnections；Each described first back metal wiring sublayer and institute
State on insulating backside layer prodefined opening be connected and fill the prodefined opening on the insulating backside layer of connection；
At described first back metal wiring layer the first back side dielectric layer formed below, described first back side medium
Multiple prodefined opening it is formed with on Ceng；One is at least had below each described first back metal wiring sublayer
Individual described prodefined opening；
With back metal wiring above the formation of metal filled described prodefined opening and described back side dielectric layer
The interconnection that layer connects.
Further, described three-dimensional interconnection structure includes m layer front metal wiring layer and/or n-layer back-side gold
Belong to wiring layer, after described formation the first front metal wiring layer and the first front dielectric layer, described grinding half
Before conductor substrate back, also including, m-1 first circulation, described first circulation includes,
The i-th front lighting photoresist is formed above described i-th-1 front dielectric layer, and to described i-th front lighting
Photoresist carries out lithographic patterning, with formed the i-th front metal wiring layer pattern and with the i-th-1 front metal cloth
The interconnection pattern that line layer connects；Wherein, described i-th-1 front dielectric layer has prodefined opening；Described
I front metal wiring layer pattern and described and that the i-th-1 front metal wiring layer is connected interconnection pattern are the most disconnected
Open；
According to described i-th front metal wiring layer pattern and the interconnection network that is connected with the i-th-1 front metal wiring layer
Case, formed above the i-th-1 front dielectric layer the i-th front metal wiring layer and with the i-th-1 front metal wiring layer
The interconnection connected；
Formed at described i-th front metal wiring layer with above the interconnection that the i-th-1 front metal wiring layer is connected
I-th front dielectric layer；
Described i-th front dielectric layer is carried out lithographic patterning and etching forms prodefined opening；
And/or, n-1 second circulation, described second circulation includes,
After the first back metal wiring layer the first back side dielectric layer formed below, also include,
Lithographic patterning is carried out, to form jth back metal wiring layer pattern above the dielectric layer of jth-1 back side；
Wherein, described jth back metal wiring layer pattern includes multiple breaking part；
According to described jth layer back metal wiring layer pattern, in described jth-1 back side dielectric layer jth formed below
Back metal wiring layer: described jth back metal wiring layer includes jth back metal wiring of multiple disconnection
Layer；
In the jth back side formed below dielectric layer of jth back metal wiring layer, shape on the dielectric layer of the described jth back side
Become to have multiple prodefined opening;
Wherein, m >=2, n >=2,2≤i≤m, 2≤j≤n.
It is further, described at described jth-1 back side dielectric layer jth formed below back metal wiring layer,
Specifically, form jth back metal wiring layer by repeatedly lithographic patterning and metallization.
Further, the hardware cloth on described front metal wiring layer and/or on described back metal wiring layer
Line is single ended line, difference connecting line.
Further, the metal line on described front metal wiring layer and/or described back metal wiring layer
For common interconnection line, co-planar waveguide, microstrip line, the co-planar waveguide microstrip line on band ground or strip line.
A kind of three-dimensional interconnection structure, described three-dimensional interconnection structure at least includes the first front metal wiring layer and the
One back metal wiring layer, it includes,
Semiconductor substrate, described Semiconductor substrate includes relative front and back；In described Semiconductor substrate
Having the trapezoidal hole running through front and back, the described trapezoidal hole opening in described Semiconductor substrate front is more than
Opening at the described Semiconductor substrate back side；
It is positioned at the front insulating barrier above described Semiconductor substrate upper front and described trapezoidal hole inclined-plane；
It is positioned at the first front metal wiring layer above the insulating barrier of described front, described first front metal wiring
Layer includes two the first front metal wiring sublayers disconnected；
It is positioned at the first front dielectric layer above described first front metal wiring layer；Wherein, described first just
Include multiple prodefined opening on the dielectric layer of face, be formed in described prodefined opening for by described first front gold
Belong to the interconnection that wiring layer is drawn；Wherein, the outermost front dielectric layer of described three-dimensional interconnection structure it is positioned at also
Fill described trapezoidal hole；
It is positioned at the insulating backside layer below described Semiconductor substrate lower rear and described front dielectric layer, institute
State the front metal wiring layer bottom the insulating backside layer close described trapezoidal hole on described trapezoidal hole inclined-plane
Opening formed below；
Be sequentially located at described insulating backside layer and described in be positioned at the close described ladder on described trapezoidal hole inclined-plane
The first back metal wiring layer below front metal wiring layer bottom shape hole and the first back side dielectric layer；
Wherein, described first back metal wiring layer includes first back of the body that at least two disconnects, mutually insulated
Face metal line sublayer, each described first back metal wiring sublayer also fills up on described insulating backside layer
Opening is also connected with described front metal wiring layer by the opening on described insulating backside layer；
It is formed with prodefined opening on described first back side dielectric layer, is formed in described prodefined opening for by institute
State the interconnection that the first back metal wiring layer is drawn, and below each described first back metal wiring sublayer
It is formed with an interconnection.
Further, described three-dimensional interconnection structure includes m layer front metal wiring layer and m layer front medium
Layer；
Wherein, i+1 front metal wiring layer is positioned at the top of the i-th front dielectric layer, described i-th front
It is provided with multiple prodefined opening on dielectric layer, is formed in described prodefined opening for by the i-th-1 front metal
Wiring layer draw interconnection, wherein, for by i-th-1 front metal wiring layer draw interconnection be used for by
The interconnection mutually insulated that i-th front metal wiring layer is drawn；
Wherein, m >=2,2≤i≤m.
Further, described three-dimensional interconnection structure includes n-layer back metal wiring layer and n-layer back side dielectric layer；
Wherein, jth back side dielectric layer is positioned at the lower section of jth back metal wiring layer, described jth back-side gold
Belong to wiring layer and include that multiple disconnection, mutually insulated jth back metal connects up sublayer；
Be provided with multiple prodefined opening on the dielectric layer of the described jth back side, be formed in described prodefined opening for
The interconnection drawn by jth back metal wiring layer, wherein, for drawing jth-1 back metal wiring layer
Interconnection with for by jth back metal wiring layer draw interconnection mutually insulated；
Wherein, n >=2,2≤j≤n.
Further, the hardware cloth on described front metal wiring layer and/or on described back metal wiring layer
Line is single ended line, difference connecting line.
Further, the metal line on described front metal wiring layer and/or described back metal wiring layer
For common interconnection line, co-planar waveguide, microstrip line, the co-planar waveguide microstrip line on band ground or strip line.
Three-dimensional interconnection structure that the present invention provides and preparation method thereof, by being formed in the front of Semiconductor substrate
Dovetail groove, then lays one or more layers front metal wiring layer on the inclined-plane of dovetail groove, then, grinds
And polish semiconductor back surface and make just be positioned at each layer bottom the close described dovetail groove on described dovetail groove inclined-plane
Face metal wiring layer exposes, and then the front metal wiring layer in semiconductor back surface and exposure is formed below extremely
Few one layer of back metal wiring layer.So, it is positioned at the metal wiring layer in quasiconductor front and is positioned at the quasiconductor back of the body
The metal wiring layer in face achieves electrical connection by the metal wiring layer on dovetail groove.Three provided in the present invention
In dimension interconnection structure, the front metal wiring layer being positioned on dovetail groove inclined-plane is equivalent to transmission belt, owing to being positioned at
Front metal wiring layer on dovetail groove inclined-plane and the front metal wiring being positioned at other region, quasiconductor front
The material of layer and the back metal wiring layer that is positioned at semiconductor back surface is identical, say, that transmission belt and metal
The material of wiring layer is identical, and structure change is little, and such signal is in transmitting procedure, and transient impedance becomes
Change little, so make to cause signaling reflex the least due to impedance mismatch, thus cause this three-dimensional interconnection
The high speed of structure, high frequency performance are preferable.
Meanwhile, three-dimensional interconnection structure that the present invention provides and preparation method thereof, insulator can be used to make medium
Layer and cover more greatly the isolation as electromagnetic wave of copper plane or grid, so the medium that causes of silicon (Si) substrate damages
Consume less.
Accompanying drawing explanation
In order to be expressly understood the embodiment of the present invention or prior art, below to describing prior art or basis
The accompanying drawing used during invention detailed description of the invention is briefly described.It should be evident that these accompanying drawings are only these
Some bright embodiments, for those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to obtain other accompanying drawing.
Fig. 1 is TSV structure schematic diagram in prior art；
Fig. 2 is the preparation method schematic flow sheet of the three-dimensional interconnection structure of the embodiment of the present invention one；
Fig. 3 (1) to Fig. 3 (11) be the embodiment of the present invention one preparation method in a series of processing procedures corresponding
Structural representation；
Fig. 4 is the preparation method schematic flow sheet of the three-dimensional interconnection structure of the embodiment of the present invention two；
Fig. 5 (1) to Fig. 5 (14) be the embodiment of the present invention two preparation method in a series of processing procedures corresponding
Structural representation；
Fig. 6: different vertical interconnection structure insertion loss S12 correlation curve figure；
Fig. 7: different vertical interconnection structure return loss S11 correlation curve figure；
Fig. 8 is novel TSS structure transmission belt schematic diagram.
Reference:
100: substrate, 101: dovetail groove (hole), 102, front insulating barrier, 1031: the first front photoetching
Glue, 1032: the second front lighting photoresist, 1041: the first front metal wiring layers, 1042: the second front gold
Genus wiring layer, 1051: the first front dielectric layers, 1052: the second front dielectric layers, 106: insulating backside
Layer, 107: back light photoresist, 1081: the first back metal wiring layers, 1082: the second back metal wirings
Layer, 1091: the first back side dielectric layers, 1092: the second back side dielectric layers, 51 ': with the first front metal cloth
The interconnection that line layer connects, 91 ': the interconnection being connected with the first back metal wiring layer, 52 ': under the salient point of front
Metal, 92 ': metal under the salient point of the back side.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the present invention
Accompanying drawing in embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention, it is clear that
Described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based in the present invention
Embodiment, those of ordinary skill in the art obtained under not making creative work premise all its
His embodiment, broadly falls into the scope of protection of the invention.
Embodiment one
In conjunction with Fig. 2 to Fig. 3 (11), the manufacture method of embodiment one is described in detail.Described in embodiment one
The preparation method of three-dimensional interconnection structure include one layer of front metal wiring layer and one layer of back metal wiring
The preparation of layer.Fig. 2 is the manufacture method schematic flow sheet of the present embodiment, and Fig. 3 (1) to Fig. 3 (11) is this
The structural representation that a series of processing procedure of manufacture method of embodiment is corresponding.
Seeing Fig. 2, this manufacture method comprises the following steps:
S201, the front of Semiconductor substrate formed dovetail groove；
In semiconductor fabrication process, the etch areas one formed by selective etch or anisotropic etching
As be groove wide at the top and narrow at the bottom, generally dovetail groove.Described selective etch is generally dry etching, as
Plasma etching.
As shown in Fig. 3 (1), the present embodiment uses anisotropic etching to enter the front of Semiconductor substrate 100
Row etching, forms dovetail groove 101 in the front of Semiconductor substrate 100.
S202, above described Semiconductor substrate upper front and described dovetail groove, form front insulating barrier:
As shown in Fig. 3 (2), just formed above Semiconductor substrate 100 upper front and dovetail groove 101
Face insulating barrier 102, this front insulating barrier 102 can use silicon dioxide (SiO2) insulating barrier, work as quasiconductor
When substrate is silicon substrate, the present embodiment can use hot oxygen method to form silicon dioxide (SiO2) insulating barrier.
S203, above the insulating barrier of described front, form the first front lighting photoresist and carry out lithographic patterning, with
Form the first front metal wiring layer pattern:
Those skilled in the art know, and metal wiring layer is by certain pattern.So, forming metal
Before wiring layer, lithographic patterning to be carried out forms the pattern of metal wiring layer.Specifically, the present embodiment is first
The first front lighting photoresist 1031 is formed, then to this first front lighting photoresist above front insulating barrier 102
1031 carry out lithographic patterning, to form the first front metal wiring layer pattern.The structure that this processing procedure is corresponding is shown
It is intended to as shown in Fig. 3 (3).
S204, foundation the first front metal wiring layer pattern, just forming first above the insulating barrier of described front
Face metal wiring layer, forms the first front dielectric layer above the first front metal wiring layer；
As shown in Fig. 3 (4), it is first depending on the pattern of above-mentioned lithographic patterning formation at front insulating barrier 102
Top form the first front metal wiring layer 1041(front RDL1), then remove the first front lighting photoresist
1031, then at this front metal wiring layer 1041(front RDL1) and be originally the first front lighting photoresist
The top of the 1031 front insulating barriers covered forms the first front dielectric layer 1051.
This formation the first front metal wiring layer 1041(front RDL1) and the first front dielectric layer 1051
Technical process is ordinary skill in the art means, those skilled in the art combine this area common knowledge and
Routine techniques means can be known easily.Such as can use formation first front metal of metal plating
Wiring layer 1041.It should be noted that in order to make three-dimensional interconnection structure keep smooth, owing to the first front is situated between
Matter layer 1051 is positioned at the outermost layer of the three-dimensional interconnection structure of this formation, so, this first front dielectric layer 1051
It is preferably filled with the most described dovetail groove 101, so that the front of the three-dimensional interconnection structure formed is the most smooth.
In the present embodiment, the metal line on the first front metal wiring layer 1041 can be single ended line, difference
Divide the transmission lines such as the co-planar waveguide microstrip line on connecting line, co-planar waveguide microstrip line, band ground, strip line.Enter one
Preferably, the metal line on this first front front metal wiring layer 1041 can be co-planar waveguide, micro-to step
The co-planar waveguide microstrip line on band wire, band ground or strip line.
S205, form prodefined opening in the precalculated position of described first front dielectric layer, and use metal filled institute
State prodefined opening to form metal under the salient point of front:
As shown in Fig. 3 (5), the first front dielectric layer 1051 is carried out lithographic patterning and etching, this
The precalculated position of one front dielectric layer 1051 forms prodefined opening, then uses this prodefined opening shape metal filled
Become metal (under bump metallization, UBM) 51 ' under salient point.Gold in metal 51 ' under this salient point
Belong to and fill and can realize in the way of using plating, it is also possible to realize by depositing metal in prodefined opening.Shape
Under the salient point become, metal 51 ' is for realizing the interconnection with chip.
In the present embodiment, the number in the precalculated position of the first front dielectric layer 1051 can be by the three-dimensional formed
How many decisions of the solder joint of the chip that interconnection structure connects.This precalculated position is positioned at the first front dielectric layer 1051
Which position can also by chip solder joint determine, as long as making metal 51 ' under the salient point ultimately formed have
It is beneficial to the connection realizing three-dimensional interconnection structure with chip.
S206, grind the back side of described Semiconductor substrate, make the close institute being positioned at above described dovetail groove inclined-plane
State the described first front metal wiring layer bottom dovetail groove to expose:
It should be noted that the inclined-plane of dovetail groove 101 described herein i.e. the side of dovetail groove 101, also
It it is exactly the slope of dovetail groove.
The back side of grinding semiconductor substrate 100, the thickness of thinning Semiconductor substrate 100, so that being positioned at trapezoidal
On groove 101 inclined-plane and bottom described dovetail groove described first front metal wiring layer 1041 exposes.
It is to say, the Semiconductor substrate 100 below dovetail groove is all removed, and also further will
First front metal wiring layer 1041 of the bottom being positioned at dovetail groove 101 also grinds removal, so original formation
Dovetail groove 101 the most just to become bottom be the dovetail groove 101 of the first front dielectric layer 1051.Now,
It is positioned at the first front metal wiring layer 1041 bottom this dovetail groove 101 above dovetail groove 101 inclined-plane
Do not blocked, outside being exposed on by the Semiconductor substrate 100 being initially positioned at below.As shown in Fig. 3 (6).
By grinding semiconductor substrate 100 back side, make the first front metal wiring layer 1041 by continuous print one
Metal level is divided into two front metal wiring sublayers of disconnection.
Under S207, the back side of described Semiconductor substrate after grinding and the described front metal wiring layer of exposure
Square one-tenth insulating backside layer:
In order to realize the insulation of follow-up back metal wiring layer and Semiconductor substrate, quasiconductor after grinding
The back side of substrate 100 and the insulating backside layer 106 formed below of the first front metal wiring layer 1041 of exposure.
As shown in Fig. 3 (7).
It should be noted that the described first front metal wiring layer 1041 of exposure described herein is for being positioned at
State the first front metal wiring layer 1041 bottom described dovetail groove above dovetail groove inclined-plane.
S208, insulating backside layer is carried out lithographic patterning and etching, make to be positioned on described dovetail groove inclined-plane
Described first front metal wiring layer bottom described dovetail groove exposes again:
Use technological means customary in the art that insulating backside layer 106 is carried out lithographic patterning and etching, with
Forming the prodefined opening on insulating backside layer 106, the prodefined opening on this insulating backside layer 106 makes to be positioned at described
The first front metal wiring layer 1041 bottom close described dovetail groove on dovetail groove 101 inclined-plane is the most sudden and the most violent
Dew.Such as 3(8) shown in.
S209, square under described insulating backside layer and the described first front metal wiring layer that again exposes
Become back light photoresist, described back light photoresist is carried out lithographic patterning, to form the first back metal wiring
Layer pattern:
It should be noted that due to by the grinding back surface to Semiconductor substrate 100, by the first front metal
Wiring layer 1041 is divided into two sub-metal wiring layers disconnected, for sub-hardware cloth the two disconnected respectively
Line layer guides to substrate back respectively, needs to draw with the back metal wiring layer of mutually insulated.So, this step
The pattern of rapid the first back metal wiring layer formed is two parts disconnected.Structure corresponding to this step is shown
It is intended to as shown in Fig. 3 (9).
S210, according to this first back metal wiring layer pattern, at described insulating backside layer and again expose
Described first front metal wiring layer the first back metal wiring layer formed below, at the first back metal cloth
Line layer the first back side dielectric layer formed below:
First, according to this first back metal wiring layer pattern, insulating barrier 106 and again exposing overleaf
The first back metal wiring layer 1081(back side formed below of described first front metal wiring layer 1041
RDL1).Owing to the first back metal wiring layer pattern is two parts disconnected, so, the first of formation
Metal layer on back 1081 is made up of two back metal wiring sublayers disconnected.Then, back light photoresist is removed
107, then in the lower section of this first back metal wiring layer 1081 and originally covered by back light photoresist 107
Region form the first back side dielectric layer 1091.As shown in Fig. 3 (10).
It should be noted that the first back metal wiring layer 1081 also can fill holding on insulating backside layer 106
Mouthful, so that the first front metal wiring layer 1041 and the first back metal wiring layer 1081 realize electrical connection.
So, the front metal wiring sublayer of two disconnections of the first front metal wiring layer 1041 is respectively by first back of the body
Face metal line sublayer is drawn.This lead-out mode is conducive to improving transmission speed and the height of three-dimensional interconnection structure
Frequently performance.
In the present embodiment, the metal line on the first back metal wiring layer 1081 can be single ended line, difference
Divide the transmission lines such as the co-planar waveguide microstrip line on connecting line, co-planar waveguide microstrip line, band ground, strip line.Enter one
Preferably, the metal line on this first back-front metal wiring layer can also be co-planar waveguide, micro-strip to step
The co-planar waveguide microstrip line on line, band ground or strip line.
Owing to being positioned at the first front metal wiring layer bottom the close dovetail groove 101 on dovetail groove 101 inclined-plane
1041 expose, it is possible to be connected with the first back metal wiring layer 1081 thereunder formed.So, logical
Crossing the first front metal wiring layer 1041 bottom the close dovetail groove being positioned on dovetail groove 101 inclined-plane can
Will be located in the first front metal wiring layer 1041(front RDL1 on Semiconductor substrate 100 front) and the
One back metal wiring layer 1081(back side RDL1) realize interconnection.So, it is positioned at dovetail groove 101 inclined-plane
On the first front metal wiring layer 1041 be equivalent to be positioned at the first front metal of quasiconductor upper front
Wiring layer 1041 and the transmission belt of the first back metal wiring layer 1081.Owing to being positioned at dovetail groove 101 inclined-plane
On the first front metal wiring layer 1041 and be positioned at the first front metal cloth in other region, quasiconductor front
The material of line layer 1041 and the first back metal wiring layer 1081 of being positioned at semiconductor back surface is identical, the most just
Being to say that transmission belt is identical with the material of metal wiring layer, such signal is in transmitting procedure, and transient impedance changes
Not quite, so make to cause signaling reflex the least due to impedance mismatch, thus cause this three-dimensional interconnection to be tied
The high speed of structure, high frequency performance are preferable.
S211, form prodefined opening in the precalculated position of described first back side dielectric layer, and use metal filled institute
State prodefined opening and form metal under back side salient point:
First back side dielectric layer 1091 is carried out lithographic patterning and etching, at the first back side dielectric layer 1091
Precalculated position formed prodefined opening, and with this prodefined opening metal filled formation salient point under metal 91 '.Should
Shown in the structural representation such as Fig. 3 (11) that processing procedure is corresponding.
In the present embodiment, the number in the precalculated position of the first back side dielectric layer 1091 can be by the three-dimensional formed
How many decisions of the solder joint of the substrate that interconnection structure connects.This precalculated position is positioned at the first back side dielectric layer 1091
Which position can also be determined by the solder joint of substrate, as long as making under the salient point ultimately formed metal be conducive to
Realize the connection of three-dimensional interconnection structure and substrate.
More than for including one layer of front metal wiring layer (front RDL1) and one layer of back metal wiring layer (back of the body
Face RDL1) the preparation method flow process of three-dimensional interconnection structure.
Compared to the preparation method of TSV structure, the preparation method of this three-dimensional interconnection structure avoids the need for making
The technological operation in high-aspect-ratio TSV hole, the preparation method of the present embodiment is by carrying out selectivity to substrate face
Etching forms dovetail groove, then (includes inclined-plane and the bottom of dovetail groove) above substrate face and dovetail groove
Form front metal wiring layer.By being positioned at above dovetail groove inclined-plane the front metal cloth bottom the dovetail groove
Line layer will be located in the front metal wiring layer in Semiconductor substrate front and is positioned at the back metal of semiconductor back surface
Wiring layer couples together, and defines interconnection structure.The preparation method technological operation of this three-dimensional interconnection structure is relatively
For easily, be conducive to improving efficiency.
The preparation method of the three-dimensional interconnection structure described in embodiment one include one layer of front metal wiring layer and
The preparation of one layer of back metal wiring layer, its preparation technology is simple, it is achieved easily.But prepared by this method
The three-dimensional interconnection structure gone out be only applicable to signal frequency the highest when, when transmission signal frequency and speed
Time higher, this three-dimensional interconnection structure can not meet requirement.So, in order to meet higher rate and higher frequency
The requirement of rate, it is also possible to make multilamellar front metal wiring layer and/multilamellar back metal wiring layer.See reality
Execute example two.
Embodiment two
In the preparation method of the three-dimensional interconnection structure described in embodiment two, including preparing 2 layers of front metal wiring
Layer and 2 layers of back metal wiring layer.It is appreciated that those of ordinary skill in the art are according to 2 layers of front gold of preparation
Belong to wiring layer and the method for 2 layers of back metal wiring layer, it is also possible to obtain three layers and the front of more than three layers
Metal level and the preparation method of back metal wiring layer.Embodiment one and embodiment two have many similarities,
For the sake of brevity, its difference is only described emphatically by the present embodiment, and its similarity refers to reality
Execute the description of example one.
The preparation method of the present embodiment is described in conjunction with Fig. 4 to Fig. 5 (14).The preparation side of this three-dimensional interconnection structure
Method, comprises the following steps:
Step S401 is identical with the step S201 to S203 in embodiment one to step S403, in order to briefly rise
Seeing, be not described in detail at this, specifying information refers to the description of embodiment one.
S404, according to the first front metal wiring layer pattern, above the insulating barrier of described front, sequentially form the
One front metal wiring layer 1041 and the first front dielectric layer 1051:
This step S404 in the present embodiment is with the step S204 difference of embodiment one, the first front
Dovetail groove is not filled full by dielectric layer 1051, only defines a thin layer dielectric layer in the bottom of dovetail groove.Should
Shown in the structural representation such as Fig. 5 (1) that processing procedure is corresponding.
S405, the precalculated position of the first front dielectric layer 1051 formed prodefined opening；
First front dielectric layer 1051 is carried out lithographic patterning and etching, at the first front dielectric layer 1051
Precalculated position formed prodefined opening.Shown in the section of structure such as Fig. 5 (2) that this processing procedure is corresponding.
S406, above the first front dielectric layer 1051, form the second front lighting photoresist 1032, and to this
Two front lighting photoresist 1032 carry out lithographic patterning and etching so that it is form the second front metal wiring layer pattern
And the interconnection pattern being connected with the first front metal wiring layer.Structural representation such as Fig. 5 that this processing procedure is corresponding
(3) shown in.
It should be noted that the interconnection pattern being connected with the first front metal wiring layer and the second front metal cloth
Line layer pattern is disconnected from each other, and is not attached to mutually.
S407, according to the second front metal wiring layer pattern and mutual with what the second front metal wiring layer was connected
Even pattern, formed above described first front dielectric layer 1,051 second front metal wiring layer 1042 and with
The interconnection 52 ' that first front metal wiring layer connects.
It is situated between it should be noted that the first front is filled in the interconnection 51 ' should being connected with the first front metal wiring layer
Prodefined opening on matter layer such that it is able to the first front metal wiring layer 1041 is drawn.It should be noted that
Second metal wiring layer 1042 and the interconnection 51 ' mutually insulated being connected with the first front metal wiring layer, each other
Disconnect.Shown in the structural representation such as Fig. 5 (4) that this processing procedure is corresponding.
S408, mutual with what the first front metal wiring layer 1041 was connected at the second front metal wiring layer 1042
Even 51 ' and the top of the first front dielectric layer 1041 that covered by the second front lighting photoresist 1032 form second
Front dielectric layer 1052:
First, remove the second front lighting photoresist 1032, then use technological means well known in the art second
Interconnection 51 ' that front metal wiring layer 1042 is connected with the first front metal wiring layer and originally by second
The top of the first front dielectric layer 1041 that front lighting photoresist 1032 covers forms the second front dielectric layer 1052,
This second front dielectric layer 1052 can fill whole dovetail groove, makes the front of three-dimensional interconnection structure form one
Substantially smooth surface.Shown in the section of structure such as Fig. 5 (5) that this processing procedure is corresponding.
S409, the precalculated position of the second front dielectric layer 1052 formed prodefined opening, and with metal filled this
Prodefined opening, is formed and metal under the first front salient point of the first front metal wiring layer interconnection and with the respectively
Metal under second front salient point of two front metal wiring layer interconnection:
Second front dielectric layer 1052 is carried out lithographic patterning and etching, at the second front dielectric layer 1052
Precalculated position form prodefined opening, and with this prodefined opening metal filled, formed golden with the first front respectively
Belong to metal under the first front salient point of wiring layer interconnection and with the second front metal wiring layer interconnection second just
Metal under the salient point of face, to facilitate the connection of this three-dimensional interconnection structure and chip.Under first front salient point metal and
Under second front salient point, metal is insulated from each other.Shown in the section of structure such as Fig. 5 (6) that this processing procedure is corresponding.
This processing procedure specifically can also use shallow lake with this prodefined opening metal filled in the way of using plating
Amass or the mode of magnetron sputtering.
S410, grind the back side of described Semiconductor substrate, make each layer be positioned at leaning on above described dovetail groove inclined-plane
Front metal wiring layer bottom nearly described dovetail groove exposes:
The back side of grinding semiconductor substrate 100, the thickness of thinning Semiconductor substrate 100, so that being positioned at trapezoidal
The first front metal wiring layer 1041 and the second front bottom close described dovetail groove above groove 101 inclined-plane
Metal wiring layer 1042 exposes.It is to say, the Semiconductor substrate 100 below dovetail groove is all ground
Remove, and also will be located in the first front metal wiring layer 1041 and of the bottom of dovetail groove 101 further
Two front metal wiring layers 1042 also grind removal, and so original dovetail groove 101 formed just becomes after grinding
Dovetail groove for the second front, bottom dielectric layer 1052.Now, be positioned at above dovetail groove 101 inclined-plane is close
The first front metal wiring layer 1041 bottom this dovetail groove 101 and the second front metal wiring layer 1042 not by
It is initially positioned at Semiconductor substrate 100 below to be blocked, outside being exposed on.The structure that this processing procedure is corresponding is shown
It is intended to as shown in Fig. 5 (7).
S411, at the described front metal wiring layer back of the body formed below of the back side of described Semiconductor substrate and exposure
Face insulating barrier:
The back side of Semiconductor substrate 100 after grinding and the first front metal wiring layer 1041 of exposure and
Two front metal wiring layers 1042 insulating backside formed below layer 106.Structural representation corresponding to this processing procedure is such as
Shown in Fig. 5 (8).
S412, insulating backside layer is carried out lithographic patterning and etching, make described in be positioned at described dovetail groove inclined-plane
On close described dovetail groove bottom described front metal wiring layer again expose:
The conventional techniques means using this area carry out lithographic patterning to insulating backside layer 106, and etch away
It is positioned at the first front metal wiring layer 1041 He bottom the close described dovetail groove on described dovetail groove inclined-plane
Insulating backside layer 106 below second front metal wiring layer 1042, to form prodefined opening, this back side is exhausted
Prodefined opening in edge layer 106 makes to be positioned at first bottom the close described dovetail groove on described dovetail groove inclined-plane
Front metal wiring layer 1041 and the second front metal wiring layer 1042 expose again.The structure that this processing procedure is corresponding
Shown in schematic diagram such as Fig. 5 (9).
S413, at described insulating backside layer 106 and the first front metal wiring layer 1041 and of again exposing
Second front metal wiring layer 1042 back light formed below photoresist 107, is carried out described back light photoresist 107
Lithographic patterning, to form the first back metal wiring layer pattern, this first back metal wiring layer pattern bag
Include four parts of mutually disconnection.
Shown in the structural representation such as Fig. 5 (10) that this processing procedure is corresponding.As shown in Fig. 5 (10), each disconnection
The first back metal wiring layer pattern corresponding with the opening on its above-mentioned insulating backside layer 106, say, that
A first back metal wiring layer figure disconnected formed below at the opening of each insulating backside layer 106
Case.
S414, according to the pattern of the first back metal wiring layer, at described insulating backside layer 106 and again
Described front metal wiring layer the first back metal wiring layer 1081 formed below exposed, at the first back-side gold
Genus wiring layer 1,081 first back side dielectric layer 1091 formed below:
Insulating barrier 106 and the first front metal wiring layer 1041 and second of again exposing are just the most overleaf
The first back metal wiring layer 1081 formed below of face metal wiring layer 1042.This first back metal connects up
Layer 1081 includes four the first back metal wiring sublayers, between each first back metal wiring sublayer mutually
Insulation.The the first back metal wiring layer 1081 formed can fill the opening on insulating backside layer 106, from
And make the first front metal wiring layer 1041 and the second front metal wiring layer 1042 and the first back metal cloth
Line layer 1081 realizes connecting.Then photoresist 107 is removed, then the first back metal wiring layer 1081 He
First back side dielectric layer 1091 formed below of the insulating backside layer 106 originally covered by back light photoresist 107.
Shown in the structural representation such as Fig. 5 (11) that this processing procedure is corresponding.
S415, the precalculated position of the first back side dielectric layer formed prodefined opening:
First back side dielectric layer 1091 is carried out lithographic patterning and etching, at the first back side dielectric layer 1091
Precalculated position formed prodefined opening.At least open in the lower section of the first back metal wiring sublayer of each disconnection
There is a prodefined opening.Shown in the structural representation such as Fig. 5 (12) that this processing procedure is corresponding.
S416, by repeatedly lithographic patterning and metallization process, in the lower section of the first back side dielectric layer 1091
Form the second back metal wiring layer 1082:
This second back metal wiring layer 1082 includes corresponding with the prodefined opening on the first back side dielectric layer
Multiple second back metals wiring sublayers.Mutually disconnect absolutely between each second back metal wiring sublayer
Edge.While forming the second back metal wiring layer 1082, metal can be filled into the first back side dielectric layer 1071
Prodefined opening in, to realize the interconnection between metal level.
Shown in the structural representation such as Fig. 5 (13) that this processing procedure is corresponding.
Specifically, the second back metal wiring layer 1082 formed below at the first back side dielectric layer 1091 is permissible
For:
1, photoresist 6 is used first back side dielectric layer 1091 to carry out lithographic patterning for the first time, alternate
(for the ease of describing and difference, the wiring of each first back metal is sub for two the first back metal wiring sublayers
Layer is expressed as 1081-1,1081-2,1081-3 and 1081-4 with this from left to right.) formed below
One photoetching window.These two alternate first back metal wiring sublayers are 1081-1 and 1081-3.Such as Fig. 5
(13-1) shown in.
2, according to this first photoetching window, at this first back metal wiring sublayer 1081-1 and 1081-3
Second back metal wiring sublayer 1082-1 and 1082-3 formed below.As shown in Fig. 5 (13-2).
3, carry out second time lithographic patterning, connect up sublayer 1081-2 and 1081-4 at the first back metal
Second photoetching window formed below.As shown in Fig. 5 (13-3).
4, according to this second photoetching window, at this first back metal wiring sublayer 1081-2 and 1081-4
Second back metal wiring sublayer 1082-2 and 1082-4 formed below.As shown in Fig. 5 (13-4).
5, remove photoresist and form the structure as shown in Fig. 5 (13).
Forming the second back metal wiring sublayer can in any combination, and its order can also overturn.Various combination
With order all at the row of protection scope of the present invention.
S417, at second back side dielectric layer 1092 formed below of the second back metal wiring layer 1082 and right
Second back side dielectric layer 1092 carries out lithographic patterning and etching, forms prodefined opening, and is somebody's turn to do with metal filled
Prodefined opening, forms metal 92 ' under the salient point of the back side.
It should be noted that the prodefined opening formed on the second back side dielectric layer 1092 and described above the
The position of two back metal wiring sublayers is corresponding.It is to say, in each second back metal wiring sublayer
At least one prodefined opening formed below, in order to drawn.Structural representation corresponding to this processing procedure is such as
Shown in Fig. 5 (14).
It is more than to include two-layer front metal wiring layer and the three-dimensional interconnection structure of two-layer back metal wiring layer
Preparation method.The preparation method of this embodiment in addition to there is the beneficial effect of embodiment one, this enforcement
Owing to being provided with multilamellar front metal wiring layer on the inclined-plane of dovetail groove in three-dimensional interconnection structure prepared by example,
Add the quantity of transmission belt, be conducive to transmitting highdensity signal.Preparation three-dimensional interconnection structure high frequency,
High speed performance is preferable.
In the preparation method of the three-dimensional interconnection structure described in embodiment two, including preparing 2 layers of front metal wiring
Layer and 2 layers of back metal wiring layer.It is appreciated that according to 2 layers of front metal wiring layer of preparation and 2 layers of back side
The method of metal wiring layer, those of ordinary skill in the art can obtain the front gold of three layers and more than three layers
Belong to wiring layer and the preparation method of back metal wiring layer.
Specifically, the side of the three-dimensional interconnection structure of the front metal wiring layer comprising three layers and more than three layers is made
In method, other step in addition to the technique of front can formed on the basis of embodiment one or embodiment two
On the premise of the most constant, repeat to be alternately performed step: form front metal wiring layer pattern, according to this front
Metal line layer pattern forms front metal wiring layer, forms front dielectric layer, and front dielectric layer is carried out light
Carve patterning and form prodefined opening.
Specifically, setting preparation and comprise m(m >=2, m is integer) layer front metal wiring layer three-dimensional mutually
Linking structure, then on the basis of embodiment one, repeat the first circulation, this first circulation includes following
A to D step:
A, (i-1) (i=2,3 ..., m-1) form the i-th front lighting photoresist above the dielectric layer of front, and right
This i-th front lighting photoresist carries out lithographic patterning, to form the i-th front metal wiring layer pattern, wherein, institute
State, on the dielectric layer of (i-1) front, there is prodefined opening.
B, according to this i-th front metal wiring layer pattern, above the dielectric layer of (i-1) front formed i-th
Front metal wiring layer:
C, above the i-th front metal wiring layer, form the i-th front dielectric layer:
D, the i-th front dielectric layer is carried out lithographic patterning formed prodefined opening:
By repeating the first circulation, i.e. step A to D, it is prepared for including the wiring of m layer front metal
The three-dimensional interconnection structure of layer.Owing to when forming the i-th front metal wiring layer, meeting just by (i-1) simultaneously
The prodefined opening of face dielectric layer is filled, and forms the interconnection structure of upper and lower metal wiring layer.(i-1) front gold
Belong to wiring layer and the i-th front metal wiring layer achieves interconnection by this interconnection structure.
Based on above-mentioned teaching, make the three-dimensional interconnection knot of the back metal wiring layer comprising three layers and more than three layers
In the method for structure, it is also possible to embodiment one or on the basis of, formed except back process in addition to other walk
On the premise of the most constant, repeat to be alternately performed step: form back metal wiring layer, form back side dielectric layer,
Back side dielectric layer is carried out lithographic patterning and forms prodefined opening.Specifically, set preparation and comprise n(n >=3,
N is integer) three-dimensional interconnection structure of layer back metal wiring layer, then on the basis of embodiment one, weight
Performing the second circulation again, this second circulation includes step a to d:
A, (j-1) back side dielectric layer jth formed below (j=2,3 ..., n-1) layer back metal wiring
Layer pattern:
B, according to this jth layer back metal wiring layer pattern formed jth back metal wiring layer；
C, at the jth back side formed below dielectric layer of jth back metal wiring layer:
D, jth back side dielectric layer is carried out lithographic patterning and etching formed prodefined opening:
By repeated execution of steps a to d, it is prepared for including the three-dimensional interconnection knot of n-layer back metal wiring layer
Structure.Owing to when forming jth back metal wiring layer, making a reservation for (j-1) back side dielectric layer simultaneously
Opening is filled, and forms the interconnection structure of upper and lower metal wiring layer.(j-1) back metal wiring layer and jth
Back metal wiring layer achieves interconnection by the interconnection structure of this upper and lower metal wiring layer.
Based on same design, it is also possible to preparation includes m(m >=3, and m is integer) wiring of layer front metal
Layer and n(n >=3, n is integer) three-dimensional interconnection structure of layer back metal wiring layer.Specifically can be repeatedly
Repeated execution of steps first circulates and the second circulation, thus defines m layer front metal wiring layer and n-layer
The three-dimensional interconnection structure of back metal wiring layer.
In the present invention, the number of plies of front metal wiring layer and/or back metal wiring layer is not construed as limiting,
As long as its each at least layer of metal wiring layer can realize the inventive concept of the present invention, solving the present invention to solve
Technical problem certainly.Specifically, as described in embodiment one, this three-dimensional interconnection structure can only include one layer
Front metal wiring layer and one layer of back metal wiring layer, it is also possible to include that one layer of front metal wiring layer is with many
Layer back metal wiring layer, it is also possible to include multilamellar front metal wiring layer and one layer of back metal wiring layer,
Certainly this three-dimensional interconnection structure can also include multilamellar front metal wiring layer and multilamellar back metal wiring layer.
In order to take into account preparation technology and the performance of three-dimensional interconnection structure, simultaneously in order to prevent three-dimensional interconnection structure
The reasons such as warpage and holding front, skewed slot and backside interconnection structure seriality, preferred technical scheme is front
Metal wiring layer is identical with the number of plies of back metal wiring layer with the number of plies.
Preparation method based on above-described embodiment one, present invention also offers the enforcement of a kind of three-dimensional interconnection structure
Example, detailed in Example three.
Embodiment three
Seeing Fig. 3 (11), this three-dimensional interconnection structure includes,
Semiconductor substrate 100, described Semiconductor substrate 100 includes relative front and back, described partly leads
Being formed through the trapezoidal hole 101 of front and back on body substrate, described trapezoidal hole is in described Semiconductor substrate
The opening in 100 fronts is more than the opening at described Semiconductor substrate 100 back side；
It should be noted that form dovetail groove by selective etch in the front of Semiconductor substrate, when completing
After the technique of front, grind the thickness of thinning described Semiconductor substrate 100 thus define trapezoidal hole structure.
It is positioned at the front above described Semiconductor substrate 100 upper front and described trapezoidal hole 101 inclined-plane exhausted
Edge layer 102；Owing to not there is front insulating barrier 102 in the bottom of trapezoidal hole 101, so, insulate in front
Layer 102 includes two parts disconnected.
It is positioned at the first front metal wiring layer 1041 above described front insulating barrier 102；Owing to front is exhausted
Edge layer 102 includes two parts disconnected, so the first front metal wiring layer 1041 on this is also
Including two the first front metal wiring sublayers disconnected.
It is positioned at the first front dielectric layer 1051 above the first front metal wiring layer 1041, wherein, institute
The pre-position stating the first front dielectric layer 1051 is provided with prodefined opening, is filled with in this prodefined opening
Metal forms metal 51 ' under the salient point of front.Under this front salient point, metal 51 ' is for by the first front metal cloth
Line layer is drawn and realizes and the welding of chip.This precalculated position is positioned at except trapezoidal hole any position other than over
Put.But realizing being connected with chip for convenience, this precalculated position can be corresponding with the solder joint on chip.
Additionally, trapezoidal hole 101 is filled up by this first front dielectric layer 1051, make the front shape of three-dimensional interconnection structure
Become a plane the most smooth.
It is positioned at the insulating backside layer 106 of described Semiconductor substrate 100 lower rear；Described insulating backside layer 106
Through lithographic patterning, will be located in the front metal wiring bottom the close described trapezoidal hole on trapezoidal hole inclined-plane
Insulating backside layer 106 etching below Ceng is removed, and the precalculated position on insulating barrier 106 defines out overleaf
Mouthful, so that described first bottom the close described trapezoidal hole 101 being positioned on described dovetail groove 101 inclined-plane
Front metal wiring layer 1041 is not covered by described insulating backside layer 106；
Be positioned at described insulating backside layer 106 and described in be positioned on described trapezoidal hole 101 inclined-plane close described
The first back metal wiring layer 1081 below described front metal wiring layer 1041 bottom dovetail groove 101
And it is positioned at the first back side dielectric layer 1091 below described first back metal wiring layer 1081.
Wherein, the first back side dielectric layer 1,091 first front metal wiring layer 1081 is divided into two independent
First back metal wiring sublayer, mutually insulated between two the first back metal wiring sublayers, each first
Back metal wiring sublayer also fills up the opening on insulating backside layer 106, to realize the first front metal wiring
Layer 1041 and the electrical connection of the first back metal wiring layer 1081.
The pre-position of described first back side dielectric layer 1091 is provided with metal 91 ' under the salient point of the back side, uses
In realizing the interconnection with substrate.
The first front metal wiring layer 1041 and the first back metal wiring layer 1081 in embodiment one pass through
The the first front metal wiring layer being positioned on dovetail groove inclined-plane couples together.It is positioned at first on dovetail groove inclined-plane
Front metal wiring layer is equivalent to the first front metal wiring layer 1041 and the first back metal wiring layer 1081
Transmission belt.Due to the first front metal wiring layer 1041, transmission belt and the first back metal wiring layer
The material of 1081 is identical, and structure is also more or less the same, so, signal is in transmitting procedure, and transient impedance becomes
Change little, so make to cause signaling reflex the least due to impedance mismatch, thus cause this three-dimensional interconnection
The high speed of structure, high frequency performance are preferable.
Preparation method based on above-described embodiment two, present invention also offers another three-dimensional interconnection structure
Embodiment, detailed in Example four.
Embodiment four
Three-dimensional interconnection structure described in this embodiment includes 2 layers of front metal wiring layer and 2 layers of back metal cloth
Line layer.Having many similarities with the three-dimensional interconnection structure of embodiment three, it only difference is that front metal
Wiring layer is different with the number of plies of back metal wiring layer.For the sake of brevity, the present embodiment is emphatically to front gold
The position, the annexation that belong to wiring layer and back metal wiring layer and other Rotating fields are described.
As shown in Fig. 5 (14), the three-dimensional interconnection structure described in the present embodiment includes the first front metal wiring
Layer 1041, it is positioned at the first front dielectric layer 1051 on the first front metal wiring layer 1041, is positioned at first
The second front metal wiring layer 1042 on front dielectric layer 1051.Wherein, the first front dielectric layer 1051
On be formed with prodefined opening, and this prodefined opening in be filled with metal, formed and the first front metal wiring layer
1041 interconnection structures 51 ' connected.Wherein, the interconnection structure being connected with the first front metal wiring layer 1041
51 ' and second mutually insulateds between front metal wiring layer 1042.
It is positioned at the second front metal wiring layer 1042 and the interconnection being connected with the first front metal wiring layer 1041
The second front dielectric layer 1052 on structure 51 '.Wherein, in the pre-determined bit of the second front dielectric layer 1052
Install and be equipped with prodefined opening and in this prodefined opening, be filled with metal, form metal 52 ' under the salient point of front.
It is connected with chip by metal 52 ' under the salient point on the second front dielectric layer 1052.
Three-dimensional interconnection structure described in the present embodiment also includes first back side being positioned at below insulating backside layer 106
Metal wiring layer 1081, be positioned at the first back side dielectric layer 1091 under the first back metal wiring layer 1081,
It is positioned at the second back metal wiring layer 1082 under the first back side dielectric layer 1091 and is positioned at second back side
The second back side dielectric layer 1092 under metal wiring layer 1082.Wherein, respectively at the first back side dielectric layer
1091 and second the precalculated position of back side dielectric layer 1092 be formed with prodefined opening, and make a reservation for metal filled this
Opening, is formed and the first back metal wiring layer 1081 in the prodefined opening of the first back side dielectric layer 1091
The interconnection structure connected, forms metal under the salient point of the back side in the prodefined opening of the second back side dielectric layer 1092
92 ', it is connected with substrate by metal 92 ' under the back side salient point on the second back side dielectric layer 1092.
It should be noted that in this embodiment, when grinding the back side of thinning Semiconductor substrate 100, need
The first front metal wiring layer 1041 and the second front metal wiring layer above trapezoidal hole inclined-plane be will be located in
1042 come out, in order to realize the electrical connection of front metal wiring layer and back metal wiring layer.So,
When grinding, need to will be located in the first front metal wiring layer bottom trapezoidal hole and the wiring of the second front metal
Layer grinds away.Thus make the first the most complete front metal wiring layer 1041 and the second front metal cloth
Line layer 1042 is cut off, and is respectively divided into two front metal sublayers.Formed these four front metal sublayers it
Between be separate.
The insulating backside layer 106 of the present embodiment is formed with 4 prodefined openings, in order to by the first front metal
Two sub-metal levels of wiring layer 1041 and two sub-metal levels of the second front metal wiring layer 1042 are drawn
Realize being connected with the first back metal wiring layer 1081 respectively.In order to keep above-mentioned 4 front metals wiring
The independence of layer, connected first back metal wiring layer 1081 is also classified into four the first back metal
Layer.Cut off realization by the first back side dielectric layer 1091 between these four the first back metal sublayers mutually to disconnect
Insulation.
Identical with the first back metal wiring layer 1081, the second back metal wiring layer 1082 is also by second back of the body
Face dielectric layer 1092 cuts off four the second back metal wiring sublayers being divided into disconnection.
Wherein, the interconnection structure being connected with the first back metal wiring layer 1081 and the second back metal wiring layer
1082 mutually insulateds.
As it was previously stated, in the present invention, to front metal wiring layer and/or the number of plies of back metal wiring layer
It is not construed as limiting, as long as its each at least layer of metal wiring layer can realize the inventive concept of the present invention, solves
The technical problem to be solved in the present invention.Specifically, as described in embodiment three, this three-dimensional interconnection structure is permissible
Only include one layer of front metal wiring layer and one layer of back metal wiring layer, it is also possible to include one layer of front metal
Wiring layer and multilamellar back metal wiring layer, it is also possible to include multilamellar front metal wiring layer and one layer of back-side gold
Belonging to wiring layer, this three-dimensional interconnection structure includes multilamellar front metal wiring layer and the wiring of multilamellar back metal certainly
Layer.
When three-dimensional interconnection structure includes multilamellar front metal wiring layer, adjacent two layers front metal wiring layer is i.e.
I-th front metal wiring layer and i+1 layer front metal wiring layer are by the i-th front dielectric layer therebetween
Interconnection structure realizes connecting.For by i-th-1 front metal wiring layer draw interconnection be used for the i-th front
The interconnection mutually insulated that metal wiring layer is drawn.
Equally, when three-dimensional interconnection structure includes multilamellar back metal wiring layer, adjacent two layers back metal cloth
Line layer that is i-th back metal wiring layer and i+1 layer back metal wiring layer are by the i-th back side medium therebetween
Interconnection structure on layer realizes connecting.For interconnection that jth-1 back metal wiring layer is drawn be used for
The interconnection mutually insulated that j back metal wiring layer is drawn.
The three-dimensional interconnection structure that the embodiment of the present invention provides is also referred to as TSS(Through Silicon Strip) knot
Structure., in order to the electric property of TSS structure is described, by traditional TSV structure and there is double-deck front metal cloth
The TSS structure of line compares, and metal wiring layer all uses microstrip transmission lines, in order to meet high frequency performance,
TSV uses with backflow TSV via.A diameter of 30 μm of TSV, interposer thickness is 150 μm, its
His primary structure and material information are shown in Table shown in I.TSS structure microstrip transmission line width is 9 μm, design spy
Property impedance is 51.71 Ω.
Table I model main material, structural parameters table
The biography of three kinds of different vertical interconnection structures is obtained by full-wave electromagnetic field simulation software HFSS modeling and simulating
Defeated characteristic, such as Fig. 6 and Fig. 7.Tradition TSV structure transmission characteristic is poor, and during 150GHz, S12 is-5.7dB.
Novel TSS structure transmission characteristic is preferable, and during 150GHz, S12 is-2.56dB.Along with increasing of frequency, novel
TSS S12 curve is significantly better than tradition TSV structure, and between 20GHz to 150GHz, in frequency band, both differ
1dB to 3dB.Owing to low-resistance silicon dielectric loss is relatively big, and exist due to impedance discontinuity produce anti-
Penetrate, it is clear that tradition TSV structure performance affects bigger when high frequency.Owing to novel TSS structure is interior in order to realize
Wall photoetching have employed anisotropic etch process, and the passband interior angle formed is about the acute angle of 57 degree, such as figure
Shown in 8.Electromagnetic wave, this does not connects through the acute angle of 57 degree when passband inwall transmission line propagates to RDL layer
Continue structure influence TSS structure transmission characteristic, but overall performance is better than the performance of traditional TSV structure.
Such as Fig. 8, the TSS dovetail groove that anisotropic etching is formed is the key affecting interconnection density, and contrast passes
System TSV in the area that the length of side is 432 μm and the length of side be 236 μm area in interconnect
Line number, illustrates two kinds of structure interconnection density problems.During conventional TSV pair of employing (such as: bore dia/hole
Limit spacing, 30 μm/30 μm), the length of side be 432 μm area in can be distributed 24 to (signal,
Ground hole) or 49 signal line (low frequency does not consider TSV hole of refluxing).But in order to ensure whole wafer
Reliability, TSV area is less than 10%, the most most of TSV use such as 30 μm/120 μm row
Cloth.And when using TSS (9 μm/9 μm), the length of side be 236 μm area in can be distributed to
Few 52 microstrip lines, can be more during employing multilamellar vertical interconnecting structure.Table II summarizes TSV based on low-resistance silicon
Structure and TSS structure performance comparison situation, analyze it is known that novel TSS structure is a kind of highly dense interconnection
Structure, can realize high-performance, fine pith chip package.
Table II TSV structure based on low-resistance silicon and TSS structure performance comparison
It is to be understood that, although this specification is been described by according to embodiment, but the most each embodiment is only
Comprising an independent technical scheme, this narrating mode of description is only for clarity sake, this area
Technical staff should be using description as an entirety, and the technical scheme in each embodiment can also be through suitably
Combination, forms other embodiment that it will be appreciated by those skilled in the art that.
The above is only the preferred embodiment of the present invention, it is noted that common for the art
For technical staff, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (9)
1. the preparation method of a three-dimensional interconnection structure, it is characterised in that described three-dimensional interconnection structure is at least
Including the first front metal wiring layer and the first back metal wiring layer, described preparation method includes,
Dovetail groove is formed in the front of Semiconductor substrate；
Front insulating barrier is formed above described Semiconductor substrate front and described dovetail groove；
Above the insulating barrier of described front, form the first front lighting photoresist, and described first front lighting photoresist is entered
Row lithographic patterning, to form the first front metal wiring layer pattern；
According to described first front metal wiring layer pattern, above the insulating barrier of described front, form the first front
Metal wiring layer；
Forming the first front dielectric layer above described first front metal wiring layer, wherein, described first just
Multiple prodefined opening it is formed with on the dielectric layer of face；
Use metal filled described prodefined opening, with the front metal wiring layer formed and below the dielectric layer of front
The interconnection of connection；
Grinding the back side of described Semiconductor substrate, make to be positioned at above described dovetail groove inclined-plane is close described trapezoidal
The described front metal wiring layer of trench bottom exposes, until the front metal wiring layer bottom dovetail groove all goes
Remove；
Described Semiconductor substrate lower rear after grinding forms insulating backside layer；
Described insulating backside layer is carried out lithographic patterning, and etches described insulating backside according to photoengraving pattern
Layer, to form prodefined opening on described insulating backside layer, it is oblique that described prodefined opening makes to be positioned at described dovetail groove
Described front metal wiring layer bottom close described dovetail groove above face exposes；
The front metal wiring layer back side formed below above the inclined-plane of described insulating backside layer and exposure
Photoresist, and described back light photoresist is carried out lithographic patterning, to form the first back metal wiring layer figure
Case；Wherein, described first back metal wiring layer pattern includes multiple breaking part；
According to described first back metal wiring layer pattern, on the inclined-plane of described insulating backside layer and exposure
The front metal wiring layer first back metal wiring layer formed below of side；Described first back metal wiring layer
The first back metal wiring sublayer including multiple disconnections；Each described first back metal wiring sublayer and institute
State on insulating backside layer prodefined opening be connected and fill the prodefined opening on the insulating backside layer of connection；
At described first back metal wiring layer the first back side dielectric layer formed below, described first back side medium
Multiple prodefined opening it is formed with on Ceng；One is at least had below each described first back metal wiring sublayer
Individual described prodefined opening；
With back metal wiring above the formation of metal filled described prodefined opening and described back side dielectric layer
The interconnection that layer connects.
Preparation method the most according to claim 1, it is characterised in that described three-dimensional interconnection structure bag
Include m layer front metal wiring layer and/or n-layer back metal wiring layer, described formation the first front metal cloth
After line layer and the first front dielectric layer, before described grinding semiconductor substrate back, also include, m-1
First circulation, described first circulation includes,
The i-th front lighting photoresist is formed above the i-th-1 front dielectric layer, and to described i-th front lighting photoresist
Carry out lithographic patterning, with formed the i-th front metal wiring layer pattern and with the i-th-1 front metal wiring layer
The interconnection pattern connected；Wherein, described i-th-1 front dielectric layer has prodefined opening；Described i-th just
Face metal line layer pattern and the described interconnection pattern being connected with the i-th-1 front metal wiring layer mutually disconnect；
According to described i-th front metal wiring layer pattern and the interconnection network that is connected with the i-th-1 front metal wiring layer
Case, formed above the i-th-1 front dielectric layer the i-th front metal wiring layer and with the i-th-1 front metal wiring layer
The interconnection connected；
Formed at described i-th front metal wiring layer with above the interconnection that the i-th-1 front metal wiring layer is connected
I-th front dielectric layer；
Described i-th front dielectric layer is carried out lithographic patterning and etching forms prodefined opening；
And/or, n-1 second circulation, described second circulation includes,
After the first back metal wiring layer the first back side dielectric layer formed below, also include,
Lithographic patterning is carried out, to form jth back metal wiring layer pattern above the dielectric layer of jth-1 back side；
Wherein, described jth back metal wiring layer pattern includes multiple breaking part；
According to described jth layer back metal wiring layer pattern, in described jth-1 back side dielectric layer jth formed below
Back metal wiring layer: described jth back metal wiring layer includes jth back metal wiring of multiple disconnection
Layer；
In the jth back side formed below dielectric layer of jth back metal wiring layer, shape on the dielectric layer of the described jth back side
Become to have multiple prodefined opening；
Wherein, m >=2, n >=2,2≤i≤m, 2≤j≤n.
Preparation method the most according to claim 2, it is characterised in that described at described jth-1 back side
Dielectric layer jth formed below back metal wiring layer, specifically, by repeatedly lithographic patterning and metallization
Form jth back metal wiring layer.
4. according to the preparation method described in any one of claim 1-3, it is characterised in that described front gold
Belonging to the metal line on wiring layer and/or on described back metal wiring layer is single ended line, difference connecting line.
5. according to the preparation method described in any one of claim 1-3, it is characterised in that described front gold
Belong to the metal line on wiring layer and/or described back metal wiring layer be common interconnection line, co-planar waveguide,
The co-planar waveguide microstrip line on microstrip line, band ground or strip line.
6. a three-dimensional interconnection structure, it is characterised in that described three-dimensional interconnection structure is just at least including first
Face metal wiring layer and the first back metal wiring layer, it includes,
Semiconductor substrate, described Semiconductor substrate includes relative front and back；In described Semiconductor substrate
Having the trapezoidal hole running through front and back, the described trapezoidal hole opening in described Semiconductor substrate front is more than
Opening at the described Semiconductor substrate back side；
It is positioned at the front insulating barrier above described Semiconductor substrate upper front and described trapezoidal hole inclined-plane；
It is positioned at the first front metal wiring layer above the insulating barrier of described front, described first front metal wiring
Layer includes two the first front metal wiring sublayers disconnected；
It is positioned at the first front dielectric layer above described first front metal wiring layer；Wherein, described first just
Include multiple prodefined opening on the dielectric layer of face, be formed in described prodefined opening for by described first front gold
Belong to the interconnection that wiring layer is drawn；Wherein, the outermost front dielectric layer of described three-dimensional interconnection structure it is positioned at also
Fill described trapezoidal hole；
It is positioned at the insulating backside layer below described Semiconductor substrate lower rear and described front dielectric layer, institute
State the front metal wiring layer bottom the insulating backside layer close described trapezoidal hole on described trapezoidal hole inclined-plane
Opening formed below；
Be sequentially located at described insulating backside layer and described in be positioned at the close described ladder on described trapezoidal hole inclined-plane
The first back metal wiring layer below front metal wiring layer bottom shape hole and the first back side dielectric layer；
Wherein, described first back metal wiring layer includes first back of the body that at least two disconnects, mutually insulated
Face metal line sublayer, each described first back metal wiring sublayer also fills up on described insulating backside layer
Opening is also connected with described front metal wiring layer by the opening on described insulating backside layer；
It is formed with prodefined opening on described first back side dielectric layer, is formed in described prodefined opening for by institute
State the interconnection that the first back metal wiring layer is drawn, and below each described first back metal wiring sublayer
It is formed with an interconnection；
Wherein, described three-dimensional interconnection structure includes m layer front metal wiring layer and m layer front dielectric layer；
Wherein, i+1 front metal wiring layer is positioned at the top of the i-th front dielectric layer, described i-th front
It is provided with multiple prodefined opening on dielectric layer, is formed in described prodefined opening for by the i-th-1 front metal
Wiring layer draw interconnection, wherein, for by i-th-1 front metal wiring layer draw interconnection be used for by
The interconnection mutually insulated that i-th front metal wiring layer is drawn；
Wherein, m >=2,2≤i≤m.
Three-dimensional interconnection structure the most according to claim 6, it is characterised in that described three-dimensional interconnection is tied
Structure includes n-layer back metal wiring layer and n-layer back side dielectric layer；
Wherein, jth back side dielectric layer is positioned at the lower section of jth back metal wiring layer, described jth back-side gold
Belong to wiring layer and include that multiple disconnection, mutually insulated jth back metal connects up sublayer；
Be provided with multiple prodefined opening on the dielectric layer of the described jth back side, be formed in described prodefined opening for
The interconnection drawn by jth back metal wiring layer, wherein, for drawing jth-1 back metal wiring layer
Interconnection with for by jth back metal wiring layer draw interconnection mutually insulated；
Wherein, n >=2,2≤j≤n.
Three-dimensional interconnection structure the most according to claim 6, it is characterised in that described front metal cloth
Metal line on line layer and/or on described back metal wiring layer is single ended line, difference connecting line.
Three-dimensional interconnection structure the most according to claim 6, it is characterised in that described front metal cloth
Metal line on line layer and/or described back metal wiring layer is common interconnection line, co-planar waveguide, micro-strip
The co-planar waveguide microstrip line on line, band ground or strip line.
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| CN1247635A (en) * | 1996-12-19 | 2000-03-15 | 艾利森电话股份有限公司 | Via structure |
| CN203466186U (en) * | 2013-09-29 | 2014-03-05 | 中国科学院微电子研究所 | Three-dimensional interconnection structure |
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| CN1247635A (en) * | 1996-12-19 | 2000-03-15 | 艾利森电话股份有限公司 | Via structure |
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