CN103346144A - Artificial magnetic conductor shaped like Chinese character 'jing' and used for 60GHz on-chip antenna and implement method - Google Patents
Artificial magnetic conductor shaped like Chinese character 'jing' and used for 60GHz on-chip antenna and implement method Download PDFInfo
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Abstract
Provided is an artificial magnetic conductor shaped like a Chinese character 'jing' and used for a 60GHz on-chip antenna. The artificial magnetic conductor can be used on a millimeter wave integrated circuit, waveguide transmission, the on-chip antenna and the like. The artificial magnetic conductor is manufactured through a CMOS integrated circuit process, and is composed of a silicon substrate, a silicon oxide buffering layer, a metal layer, a silicon oxide insulation layer and an upper functional circuit layer, and the metal layer is manufactured to be of a distributed-type structure shaped like the Chinese character 'jing'. The artificial magnetic conductor is applied to the design of the millimeter wave integrated circuit and particularly the integrated on-chip antenna, effective isolation of the antenna and the silicon substrate is achieved, and incident electromagnetic waves of the antenna are prevented from entering the silicon substrate. The artificial magnetic conductor shaped like the Chinese character 'jing' and used for the 60GHz on-chip antenna serves as an isolation layer between the millimeter wave on-chip radiating antenna and the silicon substrate, the structure is simple, the CMOS process is compatible, the artificial magnetic conductor is applied to the 60GHz on-chip antenna, and loss of signals of the incident electromagnetic waves of the antenna by the silicon substrate can be reduced.
Description
Technical field
The present invention relates to millimetre integrated circuit and on-chip antenna technical field, particularly a kind of 60 GHz on-chip antennas are with artificial magnetic conductor structure and its implementation.
Background technology
60 GHz frequency band short-distance wireless communications make wireless personal local area network network (WPANs) produce revolutionary breakthrough, at wireless consumption electronic product, the big capacity media file transmission of high-resolution, moving distributing calculates, and fields such as wireless game and quick transmission super large file have the great market prospect.Therefore the free space wavelength of 60 GHz frequencies has only 5 millimeters, adopts the antenna of small size just can realize the transmitting-receiving of wireless data very much.Therefore, integrated low-noise amplifier on monolithic integrated circuit chip, frequency mixer, frequency converter, wave detector, modulator, transceiver and antenna are realized the radio communication of 60 gigahertz band, can effectively reduce the volume of radio communication receive-transmit system, make its compact conformation, machining reproducibility is good, the reliability height.
Present 60 GHzs and millimetre integrated circuit mainly adopt the GaAs manufacturing process, complex process not only, and the cost height, price is expensive, and arsenic (As) is a kind of poisonous material, need protect.Adopt the CMOS integrated circuit technology to realize 60 GHzs and millimetre integrated circuit, can reduce cost greatly, improve output.But CMOS technology is done substrate with silicon materials, and silicon substrate is not the material that insulate fully, has certain conductivity, can not reach desirable isolation effect when particularly being operated in high frequency, can produce leakage current, obviously reduces radiation efficiency and the gain of on-chip antenna.Therefore the electromagnetic wave loss that solves silicon substrate is the key issue of CMOS millimetre integrated circuit and on-chip antenna development.
Over nearly 10 years, industry is devoted to solve silicon substrate loss problem always, has proposed proton injection method, methods of micro-mechanics, resin bed insulation method and artificial magnetic conductor method etc. once.
Artificial magnetic conductor structure is exactly to add a separator between silicon substrate and functional circuit layer, reduces silicon substrate to the loss of frequency electromagnetic waves.Its buffer action is because the reflected phase will band gap properties of artificial magnetic conductor, when incident wave frequency during near the resonance frequency of artificial magnetic conductor structure, the surface impedance of artificial magnetic conductor structure is very high, its reflected wave and incident wave phase difference were 0 when therefore plane wave incided artificial magnetic conductor surface, when the incident electromagnetic wave frequency makes artificial magnetic conductor surface impedance equal free space impedance, the phase difference of incident wave and reflected wave is ± 90 °, design artificial magnetic conductor structure, make the phase difference of its incident wave and reflected wave between ± 90 °, just can realize isolation to incident electromagnetic wave.
Artificial magnetic conductor CMOS technique compatible, cost are low, simple in structure, are a kind of very promising technology.
Summary of the invention
The objective of the invention is at 60 GHz millimetre integrated circuits and on-chip antenna design, solve silicon substrate electromagnetic wave loss problem, provide a kind of groined type for 60 GHz on-chip antennas artificial magnetic conductor, realize the insulation of on-chip circuit and silicon substrate, improve the job stability of on-chip circuit and efficient and the gain of on-chip antenna.
The artificial magnetic conductor of groined type for 60 GHz on-chip antennas provided by the invention comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer stack gradually making from top to bottom.Below silicon substrate is positioned at, cover one deck silica resilient coating above it, evaporation layer of metal layer on the silica resilient coating is made distributed groined type structure, cover one deck insulating layer of silicon oxide on metal level, the top of insulating layer of silicon oxide is the functional circuit layer.
Described artificial magnetic conductor adopts traditional CMOS technology to realize.
Described metal level is made by the first metal layer of CMOS technology.
Described metal level is divided into N * N unit, the span of N is 6 to 11, each unit all is to be the square of the length of side with 200 microns, foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between per two parallel line of rabbet joint is 30 microns.
Described silicon substrate thickness satisfies described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns during to 320 micrometer ranges.
Its thickness of described insulating layer of silicon oxide is 1.3 microns.
The implementation method of the artificial magnetic conductor of intersecting parallels provided by the invention, pass through following step successively:
The first, the silicon chip of preparing to have epitaxial loayer is done the silicon substrate 5 of artificial magnetic conductor;
The second, use the field oxidation technology growing silicon oxide resilient coating 4 of CMOS above the silicon substrate 5, as the following dielectric layer of artificial magnetic conductor;
Three, silicon chip is annealed, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, utilize the first metal layer evaporated metal layer 3 of CMOS technology then;
Four, the photoetching metal level 3, form intersecting parallels lamellule 7 cyclic array structures 9, as shown in Figures 2 and 3, make lamellule 7 at metal level 3, etch intersecting parallels fluting 8 on lamellule 7; The lamellule of each fluting links to each other with silicon substrate 5 and ground connection by via hole 6.
Five, carry out chemical vapour deposition (CVD) on metal level 3, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the last dielectric layer of artificial magnetic conductor.
Six, utilize the functional circuit layer 1 above the insulating layer of silicon oxide 2 to make waveguide device and on-chip antenna.
The present invention is based on the CMOS integrated circuit technology, in the EDA of special use design software, determine size and the position of silica resilient coating 4, lamellule 7, via hole 6, insulating layer of silicon oxide 2 and cyclic array structure 9, adopt full method for customizing design, based semiconductor technology realizes.
?
Advantage of the present invention and good effect:
60 GHz on-chip antennas provided by the invention are with the artificial magnetic conductor of intersecting parallels, have the reflected phase will band gap properties, the central task frequency is 60 GHzs, and bandwidth has reached 20.2 GHzs, relative bandwidth is big, and antenna integrated application has tangible competitive advantage on 60 GHz sheets.Artificial magnetic conductor provided by the invention is simple in structure, and area is little, each cellar area only for 200 microns be the little square of the length of side, complete compatible existing CMOS technology.
Description of drawings
Fig. 1 is the artificial magnetic conductor structure chart of a kind of groined type for 60 GHz on-chip antennas;
Fig. 2 is artificial magnetic conductor metal level lamellule 7 cellular construction figure;
Fig. 3 is artificial magnetic conductor array 9 structure charts of the N * N intersecting parallels of periodic arrangement;
Fig. 4 is the artificial magnetic conductor structure chart that has prepared on-chip antenna at the functional circuit layer.
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Embodiment
Embodiment 1:
As shown in Figure 1, the artificial magnetic conductor of the groined type for 60 GHz on-chip antennas provided by the invention, concrete structure comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer stack gradually making from top to bottom.Below silicon substrate is positioned at, cover one deck silica resilient coating above it, evaporation layer of metal layer on the silica resilient coating is made distributed groined type structure, cover one deck insulating layer of silicon oxide on metal level, the top of insulating layer of silicon oxide is the functional circuit layer.
The artificial magnetic conductor of intersecting parallels adopts traditional CMOS technology to realize.
Silicon substrate thickness satisfies described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns during to 320 micrometer ranges.
The artificial magnetic conductor metal level of intersecting parallels is made by the first metal layer of CMOS technology, and this metal level is made into distributed groined type structure.
Whole metal level is divided into N * N unit, the span of N is 6 to 11, each unit all is to be the square of the length of side with 200 microns, foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between per two parallel line of rabbet joint is 30 microns.
Its thickness of insulating layer of silicon oxide is 1.3 microns.
Embodiment 2:
Provided by the invention for the implementation method of 60 GHz on-chip antennas with the artificial magnetic conductor of intersecting parallels, pass through following step successively:
The first, the silicon chip of preparing to have epitaxial loayer is done the silicon substrate 5 of artificial magnetic conductor;
The second, use the field oxidation technology growing silicon oxide resilient coating 4 of CMOS above the silicon substrate 5, as the following dielectric layer of artificial magnetic conductor;
Three, silicon chip is annealed, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, utilize the first metal layer evaporated metal layer 3 of CMOS technology then;
Four, the photoetching metal level 3, form intersecting parallels lamellule 7 cyclic array structures 9, as shown in Figures 2 and 3, make lamellule 7 at metal level 3, etch the intersecting parallels fluting on lamellule 7; The lamellule of each fluting links to each other with silicon substrate 5 and ground connection by via hole 6.
Five, carry out chemical vapour deposition (CVD) on metal level 3, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the last dielectric layer of artificial magnetic conductor.
Six, utilize the functional circuit layer 1 above the insulating layer of silicon oxide 2 to make waveguide device and on-chip antenna.
Embodiment 3:
As shown in Figure 3, the 60 GHz on-chip antennas that are used for that N * N periodic structure is arranged are implemented as follows with the artificial magnetic conductor of intersecting parallels:
Get N=7, that realizes that 7 * 7 periodic structures arrange is used for 60 GHz on-chip antennas with the artificial magnetic conductor of intersecting parallels.
Employing has the silicon chip of epitaxial loayer as the silicon substrate 5 of the artificial magnetic conductor of intersecting parallels, and the thickness of silicon substrate 5 is 300 microns.
Above the silicon substrate 5 with field oxidation technology growing silicon oxide resilient coatings 4 of CMOS, with the method for photoetching determine the size of silica resilient coating 4 be with 1.84 millimeters be the square of the length of side, as the following dielectric layer of the artificial magnetic conductor of intersecting parallels.
Silicon chip is carried out annealing in process, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, utilize the first metal layer evaporated metal layer 3 of CMOS technology then, utilizing 7 * 7 of the method formation of photoetching is the square lamellule 7 of the length of side with 200 microns, gap between each lamellule is 55 microns, 7 * 7 lamellules 7 are pressed the ranks periodic and are arranged, and form the square formation of 7 * 7 lamellules as Fig. 3.
Described lamellule 7, etch intersecting parallels fluting 8 above, each intersecting parallels fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, centre distance between per two parallel line of rabbet joint is 30 microns, and the lamellule 7 of each fluting links to each other with silicon substrate 5 and ground connection by via hole 6.
Carry out the chemical vapour deposition (CVD) oxidation on metal level 3, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the last dielectric layer of artificial magnetic conductor, and thickness is 1.3 microns.
The central task frequency of the artificial magnetic conductor of realizing of 7 * 7 matrix structure intersecting parallels is 60 GHzs, bandwidth 20.5 GHzs, relative bandwidth 34%.
?
Embodiment 4:
Described a kind of 60 GHz on-chip antennas are as follows with the application example of the artificial magnetic conductor of intersecting parallels:
As shown in Figure 4, a kind of 60 GHz on-chip antennas of 6 * 6 periodic structures arrangement are implemented as follows with the artificial magnetic conductor array of intersecting parallels:
Employing has the silicon chip of epitaxial loayer as the silicon substrate 5 of the artificial magnetic conductor of intersecting parallels, and the thickness of silicon substrate 5 is 300 microns.
Above the silicon substrate 5 with field oxidation technology growing silicon oxide resilient coatings 4 of CMOS, with the method for photoetching determine the size of silica resilient coating 4 be with 1.585 millimeters be the square of the length of side, as the following dielectric layer of the artificial magnetic conductor of intersecting parallels.
Silicon chip is carried out annealing in process, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, utilize the first metal layer evaporated metal layer 3 of CMOS technology then, utilizing 6 * 6 of the method formation of photoetching is the square lamellule 7 of the length of side with 200 microns, gap between each lamellule is 55 microns, 6 * 6 lamellules 7 are pressed the ranks periodic and are arranged, and form the square formation of 6 * 6 lamellules 7 as Fig. 4.
Described lamellule 7, etch intersecting parallels fluting 8 above, each intersecting parallels fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, centre distance between per two parallel line of rabbet joint is 30 microns, and the lamellule 7 of each fluting links to each other with silicon substrate 5 and ground connection by via hole 6.
Carry out the chemical vapour deposition (CVD) oxidation on metal level 3, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the last dielectric layer of artificial magnetic conductor, and thickness is 1.3 microns, forms the artificial magnetic conductor 10 of 6 * 6 matrix structures.
Utilize the top layer metallic layer evaporation metal of CMOS technology, utilize the method for photoetching to form monopole antenna 11, prepare antenna welding node 13 and ground connection node 12 then, ground connection node 14.
Claims (7)
1. artificial magnetic conductor of groined type that is used for 60 GHz on-chip antennas is characterized in that this artificial magnetic conductor comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer stack gradually making from top to bottom; Below silicon substrate is positioned at, cover one deck silica resilient coating above it, evaporation layer of metal layer on the silica resilient coating is made distributed groined type structure, cover one deck insulating layer of silicon oxide on metal level, the top of insulating layer of silicon oxide is the functional circuit layer.
2. artificial magnetic conductor according to claim 1 is characterized in that, described artificial magnetic conductor adopts traditional CMOS technology to realize.
3. artificial magnetic conductor according to claim 1 is characterized in that, described metal level is made by the first metal layer of CMOS technology.
4. according to each described artificial magnetic conductor of claim 1 to 3, it is characterized in that, described metal level is divided into N * N unit, between each unit 55 microns at interval, each unit all be with 200 microns be the square of the length of side, foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between per two parallel line of rabbet joint is 30 microns.
5. according to each described artificial magnetic conductor of claim 1 to 3, it is characterized in that described silicon substrate thickness satisfies described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns during to 320 micrometer ranges.
6. according to each described artificial magnetic conductor of claim 1 to 3, it is characterized in that described silicon oxide insulation layer thickness is 1.3 microns.
7. one kind is used for 60 GHz on-chip antennas
The implementation method of the artificial magnetic conductor of intersecting parallels, pass through following step successively:
The first, the silicon chip of preparing to have epitaxial loayer is done the silicon substrate of artificial magnetic conductor;
The second, use the field oxidation technology growing silicon oxide resilient coating of CMOS above the silicon substrate, as the following dielectric layer of artificial magnetic conductor;
Three, silicon chip is annealed, on the silica resilient coating, carry out the chemical vapour deposition (CVD) oxidation, utilize the first metal layer evaporated metal layer of CMOS technology then;
Four, photoetching metal level forms intersecting parallels lamellule cyclic array structure, makes lamellule at metal level, etches the intersecting parallels fluting on lamellule; The lamellule of each fluting links to each other with silicon substrate and ground connection by via hole;
Five, carry out chemical vapour deposition (CVD) on metal level, form insulating layer of silicon oxide, insulating layer of silicon oxide is as the last dielectric layer of artificial magnetic conductor;
Six, utilize the functional circuit layer above the insulating layer of silicon oxide to make waveguide device and on-chip antenna.
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| CN103531904A (en) * | 2013-11-01 | 2014-01-22 | 南开大学 | 60 GHz trapezoidal monopole on-chip integrated antenna and implementation method |
| CN104716419A (en) * | 2015-04-08 | 2015-06-17 | 南开大学 | Programmable-control reconfigurable antenna based on transversal PIN diodes |
| CN106299645A (en) * | 2016-08-22 | 2017-01-04 | 北京无线电测量研究所 | A kind of on-chip antenna based on silicon technology |
| CN107369653A (en) * | 2016-05-13 | 2017-11-21 | 北京中电网信息技术有限公司 | A kind of system-in-a-package method of high interference component, structure and separation array structure |
| CN108258435A (en) * | 2017-12-27 | 2018-07-06 | 温州大学 | A kind of E wave band on-chip antennas for loading spiral intertexture type artificial magnetic conductor |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531904A (en) * | 2013-11-01 | 2014-01-22 | 南开大学 | 60 GHz trapezoidal monopole on-chip integrated antenna and implementation method |
| CN104716419A (en) * | 2015-04-08 | 2015-06-17 | 南开大学 | Programmable-control reconfigurable antenna based on transversal PIN diodes |
| CN104716419B (en) * | 2015-04-08 | 2018-01-05 | 南开大学 | The reconfigurable antenna of PLC technology based on horizontal PIN diode |
| CN107369653A (en) * | 2016-05-13 | 2017-11-21 | 北京中电网信息技术有限公司 | A kind of system-in-a-package method of high interference component, structure and separation array structure |
| CN106299645A (en) * | 2016-08-22 | 2017-01-04 | 北京无线电测量研究所 | A kind of on-chip antenna based on silicon technology |
| CN108258435A (en) * | 2017-12-27 | 2018-07-06 | 温州大学 | A kind of E wave band on-chip antennas for loading spiral intertexture type artificial magnetic conductor |
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