CN103325700A - Method for achieving through hole interconnection by filling through hole from bottom to top and product thereof - Google Patents
Method for achieving through hole interconnection by filling through hole from bottom to top and product thereof Download PDFInfo
- Publication number
- CN103325700A CN103325700A CN2013101685406A CN201310168540A CN103325700A CN 103325700 A CN103325700 A CN 103325700A CN 2013101685406 A CN2013101685406 A CN 2013101685406A CN 201310168540 A CN201310168540 A CN 201310168540A CN 103325700 A CN103325700 A CN 103325700A
- Authority
- CN
- China
- Prior art keywords
- blind hole
- photoresist
- hole
- seed layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000011049 filling Methods 0.000 title claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 58
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 23
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- CIJJJPBJUGJMME-UHFFFAOYSA-N [Ta].[Ta] Chemical compound [Ta].[Ta] CIJJJPBJUGJMME-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 1
- 238000000708 deep reactive-ion etching Methods 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000007772 electroless plating Methods 0.000 claims 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000009489 vacuum treatment Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 15
- 238000011161 development Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000011799 hole material Substances 0.000 description 98
- 238000007747 plating Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000012856 packing Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 3
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005518 electrochemistry Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229920006389 polyphenyl polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了一种通过自底向上填充实现通孔互联的方法，包括：（a）在基片的一个表面上加工制得盲孔；（b）在加工盲孔的基片表面上依次生长绝缘层、阻挡层和种子层；（c）向种子层表面上涂布光刻胶并填平盲孔，然后执行曝光及显影处理，以使光刻胶仅在盲孔底部的种子层表面上残留；（d）去除未覆盖光刻胶的种子层，而盲孔底部的种子层不受影响；（e）去除残留的光刻胶；（f）向盲孔中填充导电材料完成自底向上的生长；（g）减薄基片未加工盲孔的表面形成通孔，由此完成通孔互联过程。本发明还公开了相应的通孔互联结构产品。通过本发明，能够以便于操控、低成本、高效率的方式执行通孔电镀过程，并获得填充效果更好的通孔互联结构产品。
The invention discloses a method for realizing through-hole interconnection through bottom-up filling, comprising: (a) processing a blind hole on one surface of a substrate; (b) sequentially growing blind holes on the surface of a substrate where Insulation layer, barrier layer and seed layer; (c) Apply photoresist on the surface of the seed layer and fill the blind hole, and then perform exposure and development so that the photoresist is only on the surface of the seed layer at the bottom of the blind hole residual; (d) remove the seed layer not covered with photoresist, while the seed layer at the bottom of the blind hole is not affected; (e) remove the residual photoresist; (f) fill the blind hole with conductive material to complete bottom-up growth; (g) Thinning the surface of the unprocessed blind hole of the substrate to form a through hole, thereby completing the through hole interconnection process. The invention also discloses a corresponding through-hole interconnect structure product. Through the present invention, the through-hole electroplating process can be performed in a manner that is easy to control, low-cost, and high-efficiency, and through-hole interconnection structure products with better filling effect can be obtained.
Description
Technical field
The invention belongs to the semiconductor packaging field, more specifically, relate to a kind of by interconnected method of bottom-up filling realization through hole and products thereof.
Background technology
In the past few decades, integrated circuit processing technique is being followed Moore's Law and is being remained development at a high speed, the performance of chip has obtained greatly promoting, power consumption and cost also descend significantly, but the development of Electronic Encapsulating Technology is but relatively slow, become gradually one of bottleneck of restriction semiconductor technology evolves, traditional two-dimentional integrated form can't satisfy the industries such as consumer electronics, Aero-Space to speed and the more and more higher requirement of volume of integrated circuit, so three-dimensional integration technology is subject to increasing the attention and research.In numerous three-dimensional integration technologies, interconnecting silicon through holes technology (TSV) is a kind of novel solution, and it is by making the through hole of Z-direction at silicon chip, and the filled conductive material is realized the interconnection between the different chips in the through hole.The interconnection technique of this vertical direction can reduce the length of interconnection line between the chip, thereby can solve the delay problem between the chip, dwindle chip area, improve integration density, the limitation that surmounts Planar integration allows microelectronic industry continue to develop according to Moore's Law.
One of key of TSV technology is that the filling of through hole realizes signal of telecommunication interconnection.Usually adopt the mode of electroplating to carry out filling through hole in the prior art, wherein a kind of the electroplates in hole mode is sputtering seed layer on through-hole wall, then electroplates; This electro-plating method is owing to being that whole through hole is electroplated in the vertical simultaneously, need special electroplating device, and electroplating velocity is slow, require high to electroplate liquid, coating at silicon chip surface is thicker, and can exist the through hole upper and lower port to seal first, causes copper post inside that hole, the defective such as hollow are arranged, reduce simultaneously electrical property and the sealing of chip, affect device lifetime.
Another kind of the electroplates in hole mode is bottom-up electroplating technology, and to be copper begin deposition from an end of TSV through hole to electroplating process, along upwards growth of through hole, finally fills whole through hole.Bottom-up electro-plating method generally need to provide a through hole, adopts auxiliary disk as electroplating cathode, or utilizes the characteristic of electroplating cross growth at disk one face closure silicon through hole, realizes thus bottom-up plating.Electroplate with conformal and to compare, bottom-up plating does not need special installation, and speed is fast, and to electroplate liquid require lowly, the coating of silicon chip surface also can be controlled.But the method Seed Layer is made generally needs extra processing step, as make auxiliary disk, auxiliary disk ephemeral key closes; Or need to carry out in advance at the electroplated disk back side Seed Layer and fill, electroplate; Therefore exist technological process long, the defectives such as inefficiency.
Summary of the invention
Above defective or Improvement requirement for prior art, the invention provides a kind of by interconnected method of bottom-up filling realization through hole and products thereof, its purpose is to study also corresponding adjusting process step by growth mechanism and process to the filling through hole material, can so that control, low-cost, high efficiency mode carries out the electroplates in hole process, and obtains the better through hole interconnect architecture of filling effect product.
According to one aspect of the present invention, provide a kind of and realized the interconnected method of through hole by bottom-up filling, it is characterized in that, the method comprises the following steps:
(a) a surface processing at substrate makes blind hole, and so that the degree of depth of blind hole is not less than its diameter;
(b) on processing makes the whole substrate surface of blind hole, grow successively insulating barrier, barrier layer and Seed Layer;
(c) on the surface of described Seed Layer, be coated with photoresist and fill and lead up blind hole, then photoresist is carried out exposure and development treatment, so that photoresist is only residual on the Seed Layer surface that is in the blind hole bottom;
(d) Seed Layer not covered by photoresist on the substrate is carried out Transformatin, in this process, the Seed Layer of blind hole bottom is unaffected owing to the protection that is subjected to residual photoresist;
(e) remove the residual photoresist in blind hole bottom, expose the Seed Layer of its bottom;
(f) filled conductive material in the blind hole in this process, as boot media, utilizes electric conducting material growth variation between Seed Layer and the barrier layer in blind hole to finish bottom-up growth with the Seed Layer of blind hole bottom;
(g) reduction processing is carried out on another surface of the undressed blind hole of substrate, until blind hole is formed through hole, is finished thus the interconnected process of through hole and obtain required through hole interconnect architecture product.
As further preferably, in step (a), process by deep reaction ion etching, laser ablation or wet etching and to make blind hole; The quantity of described blind hole is one or more, and wherein the blind hole aperture is between 1 micron～1000 microns, and the degree of depth is between 10 microns～1000 microns, and the degree of depth of blind hole is 1～50 times of its diameter.
As further preferably, in step (b), the material of described insulating barrier is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polyphenyl and cyclobutane or photoresist and above-mentioned material, and preferably adopts the mode of thermal oxidation, physical vapor deposition or chemical vapor deposition to form; Described barrier layer is the double-deck barrier layer of titanium barrier layer, titanium-tungsten, the double-deck barrier layer of titanium-titanium nitride or the double-deck barrier layer of tantalum-tantalum nitride, and preferably adopts the mode of atomic layer deposition, physical vapor deposition or chemical vapor deposition to form; Described Seed Layer is that the materials such as copper or gold consist of, and preferably adopts the mode of chemical plating, electrochemistry grafting, atomic layer deposition, physical vapor deposition or chemical vapor deposition to form.
As further preferably, in step (c), when the surface-coated photoresist that is deposited with Seed Layer to substrate and after filling and leading up blind hole, its integral body put in the vacuum environment to carry out vacuumize processing, discharge thus the inner residual bubble of blind hole so that photoresist obtains fully filling in blind hole.
As further preferably, described photoresist is positive photoresist or negative photoresist, and the vacuum degree of vacuum environment is set to-0.3MPa～0.05MPa.
As further preferably, in step (c), by laser, electron beam or ion beam mode photoresist is carried out exposure, after exposure, photoresist is carried out the heating firmly treatment, then be soaked in the developer solution or by spray developing liquid and carry out development treatment.
As further preferably, in step (c), residual photoresist thickness is set to less than 1/2 of blind hole depth value on the Seed Layer surface of blind hole bottom.
As further preferably, in step (d), remove Seed Layer not covered by photoresist on the substrate by methods such as wet etching, dry etchings.
As further preferably, in step (e), the mode that preferably adopts acetone to soak removes the residual photoresist in blind hole bottom.
As further preferably, in step (f), described packing material is selected from copper, gold, silver or its mixture, and fill method is preferentially selected plating.
As further preferably, in step (g) afterwards, also comprise the step of removing dry film, pad, the rerouting of line layer and/or making salient point.
As further preferably, described substrate is selected from the compound semiconductors such as the element semiconductors such as silicon, germanium or GaAs, InP, gallium nitride.
According to another aspect of the present invention, also provide corresponding through hole interconnect architecture product.
In general, according to above technical scheme of the present invention compared with prior art, mainly possess following technical characterstic:
1, study by growth mechanism and process to the filling through hole material, there is very large growth variation in packing material in Seed Layer and barrier layer; And through after the present invention's processing, Seed Layer only exists in the blind hole bottom, impel the growth rate of blind hole underfill will be much larger than the growth rate of blind hole sidewall, packing material will be take the Seed Layer of blind hole bottom as boot media, from the beginning deposit of blind hole bottom, and realize bottom-up high speed, high-quality filling;
2, be a kind of bottom-up filling mode owing to what realize, during plating solution composition required to electroplate low than general conformal; Simultaneously, can strengthen electroplating current, improve electroplating efficiency, and needn't worry to cause inside the situations such as defective to occur because the blind hole opening seals first;
3, the surface of substrate is electroplated the rear surface and can not produced coating, thereby when post-processed, do not need the CMP(chemico-mechanical polishing owing to there not being the existence of Seed Layer) etc. processing, can reduce process costs;
4, according to manufacture method of the present invention be convenient to control, filling quality is high, and can simplify the processing step of through hole interconnect architecture, reduce process costs, thereby be particularly useful for large batch of suitability for industrialized production purposes.
Description of drawings
Fig. 1 is achieved in accordance with the invention by bottom-up filling and realizes the interconnected process flow diagram of through hole;
Fig. 2 a is the structural representation that processes blind hole on the substrate be used to being presented at;
Fig. 2 b is be used to the structural representation of deposition insulating layer, barrier layer and Seed Layer successively on the surface that is presented at substrate and is processed with blind hole;
Fig. 2 c is be used to coating photoresist on the surface that is presented at substrate and is deposited with Seed Layer and the structural representation after filling and leading up blind hole;
Fig. 2 d is for showing the structural representation after photoresist execution exposure and the development treatment;
Fig. 2 e is for showing take blind hole bottom photoresist as protection mechanism, removing the structural representation of the Seed Layer that comes out in the blind hole;
Fig. 2 f is the structural representation of removing the residual photoresist of blind hole for showing;
Fig. 2 g contains the structural representation that the blind hole of Seed Layer is filled for showing to the bottom.
In institute's drawings attached, identical Reference numeral is used for representing identical element or structure, wherein:
1-substrate 2-insulating barrier 3-barrier layer 4-Seed Layer 5-photoresist 6-electric conducting material
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.In addition, below in each execution mode of described the present invention involved technical characterictic just can mutually not make up as long as consist of each other conflict.
Fig. 1 realizes the interconnected process flow diagram of through hole according to of the present invention by bottom-up filling.As shown in fig. 1, mainly comprise the following steps: according to the interconnected method of realization through hole of the present invention
At first, shown in Fig. 2 a, a surface (being shown as upper surface among the figure) processing on substrate 1 makes blind hole, and so that the degree of depth of blind hole is not less than its diameter.Substrate can be selected semi-conducting material, such as compound semiconductors such as the element semiconductors such as silicon, germanium or GaAs, InP, gallium nitride.On two surfaces of substrate semiconductor device, multilayer electricity interlinkage layer or the micro-sensor structure that completes can be arranged, can also comprise pad or passivation layer.Processing makes a plurality of blind holes on the surface of substrate 1, and the diameter of blind hole does not wait from 1 micron to 1000 microns, and its cross section generally is circular or square; The degree of depth of blind hole is not less than its diameter, is preferably set in the present invention 1 times to 50 times of its diameter.Above-mentioned blind hole can be processed by deep reaction ion etching (DRIE), laser ablation or wet etching and be made.
Then, shown in Fig. 2 b, make on the whole substrate surface of blind hole successively deposition insulating layer 2, barrier layer 3 and Seed Layer 4 in processing, be formed with successively thus insulating barrier, barrier layer and the Seed Layer of layer structure at other positions of substrate surface of blind hole bottom, blind hole sidewall and undressed blind hole.The material of insulating barrier 2 is selected from mixture or the complex of silicon dioxide, silicon nitride, alundum (Al2O3), polyimides, Parylene, polyphenyl and cyclobutane or photoresist and above-mentioned material, and preferably adopts the mode of thermal oxidation, physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form.Barrier layer 3 is titanium barrier layer, the double-deck barrier layer of titanium-tungsten (Ti-W), the double-deck barrier layer of titanium-titanium nitride (Ti-TiN) or the double-deck barrier layer of tantalum-tantalum nitride (Ta-TaN), and preferably adopts the modes such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form; Seed Layer 4 is that copper (Cu) or gold materials such as (Au) consist of, and preferably adopts the mode of chemical plating, electrochemistry grafting, atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form.
Then, as shown in Fig. 2 c and 2d, Seed Layer 4 whole surface on for example be coated with photoresist 5 and fill and lead up blind hole by the spin coating mode, then photoresist is carried out exposure and development treatment, so that photoresist is only residual on the surface of the Some Species sublayer that is in the blind hole bottom and cover Seed Layer.In this process, according to a preferred embodiment of the present invention, can be in coating after photoresist fill and lead up blind hole, its integral body put to carry out in the vacuum environment vacuumize processing, can discharge thus the inner residual bubble of blind hole and make photoresist in blind hole, obtain the fully effect of filling.Described photoresist 5 is photo-sensitive characteristics, can be negative photoresist or positive photoresist; The vacuum degree of vacuum environment is set to-0.3MPa～0.05MPa.Expose with specific equipment such as mask aligner, or carry out with laser, electron beam or ion beam.After the exposure, preferably can select to heat with hot plate, baking oven or infrared mode and be applied to on-chip photoresist 5, carry out the post bake step to improve photoetching quality.Developing refers to that the substrate 1 that will scribble photoresist 5 is soaked in the developer solution, or passes through the method for spray developing liquid, removes a part of photoresist, thereby forms required figure.According to another preferred implementation of the present invention, in above-mentioned steps, behind photoresist 5 exposure imagings, only at blind hole bottom residual fraction photoresist, come out in the most of zone of blind hole, its one-tenth-value thickness 1/10 of residual photoresist is set to less than 1/2 of blind hole depth value in this way.
Then, shown in Fig. 2 e, the photoresist 5 bottom blind hole with the technique of wet etching or dry etching, is removed the Seed Layer 4 that comes out as mask.Because the protective effect of photoresist 5 will be subjected to the impact of etching technics by the Seed Layer 4 of photoresist 5 overlay areas.Seed Layer 4 can be copper, gold etc.The thickness of Seed Layer is preferably between 10 nanometers to 10 micron.
Then, shown in Fig. 2 f, can for example adopt chemical mode to remove residual photoresist 5 in the blind hole, and expose the Seed Layer of its bottom, the preferred mode that adopts acetone to soak in this process.
Then, shown in Fig. 2 g, fill up electric conducting material 6 in blind hole, filling generally is to adopt to electroplate or the method for chemical plating, and the material of filling generally is copper, also can be the mixture of the material such as gold, silver or other metals, alloy.Although the barrier layer 3 on the blind hole sidewall also is with conductivity, but owing to there not being Seed Layer to cover, packing material 6 growth rates on it will be much smaller than the growth rate at bottom seed layer 4 places, packing material 6 will be take the Seed Layer 4 of via bottoms as boot media, begin deposition from the blind hole bottom, realize bottom-up high speed, high-quality plating filling.At last, reduction processing is carried out on another surface of the undressed blind hole of substrate, until blind hole is formed through hole, obtained thus required through hole interconnect architecture product.
In sum, only keep the Seed Layer of deposit among the present invention at through hole, utilize the growth variation of blind hole packing material on Seed Layer and barrier layer, take the Seed Layer of via bottoms as boot media, realize bottom-up growth; In addition, the surface of substrate is electroplated the rear surface and can not produced coating, thereby when post-processed, do not need the techniques such as CMP owing to there not being the existence of Seed Layer.Correspondingly, can simplify the manufacture craft that the bottom-up plating of through hole is filled according to manufacture craft of the present invention, reduce the process costs that the through hole interconnect architecture is made, possess simultaneously be convenient to control, the filling quality advantages of higher, thereby be particularly useful for large batch of suitability for industrialized production purposes.
Those skilled in the art will readily understand; the above only is preferred embodiment of the present invention; not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310168540.6A CN103325700B (en) | 2013-05-09 | 2013-05-09 | A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310168540.6A CN103325700B (en) | 2013-05-09 | 2013-05-09 | A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103325700A true CN103325700A (en) | 2013-09-25 |
| CN103325700B CN103325700B (en) | 2015-11-18 |
Family
ID=49194373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310168540.6A Expired - Fee Related CN103325700B (en) | 2013-05-09 | 2013-05-09 | A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103325700B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952934A (en) * | 2015-06-25 | 2015-09-30 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method, array substrate and display panel |
| CN106191862A (en) * | 2016-07-25 | 2016-12-07 | 中国电子科技集团公司第四十研究所 | A kind of method making solid metal hole on substrate |
| CN106783634A (en) * | 2016-12-26 | 2017-05-31 | 通富微电子股份有限公司 | One kind is fanned out to packaging and its method for packing |
| CN112340694A (en) * | 2020-11-03 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN113026067A (en) * | 2021-03-04 | 2021-06-25 | 珠海市创智芯科技有限公司 | Electroplating solution and electroplating process for wafer level packaging |
| CN115050651A (en) * | 2022-05-30 | 2022-09-13 | 厦门云天半导体科技有限公司 | Hole filling structure for chip packaging deep hole interconnection and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1275802A (en) * | 1999-05-26 | 2000-12-06 | 日本电气株式会社 | Semiconductor device and making method thereof |
| US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | A method of fabricating a through-hole interconnection structure |
-
2013
- 2013-05-09 CN CN201310168540.6A patent/CN103325700B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1275802A (en) * | 1999-05-26 | 2000-12-06 | 日本电气株式会社 | Semiconductor device and making method thereof |
| US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
| CN102130042A (en) * | 2010-12-14 | 2011-07-20 | 北京大学 | A method of fabricating a through-hole interconnection structure |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952934A (en) * | 2015-06-25 | 2015-09-30 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method, array substrate and display panel |
| CN104952934B (en) * | 2015-06-25 | 2018-05-01 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and manufacture method, array base palte, display panel |
| CN106191862A (en) * | 2016-07-25 | 2016-12-07 | 中国电子科技集团公司第四十研究所 | A kind of method making solid metal hole on substrate |
| CN106783634A (en) * | 2016-12-26 | 2017-05-31 | 通富微电子股份有限公司 | One kind is fanned out to packaging and its method for packing |
| CN106783634B (en) * | 2016-12-26 | 2019-09-20 | 通富微电子股份有限公司 | One kind being fanned out to packaging and its packaging method |
| CN112340694A (en) * | 2020-11-03 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN112340694B (en) * | 2020-11-03 | 2023-05-12 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN113026067A (en) * | 2021-03-04 | 2021-06-25 | 珠海市创智芯科技有限公司 | Electroplating solution and electroplating process for wafer level packaging |
| CN115050651A (en) * | 2022-05-30 | 2022-09-13 | 厦门云天半导体科技有限公司 | Hole filling structure for chip packaging deep hole interconnection and manufacturing method thereof |
| CN115050651B (en) * | 2022-05-30 | 2025-01-10 | 厦门云天半导体科技有限公司 | Hole filling structure for chip packaging deep hole interconnection and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103325700B (en) | 2015-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102270603B (en) | Manufacturing method of silicon through hole interconnect structure | |
| CN102130042B (en) | A method of fabricating a through-hole interconnection structure | |
| CN103325700A (en) | Method for achieving through hole interconnection by filling through hole from bottom to top and product thereof | |
| CN101483150B (en) | Process for treating silicon through-hole interconnection construction | |
| CN103258789A (en) | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure | |
| CN103258788B (en) | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling | |
| CN103794587B (en) | Embedded type rewiring line packaging structure of chip with good heat dissipation performance and manufacturing method thereof | |
| US10515923B2 (en) | Method for forming semiconductor package structure with twinned copper layer | |
| CN102246292A (en) | Method for electroplating through wafer vias in a wafer for 3D packaging | |
| CN102376689A (en) | Through silicon hole structure with step and manufacture process of through silicon hole | |
| CN101483149A (en) | Production method for through wafer interconnection construction | |
| CN103681390A (en) | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate | |
| CN110323197A (en) | Structure and preparation method thereof for ultra high density chip FOSiP encapsulation | |
| CN103887231B (en) | Self-alignment technology for leak holes and dielectric layer on back of TSV and TSV | |
| CN103367285A (en) | Through hole structure and manufacturing method thereof | |
| CN104952789A (en) | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) | |
| KR100763136B1 (en) | Wafer Bonding Method in System-in-Package | |
| CN102637713A (en) | Method for packaging image sensor comprising metal micro-bumps | |
| CN116130436A (en) | Packaging structure and preparation method of integrated porous microfluidic heat dissipation structure array | |
| WO2014067288A1 (en) | Wafer-level through silicon via (tsv) manufacturing method | |
| CN104900585A (en) | Preparation method for sidewall insulating layer of vertical interconnection | |
| CN106057757A (en) | Silicon through hole structure and manufacturing method thereeof | |
| CN105679701A (en) | Method for efficiently electroplating and filling silicon-based TSV | |
| CN105070698B (en) | Wafer scale scolding tin micro convex point and preparation method thereof | |
| CN109037149B (en) | Preparation method of defect-free through silicon via structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 Termination date: 20160509 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |