CN103325409B - Memory card with smart card function, its power control method and power control circuit - Google Patents

Abstract

A memory card with smart card function, a power control method and a power control circuit thereof are provided. The memory card with the function of the smart card comprises a flash memory unit, a data processing control unit and a power supply control unit. The data processing control unit is coupled to the flash memory unit. The data processing control unit controls the flash memory unit and encrypts, decrypts and stores smart card security data. The power control unit is coupled to the data processing control unit and the flash memory unit. The power control unit receives at least one of a first power input and a second power input. The power control unit selectively provides a first power input or a second power input to the data processing control unit according to at least one control signal, and an output end of the power control unit is coupled to the first power input. In addition, a power control method and a power control circuit of the memory card are also provided.

Description

Memory card with smart card function, its power control method and power control circuit

technical field

The invention relates to a power control method and a power control circuit, and in particular to a memory card with smart card function and its power control method and power control circuit.

Background technique

As users gradually accept the use of electronic wallets and prepaid stored value, the use of smart cards is becoming more and more popular. A smart card (SmartCard) is an integrated circuit chip (IC chip) having components such as a microprocessor, a card operating system, a security module, and a memory to allow a holder to perform predetermined operations. The smart card provides computing, encryption, two-way communication and security functions, making this card not only store data, but also protect the stored data. The Subscriber Identification Module (SIM) card used in the cellular phone using the Global System for Mobile Communications (GSM) mechanism is one of the application examples of the smart card. In general, smart cards are inherently limited by the specifications of their integrated circuits and therefore have limited storage capacity.

A memory card (MEMORYCARD) is a data storage device, which generally uses a NAND flash memory as a storage medium. NAND flash memory has the advantages of being writable, erasable, and data can still be saved after power failure. In addition, with the improvement of manufacturing technology, NAND flash memory has the advantages of small size, fast access speed, and low power consumption. low merit. Therefore, in recent years, those skilled in the art try to combine the smart card with a large-capacity memory card to expand the storage capacity of the smart card.

Generally speaking, if the user wants to access the data in the memory card, he must access it through a card reader. Therefore, in the application of combining a smart card with a memory card, it can only be contacted through a card reader. Read data from memory cards and smart cards. However, with the development of Near Field Communication (NFC), many contactless sensing technologies have been widely used in daily life, such as subway ticket cards, access control cards and so on.

Therefore, a memory card combined with a smart card and having a contactless access function emerges at the historic moment, such as a MicroSecure Digital (MicroSD) with a smart card function. This kind of memory card receives different power input when it is read by the reading device in the host system under different circumstances, so if the smart card circuit inside the memory card cannot work normally when it is powered by one of the different power inputs, it will be greatly affected. limit its scope of application.

Contents of the invention

The invention provides a memory card with smart card function. When different power sources are input to supply power, the smart card circuit inside can work normally.

The invention provides a power supply control method of a memory card. The method can enable one of the dual power supplies of the memory card with smart card function to supply power, and at this time, the smart card circuit inside the memory card can work normally.

The invention provides a power control circuit suitable for application in an electronic circuit. When any one of different power inputs is input to the electronic circuit, the electronic circuit can work normally.

The invention proposes a memory card with smart card function, which includes a flash memory unit, a data processing control unit and a power control unit. The data processing control unit is coupled to the flash memory unit. The data processing control unit controls the flash memory unit, and encrypts, decrypts and stores a smart card security data. The power control unit is coupled to the data processing control unit and the flash memory unit. The power control unit receives at least one of a first power input and a second power input. The power control unit selects to provide the first power input or the second power input to the data processing control unit according to at least one control signal, and an output terminal of the power control unit is coupled to the first power input.

In an embodiment of the present invention, the above power control unit includes a first power supply channel and a second power supply channel. The first power supply channel is used to receive the first power input, and determine whether to provide the first power input to the data processing control unit according to a first control signal. The second power supply channel is used to receive the second power input, and determine whether to provide the second power input to the data processing control unit according to a second control signal. The first control signal changes its state in response to the first power input to control the first power supply channel.

In an embodiment of the present invention, the above-mentioned first power supply channel includes a first switch element and a signal receiving unit. The first switch element has a first terminal, a second terminal and a control terminal. The first end receives the first power input; the second end is coupled to the output end of the power control unit. The signal receiving unit has an input end and an output end. The input end receives the first power input and processes it into a first control signal; the output end is coupled to the control end of the first switch element and outputs the first control signal.

In an embodiment of the present invention, the above-mentioned signal receiving unit includes an inverter. The inverter has an input terminal and an output terminal. The input end receives the first power input and inverts it into a first control signal. The output end is coupled to the control end of the first switch element, and outputs a first control signal.

In an embodiment of the present invention, the above-mentioned second power supply channel includes a second switch element. The second switch element has a first terminal, a second terminal and a control terminal. The first end receives the second power input; the second end is coupled to the output end of the power control unit; the control end is used for receiving the second control signal.

In an embodiment of the present invention, the above power control unit further includes a voltage limiting unit. The voltage limiting unit is coupled between the first and second power supply channels, and is used to suppress a reverse voltage fed back from the first power supply channel to the second power supply channel from being less than a specific value, or to suppress the second power supply channel The reverse voltage fed back to the first power supply channel is less than a specific value.

In an embodiment of the present invention, the voltage limiting unit includes a first diode and a second diode. The first diode has an anode and a cathode. The anode is coupled to the first power input; the cathode is coupled to the first switching element. The second diode has an anode and a cathode. The anode is coupled to the second power input; the cathode is coupled to the second switching element.

In an embodiment of the present invention, the above-mentioned power control unit includes a voltage dividing unit. The voltage dividing unit has a first end, a second end and a voltage dividing node. The first end is coupled to the first power input; the second end is coupled to the ground. The voltage dividing unit divides the voltage of the first power input, and provides the divided first power input to the output terminal of the power control unit through the voltage dividing node.

In an embodiment of the present invention, the above-mentioned voltage dividing unit includes a first resistor, one end of which serves as the first end of the voltage dividing unit and is coupled to the first power input. The other end of the first resistor serves as a voltage dividing node, and provides the divided first power supply to the output terminal of the power control unit. The second resistor is coupled in series with the first resistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor serves as a second end of the voltage dividing unit and is coupled to ground.

In an embodiment of the present invention, the above-mentioned data processing control unit includes a memory control circuit and a smart card circuit. The memory control circuit is coupled to the flash memory unit and controls the flash memory unit. The smart card circuit is coupled to the memory control circuit, and encrypts, decrypts and stores a smart card security data. The smart card circuit receives smart card security data from a host system or transmits the processed smart card security data to the host system through the memory control circuit. The power control unit selects to provide the first power input or the second power input to the smart card circuit.

In an embodiment of the present invention, the above-mentioned flash memory unit also stores smart card security data.

In an embodiment of the present invention, the above-mentioned first power input is provided by a memory card reading device; the second power input is provided by a short-range wireless communication reading device.

The invention provides a power control method of a memory card. The memory card includes a power control unit and a data processing control unit. The power control method includes the following steps. At least one of a first power input and a second power input is received. According to at least one control signal, select to provide the first power input or the second power input to a smart card circuit in the data processing control unit. An output terminal of the power control unit is coupled to the first power input.

In an embodiment of the present invention, the step of selecting to provide the first power input or the second power input to the smart card circuit includes determining whether to provide the first power input to the data processing control unit according to a first control signal. The first control signal changes its state in response to the first power input to control supply to the first power input.

In an embodiment of the present invention, the step of selecting to provide the first power input or the second power input to the smart card circuit further includes inverting the first power input as the first control signal to control the supply of the first power input.

In an embodiment of the present invention, the step of selecting to provide the first power input or the second power input to the smart card circuit further includes determining whether to provide the second power input to the data processing control unit according to a second control signal. The first power input serves as the second control signal.

In an embodiment of the present invention, the above-mentioned power control method further includes preventing a reverse voltage fed back from the first power input to the second power input from being smaller than a specific value.

In an embodiment of the present invention, the above power control method further includes preventing the reverse voltage fed back from the second power input to the first power input from being smaller than a specific value.

In an embodiment of the present invention, the above power control method further includes dividing the voltage of the first power input, and providing the divided first power input to the output terminal of the power control unit.

The present invention provides a power control circuit, which includes a first power supply channel, a first power supply channel and a voltage limiting unit. The first power supply channel is used to receive a first power input, and determine whether to provide the first power input to a data processing control unit according to a first control signal. The second power supply channel is used to receive a second power input, and determine whether to provide the second power input to the data processing control unit according to a second control signal. The voltage limiting unit is coupled between the first and second power supply channels, and is used to prevent a reverse voltage fed back from the first power supply channel to the second power supply channel from being less than a specific value, or to prevent the second power supply channel from feeding back to the The reverse voltage of the first power supply channel is less than a specific value.

In an embodiment of the present invention, the conduction loss of the voltage input from the first power input or the second power input to the data processing control unit is less than 0.15 volts.

In an embodiment of the present invention, the above-mentioned specific value is not greater than 60% of the corresponding power input or 1 volt.

Based on the above, the memory card provided by the present invention has the function of a smart card and can perform short-distance wireless communication. Moreover, the provided power supply control method can make the internal smart card circuit of the memory card work normally under the condition that one of the dual power supplies is powered.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic block diagram of a memory card and its host system according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic block diagram of a power control unit according to an exemplary embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a power control unit according to an exemplary embodiment of the present invention.

FIG. 4 is a flow chart of steps of a power control method for a memory card according to an embodiment of the invention.

FIG. 5 is a flow chart of steps of a power control method for a memory card according to another embodiment of the present invention.

[Description of main component symbols]

100: host system

110: memory card reading device

120: Short-range wireless communication reading device

200: memory card

210: Flash memory unit

220: Data processing control unit

222: memory control circuit

224: Smart card circuit

230, 330: power control unit

232, 332: the first power supply channel

234, 334: Second power supply channel

236, 336: voltage limiting unit

238, 338: Voltage divider unit

333: Signal receiving unit

Ctrl1: first control signal

Ctrl2: second control signal

P1: first power input

P1': the first power input after voltage division

P2: Second power input

OUT: the output terminal of the power control unit

Q1: First switching element

Q2: Second switching element

D1: first diode

D2: second diode

N: Voltage divider node

R1: first resistor

R2: second resistor

S400, S402, S404, S406, S408, S500, S502, S504: steps of power control method

detailed description

FIG. 1 is a schematic block diagram of a memory card and its host system according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the host system 100 of this exemplary embodiment includes a memory card reading device 110 and a wireless communication reading device 120 . Here, the host system 100 is, for example, a portable electronic communication device (such as a mobile phone, a tablet computer), but the invention is not limited thereto. In this exemplary embodiment, the memory card 200 includes a flash memory unit 210 , a data processing control unit 220 and a power control unit 230 . The data processing control unit 220 includes a memory control circuit 222 and a smart card circuit 224 . The memory control circuit 222 is coupled to the flash memory unit 210 . The smart card circuit 224 is coupled to the memory control circuit 222 . The memory card 200 is, for example, a Micro Secure Digital (MicroSD) memory card, which is combined with a smart card and has a contactless access function. Therefore, the memory card reading device 110 of this exemplary embodiment is, for example, a Micro Secure Digital memory card reading device. In addition, in this exemplary embodiment, the flash memory unit 210 , the data processing control unit 220 and the power control unit 230 can be individually implemented in a single chip, or all functions can be integrated in a single chip for implementation.

The memory card reading device 110 is used to identify the data format conforming to the SD standard and convert it into a format that the host system 100 can recognize. Specifically, the memory card reading device 110 of this embodiment is used to connect the memory card 200. For example, the memory card 200 is detachably inserted into the memory card reading device 110, so that the host system 100 can use the memory card The reading device 110 accesses the inserted memory card 200 . In this exemplary embodiment, the user can insert the memory card 200 into the memory card reading device 110 to connect with the host system 100 for contact communication conforming to the ISO7816-3 standard. For example, the user can insert the memory card 200 with financial smart card security data into the memory card reading device 110 and perform online shopping payment through the host system 100 and the Internet.

The wireless communication reading device 120 can be used to send and receive RF signals to perform data transmission with the reading device (such as an RF reader, not shown). Other types of wireless communication specifications. That is to say, in this exemplary embodiment, the user can insert the memory card 200 into the memory card reading device 110 and use the short-range wireless communication reading device 120 to communicate with other non-contact reading devices according to the ISO14443 standard. Contactless short-range wireless communication. For example, the user may insert the memory card 200 with the security data of the smart card of the subway ticket into the memory card reading device 110 . When taking the subway, communicate with the reading device arranged at the subway station to pay in a contactless manner, or the user can insert the memory card 200 with financial smart card security data into the memory card reading device 110 and pay at the relevant store ( For example, gas stations, convenience stores) when shopping, communicate with the reader installed in the store to pay in a contactless manner.

The data processing control unit 220 is used to control the operation of the memory card 200 , it uses the memory control circuit 222 to control the flash memory unit 210 , and uses the smart card circuit 224 to encrypt, decrypt and store a smart card security data. In this exemplary embodiment, the smart card circuit 224 is, for example, a Universal Integrated Circuit Card (UICC), which stores information including user information, key code, payment method, and the like. The smart card circuit 224 receives smart card security data from the host system 100 or transmits the processed smart card security data to the host system 110 through the memory control circuit 222 (or to the host through a wireless information sending unit). Generally speaking, since the data security of the smart card circuit 224 is quite high, the smart card security data processed by the smart card circuit 224 can be used for identity verification, small payment and other applications. For example, this smart card security data is mass transit ticket data, financial data, etc. In an exemplary embodiment of the present invention, the interface of the smart card circuit 224 complies with ISO7816-3 and ISO14443 standards. However, the present invention is not limited thereto, and the smart card circuit 224 may also be other data protection mechanisms with higher security levels. It is worth mentioning that the encryption and decryption methods used by the smart card circuit 224 conform to Advanced Encryption Standard (Advanced Encryption Standard, AES), Data Encryption Standard (Data Encryption Standard, DES), Three-stage Data Encryption Standard (Triple Data Encryption Standard, 3DES), asymmetric encryption Algorithm (Rivest Shamir Adleman, RSA).

The flash memory unit 210 is used to store the data to be written by the host system 100 according to the instruction of the host system 100 under the control of the memory control circuit 222 . Specifically, after the user inserts the memory card 200 into the memory card reading device 110, the host system 100 can issue an access command to the memory control circuit 222 through the memory card reading device 110 (for example, write command, read command, etc.), and the memory control circuit 222 operates the flash memory unit 210 according to the received command, and then writes data received from the host system 100 or transmits data to the host system 100 .

For example, in this exemplary embodiment, the memory control circuit 222 includes a microprocessor unit for controlling the overall operation, a buffer memory for temporarily storing data, a flash memory interface module for accessing the flash memory unit 210, The micro-secure digital interface module for communicating with the memory card reading device 110 , the interface module capable of accessing the smart card circuit 224 , and the error checking and correction module (not shown).

In this exemplary embodiment, the microprocessor unit of the memory control circuit 222 will identify whether the instructions and data received via the memory card reading device 110 are general instructions and data to be directly transmitted to the flash memory unit 210 or must be sent by the flash memory unit 210. The smart card circuit 224 processes the smart card command and the smart card security data, and executes the operation of writing data to the flash memory unit 210 or dispatching the command and data to the smart card circuit 224 according to the judgment result. In addition, as mentioned above, when the storage capacity of the smart card circuit 224 is limited due to its specifications, in this exemplary embodiment, the smart card security data of the smart card chip 224 can be stored in a storage device under the management of the memory control circuit 222. In the flash memory unit 210 whose storage capacity is larger than that of the smart card chip 224 itself.

The power control unit 230 is coupled to the data processing control unit 220 and the flash memory unit 210 . The power control unit 230 receives at least one of a first power input P1 and a second power input P2 . The power control unit 230 selectively provides the first power input P1 or the second power input P2 to the smart card circuit 224 according to at least one control signal (not shown). In this exemplary embodiment, the first power input P1 is provided by the memory card reading device 110; the second power input P2 is provided by the short-range wireless communication reading device 120, but the present invention is not limited thereto, the first power The input and the second power input can be various types of power supply devices.

Specifically, if the host system 100 is in the normal operation mode, the memory card reading device 110 provides the first power input P1 to the smart card circuit 224. At this time, the first power input P1 is, for example, 3.3 volts. With the design of the power control unit 230 of the example, the smart card circuit 224 can work normally. Another mode of operation is to read the host system 100 with a NFC reader. In this operation mode, the second power input P2 is provided when the host system 100 detects the signal of the short-range wireless communication reading device and decides to receive the second power input P2 when it is close to the short-range wireless communication sending device. At this time, the second power input P2 is, for example, 1.8 volts. With the design of the power control unit 230 in this exemplary embodiment, the smart card circuit 224 can also work normally. In other words, in this exemplary embodiment, when either the memory card reading device 110 or the NFC reading device 120 is powered, the smart card circuit 224 can work normally.

Further, FIG. 2 is a schematic block diagram of a power control unit according to an exemplary embodiment of the present invention. Referring to FIG. 2 , the power control unit 230 of this exemplary embodiment includes a first power supply channel 232 , a second power supply channel 234 , a voltage limiting unit 236 and a voltage dividing unit 238 .

The first power supply channel 232 receives the first power input P1, and determines whether to provide the first power input P1 to the smart card circuit 224 according to a first control signal Ctrl1. In this exemplary embodiment, the first control signal Ctrl1 changes its state in response to the first power input P1 to control the first power supply channel 232 . Here, the first control signal Ctrl1 is, for example, obtained by inverting the first power input P1, but the invention is not limited thereto. In another exemplary embodiment, when the power control unit judges that the first power input P1 is higher than a predetermined voltage level, it can provide a first control signal Ctrl1 for connecting the first power input P1 to the smart card circuit 224 . On the other hand, the second power supply channel 234 receives the second power input P2, and determines whether to provide the second power input P2 to the smart card circuit 224 according to a second control signal Ctrl2. In this exemplary embodiment, the first power input P1 is used as the second control signal Ctrl2 to control whether the second power supply channel 234 is turned on or not, but the invention is not limited thereto. In another exemplary embodiment, when the power control unit judges that the second power input P2 is higher than a predetermined voltage level, it can provide a second control signal Ctrl2 for inputting the second power input P2 to the smart card circuit 224, and the The first control signal Ctrl1 for cutting off the first power supply channel 232 .

The voltage limiting unit 236 is coupled between the first power supply channel 232 and the second power supply channel 234, and is used to prevent a reverse voltage fed back from the first power supply channel 232 to the second power supply channel 234 from being less than a certain value, and The reverse voltage fed back from the second power supply channel 234 to the first power supply channel 232 is prevented from being less than a specific value. In this embodiment, the specified value is not greater than 60% of the corresponding power input or 1 volt. For example, when the first power supply channel 232 provides the first power input P1, the specific value is not greater than 60% of the first power input P1, that is, 0.6 times. Furthermore, when the memory card reading device 110 is powered, the first power input P1 of 3.3 volts is output to the smart card circuit 224 through the first power supply channel 232, and at the same time, the first power supply channel 232 will also provide a reverse voltage The feedback is fed back to the second power supply channel 234, thereby affecting the second power input P2. Therefore, in this exemplary embodiment, in order to comply with the UICC specification standard such as the smart card circuit 224, the present exemplary embodiment is combined with the voltage limiting unit 236 to suppress the reverse voltage fed back by the first power supply channel 232 from about 0.3 volts, which is less than 0.5 volts. Volts, but the present invention is not limited thereto, and the limit requirement of the feedback reverse voltage between the power supply channels can be determined according to the needs of the designer. In this example, the first power input P1 actually supplied to the smart card circuit 224 is about 3.28 volts, so the voltage conduction loss of the first power input P1 input to the data processing control unit 220 in this exemplary embodiment is less than 0.15 volts.

Conversely, when the short-range wireless communication reader 120 provides the second power input P2 of 1.8 volts, the second power supply channel 234 will also provide reverse voltage feedback to the first power supply channel 232, with the voltage limitation of this exemplary embodiment The unit 236 can also suppress the reverse voltage fed back from the second power supply channel 234 to be less than 0.5 volts. In other words, the design architecture of this exemplary embodiment, in addition to achieving the purpose of choosing one of the dual power supplies, when either power input does not exist, the reverse voltage fed back is about 0.3 volts, which is less than 0.5 volts, which complies with UICC specification standards. In this example, the second power input P2 actually supplied to the smart card circuit 224 is about 1.78 volts, so the voltage conduction loss of the second power input P2 input to the data processing control unit 220 in this exemplary embodiment is also less than 0.15 volts.

The voltage dividing unit 238 divides the voltage of the first power input P1, and provides the divided first power input P1' to the output terminal OUT of the power control unit 230 via its voltage dividing node. In other words, the first power input P1 is divided and coupled to the output terminal OUT of the power control unit 230, therefore, the output voltage of the power control unit 230 will be linked with the first power input P1, that is, when the first power input When P1 is 3.3 volts, the output is 3.3 volts, otherwise it is 1.8 volts. This exemplary embodiment can avoid the erroneous operation that causes the voltage of the first power input P1 to drop to 1.8 volts or 0 volts when switching from the second power input P2 to the first power input P1 through such a linkage design. In this exemplary embodiment, the power control unit 230 includes a voltage dividing unit 238. In other exemplary embodiments, the voltage dividing unit 238 can be selectively configured according to actual design requirements, that is, the power control unit can optionally include or not Includes divider unit.

FIG. 3 is a schematic circuit diagram of a power control unit according to an exemplary embodiment of the present invention. Please refer to FIG. 3 , the first power supply channel 332 of this exemplary embodiment includes a first switching element Q1 and a signal receiving unit 333 . In this exemplary embodiment, the first switch element Q1 is realized by, for example, a transistor element such as a P-type metal oxide semiconductor field effect transistor (P-MOSFET), but the invention is not limited thereto. The first switching element Q1 has a first terminal, a second terminal and a control terminal, so the first terminal, the second terminal and the control terminal of the first switching element Q1 respectively correspond to the source of the PMOS field effect transistor. pole, drain and gate. The first end of the first switch element Q1 receives the first power input P1; the second end of the first switch element Q1 is coupled to the output end OUT of the power control unit; the control end of the first switch element Q1 is coupled to the signal receiving unit 333 to receive the first control signal Ctrl1. The signal receiving unit 333 has an input terminal and an output terminal. The input end receives the first power input P1 and processes it into a first control signal Ctrl1; the output end is coupled to the control end of the first switching element Q1, and outputs the first control signal Ctrl1 to the first switching element Q1 to control it conduction state. In this example, the signal receiving unit 333 includes an inverter, so the signal receiving unit 333 inverts the first power input P1 and serves as the first control signal Ctrl1.

The second power supply channel 334 includes a second switch element Q2. In this exemplary embodiment, the second switch element Q2 is realized by, for example, a PMOS field effect transistor, but the invention is not limited thereto. The second switching element Q2 has a first terminal, a second terminal and a control terminal, so the first terminal, the second terminal and the control terminal of the second switching element Q2 respectively correspond to the source of the PMOS field effect transistor. pole, drain and gate. The first end of the second switching element Q2 receives the second power input P2; the second end of the second switching element Q2 is coupled to the output end OUT of the power control unit; the control end receives the first power input P1 as the second control signal Ctrl2 .

In this exemplary embodiment, the first switching element Q1 and the second switching element Q2 are realized by P-type metal-oxide-semiconductor field effect transistors. With this design structure, the voltage conduction loss is about 0.02 volts. In the embodiment where the power input P1 is 3.3 volts and the second power input P2 is 1.8 volts, it can ensure that the voltage value of the first power input P1 output by the first power supply channel 332 is about 3.28 volts, while ensuring that the second power supply The voltage value of the second power input P2 output by the channel 334 is about 1.78 volts, which meets the standard of UICC. The aforementioned voltage values of 0.02 volts, 3.3 volts, 3.28 volts, 1.8 volts, and 1.78 volts are for illustrative purposes only, and the present invention is not limited thereto.

The voltage limiting unit 336 includes a first diode D1 and a second diode D2. An anode of the first diode D1 is coupled to the first power input P1; a cathode is coupled to the first end of the first switching element Q1. An anode of the second diode D2 is coupled to the second power input P2; a cathode is coupled to the first terminal of the second switching element Q2. This kind of circuit design structure can suppress the reverse voltage fed back by the first power supply channel 332 and the second power supply channel 334 to be less than 0.5 volts. In this exemplary embodiment, when any power input does not exist, the reverse voltage fed back by each channel is, for example, about 0.3 volts, which complies with the standard of UICC. The above-mentioned voltage values of 0.3 volts and 0.5 volts are for illustrative purposes only, and the present invention is not limited thereto.

In this exemplary embodiment, the voltage dividing unit 338 has a first end, a second end and a voltage dividing node N. Referring to FIG. The first end is coupled to the first power input P1; the second end is coupled to the ground. The voltage dividing unit 338 divides the voltage of the first power input P1, and provides the divided first power input P1 to the output terminal OUT of the power control unit via the voltage dividing node N. The voltage dividing unit 338 in this exemplary embodiment is implemented by a first resistor R1 and a second resistor R2 coupled in series. One end of the first resistor R1 serves as a first end of the voltage dividing unit 338 and is coupled to the first power input P1. The other end of the first resistor R1 serves as a voltage dividing node N1 to provide the divided first power input P1' to the output terminal OUT of the power control unit 330. One end of the second resistor R2 is coupled to the other end of the first resistor R1 , and the other end of the second resistor serves as the second end of the voltage dividing unit 338 and is coupled to the ground. The voltage dividing unit 338 will provide the divided first power input P1' to the output terminal OUT of the power control unit 330. This exemplary embodiment can avoid switching from the second power input P2 to the second power input P2 through this linkage design. When a power supply is input to P1 , the voltage of the first power input P1 drops to 1.8 volts or 0 volts in an erroneous operation.

FIG. 4 is a flow chart of steps of a power control method for a memory card according to an embodiment of the invention. Please refer to FIG. 1 , FIG. 2 and FIG. 4 at the same time. The power control method of this embodiment is at least applicable to the memory card illustrated in FIG. 1 to FIG. 3 , and includes the following steps. In step S400, at least a first power input P1 is received. In this exemplary embodiment, the host system 100 is, for example, in a normal operation mode, and the memory card reading device 110 provides the first power input P1 to the power control unit 230 , and the first power input P1 is, for example, 3.3 volts. In other exemplary embodiments, step S400 may also include receiving a second power input P2. Next, in step S402, divide the first power input P1 and provide the divided first power input P1' to the output terminal OUT of the power control unit 230 and the first power supply channel 232. Afterwards, in step S404, the reverse-divided first power input P1' is used as the first control signal Ctrl1 to control the supply of the first power input P1. In this step, if the power control unit 230 selectively does not configure the voltage dividing unit 238 , the reversed one is the first power input P1 . Next, in step S406 , according to the first control signal Ctrl1 , select to provide the first power input P1 to a smart card circuit 224 in the data processing control unit 220 . Next, in step S408 , the reverse voltage fed back from the first power input P1 to the second power input P2 is suppressed from being less than a specific value. In step S400, if the recipient includes the second power input P2, then step S408 further includes inhibiting the reverse voltage of the second power input P2 from feeding back to the first power input P1 to be less than the specified value.

FIG. 5 is a flow chart of steps of a power control method for a memory card according to another embodiment of the present invention. Please refer to FIG. 1 , FIG. 2 and FIG. 5 at the same time. The power control method of this embodiment is at least applicable to the memory card illustrated in FIG. 1 to FIG. 3 , and includes the following steps. In step S500, a second power input P2 is received. In this exemplary embodiment, the provision of the second power input P2 is that when the host system 100 detects the signal of the NFC reader device when approaching the NFC transmitter device, it decides to receive the second power input P2. At this time, the NFC reading device 120 provides the second power input P2 to the power control unit 230, and the memory card reading device 110 does not supply power, or the first power input P1 is in a low state. Next, in step S502 , according to the second control signal Ctrl2 , select to provide the second power input P2 to a smart card circuit 224 in the data processing control unit 220 . In this step, the first power input P1 is used as the second control signal Ctrl2 to turn on the second power supply channel 234 . Afterwards, in step S504, the reverse voltage fed back from the second power input P2 to the first power input P1 is suppressed from being less than a specific value.

In addition, the power control method of the embodiment of the present invention can obtain sufficient teachings, suggestions and implementation descriptions from the description of the embodiments in FIG. 1 to FIG. 3 , so the details are not repeated here.

To sum up, in the exemplary embodiment of the present invention, the memory card has the function of a smart card and can perform near-field wireless communication. Moreover, the provided power supply control method can make the internal smart card circuit of the memory card work normally under the condition that one of the dual power supplies is powered. In addition, by using the design structure of the voltage limiting unit, when any power input does not exist, the feedback reverse voltage can be suppressed from being less than a specific value to meet the design specification. At the same time, through the design method of linkage between the power input and the output end of the power control unit, the wrong operation of the voltage drop caused by the switching of the power input can be avoided.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention When depending on what is defined in the appended claims shall prevail.

Claims (21)

1. A memory card with smart card function, comprising: a flash memory unit; a data processing control unit, coupled to the flash memory unit, controls the flash memory unit, and encrypts, decrypts and stores a smart card security data; and a power control unit, coupled to the data processing control unit and the flash memory unit, receiving at least one of a first power input and a second power input, Wherein the power control unit selectively provides the first power input or the second power input to the data processing control unit according to at least one control signal, wherein the first power input is divided and the divided first power input is coupled to an output terminal of the power control unit, Wherein the power control unit includes: a first power supply channel for receiving the first power input; and A second power supply channel is used to receive the second power supply input, and the divided first power supply input is used to turn on the first power supply channel or the second power supply channel. 2. The memory card according to claim 1, wherein the first power supply channel determines whether to provide the first power input to the data processing control unit according to a first control signal, wherein the first control signal is reversed by The first power input after the voltage division is generated; and The second power supply channel determines whether to provide the second power input to the data processing control unit according to a second control signal, wherein the second control signal is generated by the divided first power input, Wherein the first control signal changes its state in response to the first power input to control the first power supply channel. 3. The memory card as claimed in claim 2, wherein the first power supply channel comprises: A first switch element has a first terminal, a second terminal and a control terminal, the first terminal receives the first power input, the second terminal is coupled to the output terminal of the power control unit; and A signal receiving unit has an input terminal and an output terminal, the input terminal of the signal receiving unit receives the first power input and processes it into the first control signal, the output terminal of the signal receiving unit is coupled to to the control terminal of the first switch element, and output the first control signal. 4. The memory card as claimed in claim 3, wherein the signal receiving unit comprises: An inverter, having the input terminal and the output terminal of the signal receiving unit, the input terminal receives the divided first power supply input, and inverts it into the first control signal, the signal receiving unit The output terminal is coupled to the control terminal of the first switch element, and outputs the first control signal. 5. The memory card as claimed in claim 2, wherein the second power supply channel comprises: A second switch element has a first end, a second end and a control end, the first end receives the second power input, the second end is coupled to the output end of the power control unit, and the The control terminal of the second switch element is used for receiving the second control signal. 6. The memory card as claimed in claim 2, wherein the power control unit further comprises: a voltage limiting unit, coupled between the first power supply channel and the second power supply channel, for preventing a reverse voltage fed back from the first power supply channel to the second power supply channel from being less than a specific value, Or suppress the reverse voltage fed back from the second power supply channel to the first power supply channel to be less than the specific value. 7. The memory card as claimed in claim 6, wherein the voltage limiting unit comprises: a first diode having an anode and a cathode, the anode is coupled to the first power input, and the cathode is coupled to a first switching element; and A second diode has an anode and a cathode, the anode is coupled to the second power input, and the cathode is coupled to a second switch element. 8. The memory card as claimed in claim 1, wherein the power control unit comprises: A voltage dividing unit has a first terminal, a second terminal and a voltage dividing node, the first terminal is coupled to the first power supply input, the second terminal is coupled to ground, and the voltage dividing unit is connected to the first power supply input A power input is divided, and the divided first power input is provided to the output terminal of the power control unit through the voltage dividing node. 9. The memory card as claimed in claim 8, wherein the voltage dividing unit comprises: A first resistor, one end of which serves as the first end of the voltage dividing unit and is coupled to the first power supply input, and the other end of the first resistor serves as the voltage dividing node and provides the first divided voltage power is input to the output of the power control unit; and a second resistor, coupled in series with the first resistor, one end of the second resistor is coupled to the other end of the first resistor, the other end of the second resistor is used as the second end of the voltage dividing unit and Coupled to ground. 10. The memory card as claimed in claim 1, wherein the data processing control unit comprises: a memory control circuit, coupled to the flash memory unit, and controls the flash memory unit; and A smart card circuit, coupled to the memory control circuit, encrypts, decrypts and stores the smart card security data, Wherein the smart card circuit receives the smart card security data from a host system or transmits the processed smart card security data to the host system through the memory control circuit; and the power control unit selects to provide the first power input or the second power supply input to the smart card circuit. 11. The memory card of claim 1, wherein the flash memory unit also stores the smart card security data. 12. The memory card of claim 1, wherein the first power input is provided by a memory card reader, and the second power input is provided by a near field communication reader. 13. A power control method for a memory card, the memory card comprising a power control unit and a data processing control unit, the power control method comprising: receiving at least one of a first power input and a second power input; dividing the first power input and coupling the divided first power input to an output terminal of the power control unit, and Selecting to provide the first power input or the second power input to a smart card circuit in the data processing control unit according to at least one of a first control signal and a second control signal; Wherein the power control unit includes: a first power supply channel for receiving the first power input, and a second power supply channel for receiving the second power input, and the divided first power input used to generate the first control signal, and the divided first power input is used to generate the second control signal. 14. The power control method as claimed in claim 13, wherein the step of selecting to provide the first power input or the second power input to the smart card circuit comprises: Whether to provide the first power input to the data processing control unit is determined according to the first control signal, wherein the first control signal changes its state in response to the first power input to control the supply of the first power input. 15. The power control method as claimed in claim 14, wherein the step of selecting to provide the first power input or the second power input to the smart card circuit further comprises: Inverting the divided first power input as the first control signal to control the supply of the first power input. 16. The power control method as claimed in claim 14, wherein the step of selecting to provide the first power input or the second power input to the smart card circuit further comprises: Whether to provide the second power input to the data processing control unit is determined according to the second control signal, wherein the divided first power input is used as the second control signal. 17. The power control method of claim 13, further comprising: A reverse voltage fed back from the first power input to the second power input is suppressed from being less than a specific value. 18. The power control method of claim 17, further comprising: The reverse voltage fed back from the second power input to the first power input is suppressed from being less than the specific value. 19. A power control circuit comprising: A first power supply channel, used to receive a first power input, and determine whether to provide the first power input to a data processing control unit according to a first control signal; a second power supply channel, used to receive a second power input, and determine whether to provide the second power input to the data processing control unit according to a second control signal; a voltage limiting unit, coupled between the first power supply channel and the second power supply channel, for preventing a reverse voltage fed back from the first power supply channel to the second power supply channel from being less than a specific value, or inhibit the reverse voltage fed back from the second power supply channel to the first power supply channel from being less than the specified value; and a voltage dividing unit, coupled to the first power input, for dividing the first power input and coupling the divided first power input to an output terminal of a power control unit, and the divided voltage The first power input is used to generate the first control signal, and the divided first power input is used to generate the second control signal. 20. The power control circuit as claimed in claim 19, wherein the conduction loss of the voltage input to the data processing control unit by the first power input or the second power input is less than 0.15V. 21. The power control circuit as claimed in claim 19, wherein the specified value is not greater than 60% of the corresponding power input or 1 volt.