CN103324599A - Inter-processor communication method and system on chip - Google Patents
Inter-processor communication method and system on chip Download PDFInfo
- Publication number
- CN103324599A CN103324599A CN2013102185188A CN201310218518A CN103324599A CN 103324599 A CN103324599 A CN 103324599A CN 2013102185188 A CN2013102185188 A CN 2013102185188A CN 201310218518 A CN201310218518 A CN 201310218518A CN 103324599 A CN103324599 A CN 103324599A
- Authority
- CN
- China
- Prior art keywords
- mailbox
- information
- processor
- passage
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Multi Processors (AREA)
Abstract
The invention provides an inter-processor communication method and a system on chip (SOC). The inter-processor communication method comprises of the steps of using a first processor in the SOC to write information into a memory space through at least one channel in a mailbox; configuring channel occupancy information of the mailbox after information writing is finished and sending an interruption request to a second processor, confirming the channel in the mailbox with written information according to the configured channel occupancy information of the mailbox after the second processor receives the interruption request, and reading the information from the memory space corresponding to the confirmed channel; receiving the information read by the second processor, updating the configured channel occupancy information of the mailbox, then sending a processing completion interruption request, and releasing occupancy of the channel finishing information reading in the mailbox according to the updated channel occupancy information of the mailbox. By means of the inter-processor communication method and the SOC, the resource utilization rate of the mailbox is improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to communication means and SOC(System On Chip between a kind of processor, system level chip).
Background technology
SOC is also referred to as system level chip or SOC (system on a chip), can be understood as the integrated circuit that has comprised microprocessor/microcontroller, storer and other specialized functional logic.Along with improving constantly of chip integration, more and more integrated a plurality of processor concurrent working in the SOC chip design is to satisfy the requirement of the growing data-handling capacity of people.
Such as; wireless communication process device among typical SOC; except using CPU; usually also need the relevant MCU(Micro Control Unit of integrated base band; micro-control unit), DSP(Digital Signal Processor; digital signal processor), comprise central cpu and graph and image processing GPU(Graphic Processing Unit, graphic process unit) multimedia processor etc.In real work, usually need collaborative work between these different processors, therefore swap data and control information need a preferably machine-processed information interaction that realizes between the processor, usually use the mailbox(mailbox in the present system) finish.
In traditional mailbox structure, usually do not support hyperchannel, each mailbox can only carry one group of information, and this is so that when communicating by letter between the different processes of two processors, needs use different mailbox, and the priority of process communication is difficult to guarantee.And, with respect to limited resource, need to be each mailbox assigned source processor ID and purpose processor ID, also be, be each mailbox stationary source processor and purpose processor, and the structures shape of mailbox itself consume ample resources, design needs to limit the mailbox number.In addition, carry out efficient and be subject to processing the impact of device quantity of information, processor needed first to file before using mailbox, if the mailbox resource is used up, then processor need to be inquired about wait.And, be not easy to expansion, when system increases processor, need to carry out larger modification to structure and the design of mailbox.
Summary of the invention
The invention provides communication means and SOC between a kind of processor, one of to address the above problem at least.
In order to address the above problem, the invention discloses a kind of inter-processor communication method, comprise: the first processor in the system level chip by at least one passage among the mailbox mailbox corresponding with described first processor to corresponding storage space writing information, wherein, described mailbox is that described system level chip is that signal post between the second processor in described first processor and the described system level chip distributes, and each mailbox comprises a plurality of passages; Described first processor is after writing described information and finishing, configure the passage occupied information of described mailbox, and to described the second processor transmission request interruption, causing described the second processor to receive in the described request has no progeny, passage occupied information according to the described mailbox that configures, determine to write the passage among the mailbox of described information, and from storage space corresponding to the described passage determined reading information; Described first processor receives described the second processor and has read described information and upgraded the interruption of finishing dealing with that sends behind the passage occupied information of described mailbox, and according to the passage occupied information of the described mailbox after upgrading, remove having finished taking of passage that information reads among the described mailbox.
Preferably, the step that described first processor configures the passage occupied information of described mailbox comprises: described first processor configures the passage occupied information of described mailbox by the information of configuration register described mailbox, corresponding with described first processor; Then, the step of the passage occupied information of the described mailbox of described the second update processor comprises: described the second processor upgrades the passage occupied information of described mailbox by the information of configuration register described mailbox, corresponding with described the second processor.
Preferably, described first processor configure described mailbox, comprise with the step of the information of register corresponding to described first processor: described first processor arranges in the initiation request register of described mailbox, the bit corresponding with the passage of writing information, resource with the passage of request said write information, wherein, described initiation request register is for the resource of applying for described at least one passage; Setting according to described initiation request register, arrange in the status register of described mailbox, the bit corresponding with the passage of writing information, to indicate described passage occupied, wherein, described status register is used to indicate the state of described at least one passage.
Preferably, described the second processor is according to the passage occupied information of described mailbox of configuration, and the step of determining to write the passage among the mailbox of described information comprises: described the second processor determines to write passage among the mailbox of described information according to arranging of the bit of the status register of described mailbox.
Preferably, described the second processor configure described mailbox, comprise with the step of the information of register corresponding to described the second processor: described the second processor arranges in the register of finishing dealing with of described mailbox, the bit corresponding with the passage that has read information, read with the information of indicating described passage and to have finished, wherein, the described register of the finishing dealing with information that is used to indicate described a plurality of passages reads and finishes; Described the second processor is according to the setting of the described register of finishing dealing with, and arranges in the status register of described mailbox, the bit corresponding with the passage that has read information, takies to indicate described passage to remove.
Preferably, described first processor is according to the passage occupied information of the described mailbox after upgrading, releasing comprises the step that takies of the passage having finished information among the described mailbox and read: described first processor determines to have finished among the described mailbox passage that information reads according to the setting of the bit of the status register of described mailbox; Releasing takies the passage having finished information among the described mailbox and read.
Preferably, the number of the number of the bit of the number of the bit of described status register, described initiation request register and the bit of the described register of finishing dealing with, all the number with the passage of described mailbox is identical.
In order to address the above problem, the invention also discloses a kind of system level chip, comprising: first processor, the second processor and mailbox mailbox; Wherein, described first processor comprises: writing module, be used at least one passage by the mailbox mailbox corresponding with described first processor to corresponding storage space writing information, wherein, described mailbox is that described system level chip is that signal post between the second processor in described first processor and the described system level chip distributes, and each mailbox comprises a plurality of passages; The request interrupt module, be used for after writing described information and finishing, configure the passage occupied information of described mailbox, and to described the second processor transmission request interruption, causing described the second processor to receive in the described request has no progeny, according to the passage occupied information of described mailbox of configuration, determine to write the passage among the mailbox of described information, and from storage space corresponding to the described passage determined reading information; Remove module, being used for receiving described the second processor has read described information and has upgraded the interruption of finishing dealing with that sends behind the passage occupied information of described mailbox, and according to the passage occupied information of the described mailbox after upgrading, remove having finished taking of passage that information reads among the described mailbox.
Preferably, the described request interrupt module, concrete being used for after writing described information and finishing, by configuring the information of register described mailbox, corresponding with described first processor, configure the passage occupied information of described mailbox, and send the request interruption to described the second processor; Described the second processor is used for having read described information and by configuring the information of register described mailbox, corresponding with described the second processor, upgrades the passage occupied information of described mailbox.
Preferably, the described request interrupt module, concrete being used for after writing described information and finishing, arrange in the initiation request register of described mailbox, the bit corresponding with the passage of writing information, resource with the passage of request said write information, wherein, described initiation request register is for the resource of applying for described at least one passage; And, according to the setting of described initiation request register, arrange in the status register of described mailbox, the bit corresponding with the passage of writing information, occupied to indicate described passage, wherein, described status register is used to indicate the state of described at least one passage.
Preferably, described the second processor also is used for the mailbox passage of determining to write described information that arranges according to the bit of the status register of described mailbox.
Preferably, described the second processor, concrete for the register of finishing dealing with of described mailbox, the bit corresponding with the passage that has read information are set, read with the information of indicating described passage and to have finished, wherein, the described register of the finishing dealing with information that is used to indicate described a plurality of passages reads and finishes; And according to the setting of the described register of finishing dealing with, arrange in the status register of described mailbox, the bit corresponding with the passage that has read information, take to indicate described passage to remove.
Preferably, described releasing module, the concrete setting that is used for according to the bit of the status register of described mailbox determines to have finished among the described mailbox passage that information reads; Releasing takies the passage having finished information among the described mailbox and read.
Compared with prior art, the present invention has the following advantages:
Among the present invention, the mailbox of SOC comprises a plurality of passages; And, when having processor need to use mailbox communication, for processor is specified available mailbox flexibly; Each passage of mailbox, is determined corresponding storage space by determining occupied passage, and then the information of this storage space is carried out corresponding read-write operation when processor communicates corresponding storage space should be arranged.Because mailbox of the present invention supports hyperchannel, can make and use same mailbox to carry out process communication between two processors, clearly distinguish the process of using different information thereby can make between the processor of communication, guarantee the priority of process communication; In the present invention, the each mailbox that uses of processor is by the SOC flexible allocation, and each mailbox is the processor of fixing use, thereby has saved the mailbox resource, has improved mailbox and has used dirigibility; The mailbox that uses because processor is each is by the SOC flexible allocation, as long as idle mailbox resource is arranged, processor can be applied for obtaining, and need not wait for; In addition, because the processor on-fixed uses fixing mailbox resource, therefore, even system increases processor, also need not carry out larger modification to mailbox structure and design, save the realization cost, improve the mailbox resource utilization.
Description of drawings
Fig. 1 is the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention one;
Fig. 2 is the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention two;
Fig. 3 is the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention three;
Fig. 4 is the structural representation of the mailbox among a kind of SOC in embodiment illustrated in fig. 3;
Fig. 5 is the structured flowchart according to a kind of SOC of the embodiment of the invention four.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
In the embodiment of the invention, comprise two or more processors among the SOC.
Embodiment one
With reference to Fig. 1, show the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention one.
The inter-processor communication method of the present embodiment may further comprise the steps:
First processor among the step S102:SOC by at least one passage among the mailbox corresponding with first processor to corresponding storage space writing information.
Wherein, mailbox is that SOC is that signal post between the second processor among first processor and the SOC distributes, and each mailbox comprises a plurality of passages.
In the present embodiment, SOC comprises a plurality of processors, and these a plurality of processors comprise first processor and the second processor.In concrete the application, the number of processor is determined by system requirements, in the SOC that uses mailbox, comprises at least two processors.Among the present invention, the concrete number of the processor that SOC is not comprised is restricted.
Mailbox is a kind of mailbox kernel component, is used for sending between multiprocessor message.The mailbox kernel contains two mutexes, and assurance is to unique write access of shared storage, and another guarantees the unique read access to shared storage, and it uses with the independent shared storer, realizes the message queue communication between processor.The mailbox kernel is suitable for unidirectional message communicating between dual processor, and function is equivalent to the FIFO buffer queue, and the message back of its transmission replaces actual data transmission toward being the pointer that points to shared drive block structure body, improves exchanges data efficient.
First processor among the step S104:SOC is after writing information is finished, the passage occupied information of configuration mailbox, and the second processor in SOC sends the request interruption, causing the second processor to receive in the request has no progeny, passage occupied information according to the mailbox that configures, determine the passage among the mailbox of writing information, and from storage space corresponding to the passage determined reading information.
As mentioned above, mailbox uses with shared storage, and each mailbox is corresponding to certain storage space, and each passage of each mailbox has corresponding position and storage space in this storage space.
When first processor sent information by mailbox to the second processor, the information of transmission can take part even whole storage space corresponding to passage in a plurality of passages.First processor can the collocation channel occupied information and send request to the second processor and interrupt after the information of finishing writes, and receives information to inform the second processor.The second processor can be had no progeny in the request of receiving and can be determined passage among the mailbox of writing information according to the passage occupied information, and from storage space corresponding to the passage determined reading information.
First processor among the step S106:SOC receives the second processor and has read information and upgraded the interruption of finishing dealing with that sends behind the passage occupied information of mailbox, and according to the passage occupied information of the mailbox after upgrading, remove having finished taking of passage that information reads among the mailbox.
The second processor among the SOC is had no progeny in receiving request, can determine that at first which passage is occupied according to the passage occupied information, the position of the storage space that these passages are corresponding, then, reading information from storage space corresponding to occupied passage (also namely, having write the passage of information).Then, upgrade this passage occupied information, so that the passage occupied information of first processor after can upgrading according to this, remove having finished taking of passage that information reads among the mailbox.
In the present embodiment, the mailbox of SOC comprises a plurality of passages; And, when having processor need to use mailbox communication, for processor is specified available mailbox flexibly; Each passage of mailbox, is determined corresponding storage space by determining occupied passage, and then the information of this storage space is carried out corresponding read-write operation when processor communicates corresponding storage space should be arranged.Because the mailbox of the present embodiment supports hyperchannel, can make and use same mailbox to carry out process communication between two processors, clearly distinguish the process of using different information thereby can make between the processor of communication, guarantee the priority of process communication; In the present embodiment, the each mailbox that uses of processor is by the SOC flexible allocation, and each mailbox is the processor of fixing use, thereby has saved the mailbox resource, has improved mailbox and has used dirigibility; The mailbox that uses because processor is each is by the SOC flexible allocation, as long as idle mailbox resource is arranged, processor can be applied for obtaining, and need not wait for; In addition, because the processor on-fixed uses fixing mailbox resource, therefore, even system increases processor, also need not carry out larger modification to mailbox structure and design, save the realization cost, improve the mailbox resource utilization.
In the embodiment of the invention, first processor is after writing information is finished, need the passage occupied information of configuration mailbox, particularly, can configure in several ways the passage occupied information of mailbox, for example: by the information of configuration register mailbox, corresponding with first processor, configure the passage occupied information of mailbox; Perhaps, carry the message of passage occupied information by generation, configure the passage occupied information of mailbox.
Like this, the passage occupied information of the second update processor mailbox comprises: by the information of configuration register mailbox, corresponding with the second processor, upgrade the passage occupied information of mailbox, perhaps, directly upgrade the message of carrying the passage occupied information, upgrade the passage occupied information of mailbox.
Certainly, other configuration or the passage occupied information mode of upgrading mailbox can use with the embodiment of the invention in, just enumerated no longer one by one.
Embodiment two
With reference to Fig. 2, show the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention two.
The inter-processor communication method of the present embodiment may further comprise the steps:
Step S202: the mailbox among the SOC is set.
In the present embodiment, arrange mailbox comprise a plurality of passages, the indication a plurality of passages state status register, the application a plurality of passages the initiation request register and indicate the information of a plurality of passages to read the register of finishing dealing with of finishing.Wherein, the register corresponding with the processor (being first processor in the present embodiment) of data writing comprises initiation request register and status register; The register corresponding with the processor (being the second processor in the present embodiment) of reading out data comprises finish dealing with register and status register.Also namely, status register is shared by two processors, transmits relevant information between two processors.
After mailbox among the SOC arranges and finishes, can in follow-up multiprocessor communication process, use always.Need to prove, above-mentioned status register, initiate request register and the register of finishing dealing with can exist simultaneously; Status register also can only be set and initiate request register, and the register of finishing dealing with substitutes realization by alternate manner; Status register can also only be set and the register of finishing dealing with, substitute realization and initiate request register by alternate manner.
Preferably, in the present embodiment, the number of the bit of the number of the bit of status register, the number of bit of initiating request register and the register of finishing dealing with, all the number with the passage of mailbox is identical.It is identical with the number of the passage of mailbox that the number of the bit of above-mentioned a plurality of registers is set to, the passage situation that can indicate mailbox on the one hand, this clear and definite indicating mode has also been accelerated processor carries out process communication by mailbox speed on the other hand explicitly.But be not limited to this, in actual applications, the number of the bit between above-mentioned a plurality of registers can be identical or different, and the number of the number of the bit of above-mentioned a plurality of registers and the passage of mailbox also can be identical or different.The restriction of the number of the bit of register, the number that can satisfy the passage of indication mailbox gets final product.
Step S204: when the first processor among the SOC and the second processor need to communicate by mailbox, SOC was first processor and the second processor distribution mailbox.
Have a plurality of processors among the SOC, comprise first processor and the second processor in these a plurality of processors.Also comprise a plurality of mailbox among the SOC, the number of mailbox can suitably be set by those skilled in the art according to the number of processor.Each mailbox has the characteristic of one-way communication, and for example, the needs if CPU1 and CPU2 communicate by letter each other need two mailbox usually.But the traffic from CPU1 to CPU2 and the traffic from CPU2 to CPU1 are possible different, such as CPU1-〉CPU2 has two mailbox, CPU2-〉CPU1 has a mailbox.Can select as required to set the number of mailbox, the demand when farthest satisfying all processors needs communicate simultaneously.But be not limited to this, the number of the actual mailbox that arranges also can be greater than demand, to make things convenient for the expansion of SOC processor; Also demand can be slightly less than, take the actual demand that can satisfy processor communication as principle, SOC resource and space can be saved.Certainly, in some cases, also a mailbox may only need be set.
When the first processor of communicating by letter for needs and the second processor distribution mailbox, optional one gets final product from the mailbox of free time.
Storage space writing information corresponding to part or all of passage of the first processor of step S206:SOC in a plurality of passages of mailbox, and write finish after, the information of configuration register mailbox, corresponding with first processor, and to the second processor transmission request interruption.
In the present embodiment, because the register corresponding with first processor that arranges comprises: initiate request register and status register, therefore, this step can comprise: storage space writing information corresponding to part or all of passage of first processor in a plurality of passages of mailbox; Write finish after, arrange initiate in the request register, the bit corresponding with the passage of writing information, with the resource of the passage of asking writing information; And then, according to the setting of initiating request register, arrange in the status register, the bit corresponding with the passage of writing information, occupied to indicate described passage; Simultaneously, the request of producing is interrupted and is sent to the second processor.Arrange and initiate corresponding bit in the request register, can make clear and definite which passage of status register occupied, and then according to the state that corresponding bits position in the change status register is set of initiating bit in the request register, the follow-up information side of reading that offers of the state of bit in this status register, i.e. the second processor has information for reading so that the second processor is known in which passage among the mailbox.
The second processor of step S208:SOC receives request and interrupts, and according to the information of register mailbox, corresponding with first processor after the configuration, determines the passage of writing information, and from storage space corresponding to definite passage reading information.
Preferably, because of the register corresponding with first processor, and all include status register in the register corresponding with the second processor, and in the above-mentioned steps, first processor is writing the information that has configured status register after described information is finished, therefore, the second processor can be according to the passage of determining writing information that arranges of the bit of status register when determining the passage of writing information, so from storage space corresponding to the passage determined reading information.
After the second processor of step S210:SOC has read information, configure the information of register mailbox, corresponding with the second processor, and finish interruption to the first processor transmission processing.
Because register corresponding with the second processor in the present embodiment includes status register and the register of finishing dealing with, therefore, preferably, this step comprises: after the second processor has read information, set handling finishes in the register, the bit corresponding with the passage that has read information, read with the information of indicating described passage and finished; According to the setting of the register of finishing dealing with, arrange in the status register, the bit corresponding with the passage that has read information, take to indicate described passage to remove; Simultaneously, produce to finish dealing with and interrupt and send to first processor.Set handling is finished corresponding bit in the register, information in clear and definite which passage of status register is read, can remove and take, and then according to the state of corresponding bits position in the change status register that arranges of bit in the register of finishing dealing with, the follow-up information side of writing that offers of the state of bit in this status register, be first processor, be read so that first processor is known the information in which passage among the mailbox, can re-use.
The first processor reception ﹠ disposal of step S212:SOC is finished interruption, and according to the information of register mailbox, corresponding with the second processor after the configuration, determine to have finished among the mailbox passage that information reads, remove having finished taking of passage that information reads among the mailbox.
Preferably, in the present embodiment, the register corresponding with first processor, and all include status register in the register corresponding with the second processor, like this, the first processor reception ﹠ disposal is had no progeny in finishing, can be according to the setting of the bit of status register, determine to have finished among the mailbox passage that information reads, remove having finished taking of passage that information reads among the mailbox.These have been finished the passage that information reads and can be continued to use by first processor, and writing information passes to the second processor, continues to communicate by letter with the second processor.
Need to prove, step S210 to step S212 be preferred steps, in actual applications, information in the mailbox passage has been read and has determined to have finished the passage that information reads and also can adopt other appropriate ways to realize, as in message, carrying the corresponding information of having finished the passage that information reads, and then according to mode of this information updating channel status etc.
Pass through the present embodiment, realized the flexible communications of processor by mailbox, mailbox support hyperchannel because of the present embodiment, can make and use same mailbox to carry out process communication between two processors, clearly distinguish the process of using different information between the processor of communication thereby can make, guarantee the priority of process communication; In the present embodiment, the each mailbox that uses of processor is by the SOC flexible allocation, and each mailbox is the processor of fixing use, thereby has saved the mailbox resource, has improved mailbox and has used dirigibility; The mailbox that uses because processor is each is by the SOC flexible allocation, as long as idle mailbox resource is arranged, processor can be applied for obtaining, and need not wait for; In addition, because the processor on-fixed uses fixing mailbox resource, therefore, even system increases processor, also need not carry out larger modification to mailbox structure and design, save the realization cost, improve the mailbox resource utilization.
Embodiment three
With reference to Fig. 3, show the flow chart of steps according to a kind of inter-processor communication method of the embodiment of the invention three.
The inter-processor communication method of the present embodiment may further comprise the steps:
Step S302: the mailbox among the SOC is set.
In the present embodiment, each the mailbox resource that arranges among the SOC comprises 32 bit status registers (CHNL_STTS), and (REQ_INT) and 1 interruption (ACK_INT) of finishing dealing with are interrupted in 1 request; In addition, for convenient a plurality of processors are finished the request of mailbox and the control of finishing dealing with, need extra two 32 interface registers of realizing, one for initiating request register (CHNL_SET), one is the register of finishing dealing with (CHNL_CLR), and the structure of the above-mentioned mailbox of setting as shown in Figure 4.Wherein, CHNL_STTS represents 32 channel statuses that this mailbox is corresponding, and establishing 1 expression has data, the countless certificates of 0 expression, and processor is controlled the set and clear 0 of each bit of CHNL_STTS by operation CHNL_SET register and CHNL_CLR register.
In general, the access of system bus is taken 32 bits usually, therefore, the mailbox in the present embodiment is set to 32 passages, and above-mentioned a plurality of registers of setting also are 32 accordingly.But be not limited to this, in actual applications, those skilled in the art can suitably arrange according to actual conditions, as are 64 or are that 16 or 8 etc. all can.
Step S304:SOC is that mailbox distributes sender and recipient.
When having processor need to carry out mailbox communication, SOC is processor distribution mailbox, mailbox for a free time, also be that SOC is that mailbox distributes the sender (namely to send the processor of information, such as first processor) and recipient's (namely receiving the processor of information, such as the second processor).
Before each mailbox uses, all need to specify a sender and recipient for it, concerning the sender, need to receive the interruption of finishing dealing with of mailbox, concerning the recipient, the request that needs to receive mailbox is interrupted.When realizing, can shield for the unconcerned interrupt source of processor with OIER.
Step S306: when the sender uses certain passage of the mailbox of distribution to send information, at first information is write the shared storage corresponding to this mailbox passage of making an appointment.
Step S308: the sender initiates write operation to CHNL_SET corresponding to this mailbox, exists the channel bit of transmission information to write 1 corresponding mailbox, and other position writes 0.
Step S310:SOC can will write 1 corresponding bit position 1 among the CHNL_STTS with among the CHNL_SET, and the request that produces simultaneously mailbox is interrupted.
Step S312: the recipient detects this request and interrupts, and further reads the CHNL_STTS register, inquires about which passage and has information, then the shared storage reading information from making an appointment.
Step S314: after the recipient handles information, initiate write operation to CHNL_CLR corresponding to mailbox, the finish dealing with channel bit of information of corresponding mailbox is write 1, other position writes 0.
Step S316:SOC can with among the CHNL_STTS with to write 1 corresponding bit position clear 0 among the CNNL_CLR, the interruption of finishing dealing with that produces simultaneously mailbox.
Step S318: the sender detects the interruption of finishing dealing with, and reads the CHNL_STTS register, inquires about which passage and finishes dealing with, and removes having finished taking of passage that information reads among the mailbox.
By the present embodiment, mailbox internal support hyperchannel, the different processes of being convenient to processor are used different passage interactive information, and software can freely determine the priority of different channel informations; Resource is simplified, realize simple, each mailbox only has 32 registers, and 32 passages are provided simultaneously, greatly reduces the mailbox resources costs, the information that passage carries is directly used shared storage, such as the DDR particle, do not have extra resource, with respect to traditional implementation under same hardware size, can realize more mailbox, for a plurality of processor distribution; Carry out efficient higher, mailbox determined transmit leg processor and take over party's processor before using, be these two processor special uses in a communication process, did not need during use again to apply for; Simultaneously, each mailbox can specify arbitrarily sender and recipient, makes it very flexible in application; Be easy to expansion, when system's increase more during multiprocessor, can use that to keep existing mailbox resource constant, only add newly-increased processor and interrupt an enable configuration register and get final product; When system need to increase the mailbox resource, can increase register corresponding to mailbox in former design, the interruption enable configuration register that expands simultaneously processor need not to revise original circuit.
Embodiment four
With reference to Fig. 5, show the structured flowchart according to a kind of SOC of the embodiment of the invention four.
The SOC of the present embodiment has structurally adopted at least two processors, and one, two or more mailbox wherein, comprise first processor and the second processor in the present embodiment in a plurality of processors, and each mailbox all adopts multi-channel structure.
Communicate as example by mailbox with first processor and the second processor, first processor among the SOC of the present embodiment comprises: writing module 402, be used at least one passage by the mailbox corresponding with first processor to corresponding storage space writing information, wherein, mailbox is that SOC is that signal post between the second processor among first processor and the SOC distributes, and each mailbox comprises a plurality of passages; Request interrupt module 404, be used for after writing information is finished, the passage occupied information of configuration mailbox, and to the second processor transmission request interruption, causing the second processor to receive in the request has no progeny, according to the passage occupied information of mailbox of configuration, determine the passage among the mailbox of writing information, and from storage space corresponding to the passage determined reading information; Remove module 406, being used for receiving the second processor has read information and has upgraded the interruption of finishing dealing with that sends behind the passage occupied information of mailbox, and according to the passage occupied information of the mailbox after upgrading, remove having finished taking of passage that information reads among the mailbox.
Preferably, request interrupt module 404 is concrete for after writing information is finished, and by the information of configuration register mailbox, corresponding with first processor, configures the passage occupied information of mailbox, and interrupts to the second processor transmission request; The second preparation implement body is used for the information that read and by configuring the information of register mailbox, corresponding with the second processor, upgrades the passage occupied information of mailbox.
Preferably, request interrupt module 404 is after writing information is finished, when configuring the information of register mailbox, corresponding with first processor: after writing information is finished, arrange in the initiation request register of mailbox, the bit corresponding with the passage of writing information, the resource of passage with the request writing information, wherein, initiate the resource that request register is used at least one passage of application; According to the setting of initiating request register, arrange in the status register of mailbox, the bit corresponding with the passage of writing information, to indicate passage occupied, wherein, status register is used to indicate the state of at least one passage.
Preferably, the second processor is at the passage occupied information of mailbox according to configuration, and when determining the passage among the mailbox of writing information: the second processor is according to the passage among the mailbox that determines writing information that arranges of the bit of the status register of mailbox.
Preferably, the second processor configuration mailbox, during with the information of register corresponding to the second processor: the second processor arranges in the register of finishing dealing with of mailbox, and read the corresponding bit of the passage of information, information with the indication passage has read and has finished, wherein, finish dealing with information that register is used to indicate a plurality of passages reads and finishes; According to the setting of the register of finishing dealing with, arrange in the status register of mailbox, the bit corresponding with the passage that has read information, remove taking with the indication passage.
Preferably, remove module 406 at the passage occupied information according to the mailbox after upgrading, releasing is during to the taking of the passage having finished information among the mailbox and read: according to the setting of the bit of the status register of mailbox, determine to have finished among the mailbox passage that information reads; Releasing takies the passage having finished information among the described mailbox and read.
Preferably, the number of the bit of the number of the bit of status register, the number of bit of initiating request register and the register of finishing dealing with, all the number with the passage of mailbox is identical.
The SOC of the present embodiment is used for realizing the corresponding inter-processor communication method of aforementioned a plurality of embodiment of the method, and the beneficial effect with corresponding embodiment of the method, does not repeat them here.
The invention provides the communication plan between the processor of a kind of SOC, in this scheme, proposed a kind of mailbox circuit structure, can support between a plurality of processors, based on multichannel communication mechanism.This mailbox circuit structure adopts the hyperchannel design, send the request interruption and finish dealing with the interrupt operation communication process by passage, can specify flexibly sender and the recipient of mailbox, resource is little, be easy to expansion, thereby have low cost, use flexibly characteristics, be easy to expand to the more communication structure of multiprocessor.Through actual testing authentication, mailbox structure decrease of the present invention the design resource, optimized software flow, be convenient to the Control on Communication of the different processes of multiprocessor, be easy to simultaneously exploitation and integrated, improved the dirigibility of using and designed extensibility.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For SOC embodiment because itself and embodiment of the method basic simlarity, so describe fairly simple, relevant part gets final product referring to the part explanation of embodiment of the method.
Above a kind of inter-processor communication method provided by the present invention and SOC are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (13)
1. an inter-processor communication method is characterized in that, comprising:
First processor in the system level chip by at least one passage among the mailbox mailbox corresponding with described first processor to corresponding storage space writing information, wherein, described mailbox is that described system level chip is that signal post between the second processor in described first processor and the described system level chip distributes, and each mailbox comprises a plurality of passages;
Described first processor is after writing described information and finishing, configure the passage occupied information of described mailbox, and to described the second processor transmission request interruption, causing described the second processor to receive in the described request has no progeny, passage occupied information according to the described mailbox that configures, determine to write the passage among the mailbox of described information, and from storage space corresponding to the described passage determined reading information;
Described first processor receives described the second processor and has read described information and upgraded the interruption of finishing dealing with that sends behind the passage occupied information of described mailbox, and according to the passage occupied information of the described mailbox after upgrading, remove having finished taking of passage that information reads among the described mailbox.
2. method according to claim 1 is characterized in that, the step that described first processor configures the passage occupied information of described mailbox comprises:
Described first processor configures the passage occupied information of described mailbox by the information of configuration register described mailbox, corresponding with described first processor;
Then, the step of the passage occupied information of the described mailbox of described the second update processor comprises:
Described the second processor upgrades the passage occupied information of described mailbox by the information of configuration register described mailbox, corresponding with described the second processor.
3. method according to claim 2 is characterized in that, the step that described first processor configures the information of register described mailbox, corresponding with described first processor comprises:
Described first processor arranges in the initiation request register of described mailbox, the bit corresponding with the passage of writing information, resource with the passage of request said write information, wherein, described initiation request register is for the resource of applying for described at least one passage;
Setting according to described initiation request register, arrange in the status register of described mailbox, the bit corresponding with the passage of writing information, to indicate described passage occupied, wherein, described status register is used to indicate the state of described at least one passage.
4. method according to claim 3 is characterized in that, described the second processor is according to the passage occupied information of described mailbox of configuration, and the step of determining to write the passage among the mailbox of described information comprises:
Described the second processor determines to write passage among the mailbox of described information according to arranging of the bit of the status register of described mailbox.
5. method according to claim 2 is characterized in that, the step that described the second processor configures the information of register described mailbox, corresponding with described the second processor comprises:
Described the second processor arranges in the register of finishing dealing with of described mailbox, the bit corresponding with the passage that has read information, read with the information of indicating described passage and to have finished, wherein, the described register of the finishing dealing with information that is used to indicate described a plurality of passages reads and finishes;
Described the second processor is according to the setting of the described register of finishing dealing with, and arranges in the status register of described mailbox, the bit corresponding with the passage that has read information, takies to indicate described passage to remove.
6. method according to claim 5 is characterized in that, described first processor is according to the passage occupied information of the described mailbox after upgrading, and the step that takies of removing having finished the passage that information reads among the described mailbox comprises:
Described first processor determines to have finished among the described mailbox passage that information reads according to the setting of the bit of the status register of described mailbox;
Releasing takies the passage having finished information among the described mailbox and read.
7. according to claim 5 or 6 described methods, it is characterized in that, the number of the bit of the number of the bit of the number of the bit of described status register, described initiation request register and the described register of finishing dealing with, all the number with the passage of described mailbox is identical.
8. a system level chip is characterized in that, comprising: first processor, the second processor and mailbox mailbox;
Wherein, described first processor comprises:
Writing module, be used at least one passage by the mailbox mailbox corresponding with described first processor to corresponding storage space writing information, wherein, described mailbox is that described system level chip is that signal post between the second processor in described first processor and the described system level chip distributes, and each mailbox comprises a plurality of passages;
The request interrupt module, be used for after writing described information and finishing, configure the passage occupied information of described mailbox, and to described the second processor transmission request interruption, causing described the second processor to receive in the described request has no progeny, according to the passage occupied information of described mailbox of configuration, determine to write the passage among the mailbox of described information, and from storage space corresponding to the described passage determined reading information;
Remove module, being used for receiving described the second processor has read described information and has upgraded the interruption of finishing dealing with that sends behind the passage occupied information of described mailbox, and according to the passage occupied information of the described mailbox after upgrading, remove having finished taking of passage that information reads among the described mailbox.
9. system level chip according to claim 8 is characterized in that,
The described request interrupt module, concrete being used for after writing described information and finishing, by configuring the information of register described mailbox, corresponding with described first processor, configure the passage occupied information of described mailbox, and send the request interruption to described the second processor;
Described the second processor is used for having read described information and by configuring the information of register described mailbox, corresponding with described the second processor, upgrades the passage occupied information of described mailbox.
10. system level chip according to claim 9 is characterized in that,
The described request interrupt module, concrete being used for after writing described information and finishing, arrange in the initiation request register of described mailbox, the bit corresponding with the passage of writing information, resource with the passage of request said write information, wherein, described initiation request register is for the resource of applying for described at least one passage; And,
Setting according to described initiation request register, arrange in the status register of described mailbox, the bit corresponding with the passage of writing information, to indicate described passage occupied, wherein, described status register is used to indicate the state of described at least one passage.
11. system level chip according to claim 10 is characterized in that,
Described the second processor also is used for the mailbox passage of determining to write described information that arranges according to the bit of the status register of described mailbox.
12. system level chip according to claim 9 is characterized in that,
Described the second processor, concrete for the register of finishing dealing with of described mailbox, the bit corresponding with the passage that has read information are set, read with the information of indicating described passage and to have finished, wherein, the described register of the finishing dealing with information that is used to indicate described a plurality of passages reads and finishes; And according to the setting of the described register of finishing dealing with, arrange in the status register of described mailbox, the bit corresponding with the passage that has read information, take to indicate described passage to remove.
13. system level chip according to claim 12 is characterized in that,
Described releasing module, the concrete setting that is used for according to the bit of the status register of described mailbox determines to have finished among the described mailbox passage that information reads; Releasing takies the passage having finished information among the described mailbox and read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102185188A CN103324599A (en) | 2013-06-04 | 2013-06-04 | Inter-processor communication method and system on chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102185188A CN103324599A (en) | 2013-06-04 | 2013-06-04 | Inter-processor communication method and system on chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103324599A true CN103324599A (en) | 2013-09-25 |
Family
ID=49193353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102185188A Pending CN103324599A (en) | 2013-06-04 | 2013-06-04 | Inter-processor communication method and system on chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103324599A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106372029A (en) * | 2016-09-06 | 2017-02-01 | 北方电子研究院安徽有限公司 | Point-to-point on-chip communication module based on interruption |
| CN108062234A (en) * | 2017-12-07 | 2018-05-22 | 郑州云海信息技术有限公司 | A kind of system and method that BMC FLASH are accessed by mailbox protocol realizations server host |
| WO2020118721A1 (en) * | 2018-12-14 | 2020-06-18 | 华为技术有限公司 | Multi-processor system and inter-processor communication method |
| TWI703501B (en) * | 2018-08-23 | 2020-09-01 | 慧榮科技股份有限公司 | Multi-processor system having distributed mailbox architecture and communication method thereof |
| CN111930676A (en) * | 2020-09-17 | 2020-11-13 | 湖北芯擎科技有限公司 | Method, device, system and storage medium for communication among multiple processors |
| CN113110950A (en) * | 2021-05-18 | 2021-07-13 | 南方电网科学研究院有限责任公司 | Processor, communication method, storage medium, and computing device |
| CN115599459A (en) * | 2022-12-13 | 2023-01-13 | 成都启英泰伦科技有限公司（Cn） | Cross-power-domain multiprocessor operation device and communication method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060200257A1 (en) * | 2005-03-03 | 2006-09-07 | Hans-Herbert Kirste | Microprocessor system for a machine controller in safety-certifiable applications |
| CN1964285A (en) * | 2006-12-13 | 2007-05-16 | 杭州华为三康技术有限公司 | A master control device with double CPU and realization method |
| CN101226519A (en) * | 2007-01-17 | 2008-07-23 | 三星电子株式会社 | Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof |
| CN101788973A (en) * | 2010-01-12 | 2010-07-28 | 深圳市同洲电子股份有限公司 | Method for communication between dual processors |
-
2013
- 2013-06-04 CN CN2013102185188A patent/CN103324599A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060200257A1 (en) * | 2005-03-03 | 2006-09-07 | Hans-Herbert Kirste | Microprocessor system for a machine controller in safety-certifiable applications |
| CN1964285A (en) * | 2006-12-13 | 2007-05-16 | 杭州华为三康技术有限公司 | A master control device with double CPU and realization method |
| CN101226519A (en) * | 2007-01-17 | 2008-07-23 | 三星电子株式会社 | Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof |
| CN101788973A (en) * | 2010-01-12 | 2010-07-28 | 深圳市同洲电子股份有限公司 | Method for communication between dual processors |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106372029A (en) * | 2016-09-06 | 2017-02-01 | 北方电子研究院安徽有限公司 | Point-to-point on-chip communication module based on interruption |
| CN108062234B (en) * | 2017-12-07 | 2021-07-27 | 郑州云海信息技术有限公司 | System and method for realizing server host to access BMC FLASH through mailbox protocol |
| CN108062234A (en) * | 2017-12-07 | 2018-05-22 | 郑州云海信息技术有限公司 | A kind of system and method that BMC FLASH are accessed by mailbox protocol realizations server host |
| US11314571B2 (en) | 2018-08-23 | 2022-04-26 | Silicon Motion, Inc. | Multi-processor system with distributed mailbox architecture and communication method thereof |
| TWI703501B (en) * | 2018-08-23 | 2020-09-01 | 慧榮科技股份有限公司 | Multi-processor system having distributed mailbox architecture and communication method thereof |
| CN111742306A (en) * | 2018-12-14 | 2020-10-02 | 华为技术有限公司 | Multiprocessor system and communication method between processors |
| WO2020118721A1 (en) * | 2018-12-14 | 2020-06-18 | 华为技术有限公司 | Multi-processor system and inter-processor communication method |
| CN111742306B (en) * | 2018-12-14 | 2024-10-18 | 华为技术有限公司 | Multiprocessor system and inter-processor communication method |
| CN111930676A (en) * | 2020-09-17 | 2020-11-13 | 湖北芯擎科技有限公司 | Method, device, system and storage medium for communication among multiple processors |
| CN111930676B (en) * | 2020-09-17 | 2020-12-29 | 湖北芯擎科技有限公司 | Method, device, system and storage medium for communication among multiple processors |
| CN113110950A (en) * | 2021-05-18 | 2021-07-13 | 南方电网科学研究院有限责任公司 | Processor, communication method, storage medium, and computing device |
| CN115599459A (en) * | 2022-12-13 | 2023-01-13 | 成都启英泰伦科技有限公司（Cn） | Cross-power-domain multiprocessor operation device and communication method thereof |
| US11921563B1 (en) | 2022-12-13 | 2024-03-05 | Chipintelli Technology Co., Ltd | Operating device of cross-power domain multiprocessor and communication method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103324599A (en) | Inter-processor communication method and system on chip | |
| CN110647480B (en) | Data processing method, remote direct access network card and equipment | |
| US8478926B1 (en) | Co-processing acceleration method, apparatus, and system | |
| US8209690B2 (en) | System and method for thread handling in multithreaded parallel computing of nested threads | |
| CN103793342B (en) | Multichannel direct memory access (DMA) controller | |
| US11599491B2 (en) | System on chip having semaphore function and method for implementing semaphore function | |
| CN105630731A (en) | Network card data processing method and device in multi-CPU (Central Processing Unit) environment | |
| CN106095604A (en) | The communication method between cores of a kind of polycaryon processor and device | |
| JP2007079789A (en) | Computer system and event processing method | |
| CN104102542A (en) | Network data packet processing method and device | |
| CN101877666B (en) | Method and device for receiving multi-application program message based on zero copy mode | |
| JP4368795B2 (en) | Improved interprocessor communication system for communicating between processors. | |
| CN112131176B (en) | FPGA (field programmable Gate array) quick local reconstruction method based on PCIE (peripheral component interface express) | |
| CN102291298B (en) | Efficient computer network communication method oriented to long message | |
| CN110046050B (en) | Device and method for inter-core data transmission | |
| JP2006309512A (en) | Multiprocessor system, and message transmission method for multiprocessor system | |
| CN111290983A (en) | USB transmission equipment and transmission method | |
| US7216186B2 (en) | Controlling data flow between processor systems | |
| WO2013148439A1 (en) | Hardware managed allocation and deallocation evaluation circuit | |
| US8909823B2 (en) | Data processing device, chain and method, and corresponding recording medium for dividing a main buffer memory into used space and free space | |
| CN101634956B (en) | Dispatching method and dispatcher of information of polynuclear processor | |
| CN115934385A (en) | Method, system, equipment and storage medium for communication among multiple cores | |
| CN108241770B (en) | Message response distributed simulation method based on reflective memory network | |
| JP2007102447A (en) | Arithmetic processor | |
| WO2021179218A1 (en) | Direct memory access unit, processor, device, processing method, and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130925 |