CN103296067A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN103296067A CN103296067A CN2012100434694A CN201210043469A CN103296067A CN 103296067 A CN103296067 A CN 103296067A CN 2012100434694 A CN2012100434694 A CN 2012100434694A CN 201210043469 A CN201210043469 A CN 201210043469A CN 103296067 A CN103296067 A CN 103296067A
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Abstract
The invention discloses a semiconductor structure and a forming method of the semiconductor structure. The semiconductor structure comprises a first doped region, a second doped region, a doped stripe and a top doped region. The first doped region has a first conductivity type. The second doped region is formed in the first doped region and has a second conductivity type relative to the first conductivity type. The doped stripe is formed in the first doped region and has the second conductivity type. The top doped region is formed in the doped stripe and has the first conductivity type. The top doped region is provided with a first side edge and a second side edge, wherein the first side edge is opposite to the second side edge. The doped stripe extends beyond the first side edge or the second side edge.
Description
Technical field
The invention relates to semiconductor structure and forming method thereof, particularly relevant for high voltage semiconductor device and forming method thereof.
Background technology
Between nearly decades, the semiconductor industry continues to dwindle the size of semiconductor structure, and improves the unit cost of speed, usefulness, density and integrated circuit simultaneously.In the general withstand voltage degree methods of lifting device, for instance, be to utilize the identical mask field plate zone that depth bounds is different in that drift region formation surface profile is identical.Yet this technology is still limited to the lifting degree of the device reduction of impedance and firing current.
Summary of the invention
The invention relates to semiconductor structure and forming method thereof, the operation usefulness of semiconductor structure is good.
According to an aspect of the present invention, the invention provides a kind of semiconductor structure, this semiconductor structure comprises first doped region, second doped region, doping striped and top doped region; First doped region has first conductivity type; Second doped region is formed in first doped region, and has second conductivity type with respect to first conductivity type; The doping stripe-shaped is formed in first doped region, and has second conductivity type; The top doped region is formed in the doping striped, and has first conductivity type; The top doped region has relative first side and second side; The doping striped is to extend beyond first side or second side.
According to a further aspect of the invention, the invention provides a kind of formation method of semiconductor structure, this method may further comprise the steps: form second doped region in first doped region; First doped region has first conductivity type; Second doped region has second conductivity type with respect to first conductivity type; Form the doping striped in first doped region; The doping striped has second conductivity type; Form the top doped region in the doping striped; The top doped region has first conductivity type; The top doped region has relative first side and second side; The doping striped is to extend beyond first side or second side.
Preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 2 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 3 illustrates the top view according to the semiconductor structure of an embodiment.
Fig. 4 A illustrates the profile according to the semiconductor structure of an embodiment.
Fig. 4 B illustrates the profile according to the semiconductor structure of an embodiment.
Fig. 5 A to Fig. 8 B illustrates the manufacture method according to the semiconductor structure of an embodiment.
Fig. 9 A illustrates the profile according to the semiconductor structure of an embodiment.
Fig. 9 B illustrates the profile according to the semiconductor structure of an embodiment.
Figure 10 illustrates the top view according to the semiconductor structure of an embodiment.
Figure 11 illustrates the profile according to the semiconductor structure of an embodiment.
Figure 12 illustrates the top view according to the semiconductor structure of an embodiment.
Figure 13 illustrates the profile according to the semiconductor structure of an embodiment.
Figure 14 illustrates the I-V curve of semiconductor structure.
Figure 15 illustrates the I-V curve of semiconductor structure.
[main element symbol description]
102: the first doped regions
104: substrate
106: the second doped regions
108: the three doped regions
110,210: the first doped electrode districts
112,212: the second doped electrode districts
114,214: the three doped electrode districts
116,216: the four doped electrode districts
118,318,418: the doping striped
120,320,420: the top doped region
122,422: the first side
124,324,424: the second side
126,326,426: the three sides
128,328,428: the four sides
130: insulation system
132,232: grid structure
134: dielectric layer
136,138,140,142,236,244: conductive layer
Embodiment
First embodiment
Fig. 1 and Fig. 2 illustrate the top view according to the semiconductor structure of first embodiment.The enlarged drawing of the part that the semiconductor structure that Fig. 3 illustrates Fig. 1 and Fig. 2 surrounds with dotted line.Fig. 3 shows doping striped 118, top doped region 120, the first doped electrode district 110, the second doped electrode district 112, the 3rd doped electrode district 114 and the 4th doped electrode district 116 of semiconductor structure.Fig. 1 is the top doped region 120 that omits among Fig. 3.Fig. 2 is the doping striped 118 that omits among Fig. 3.Fig. 4 A illustrates the semiconductor structure of Fig. 3 along the profile of AB line segment.Fig. 4 B illustrates the semiconductor structure of Fig. 3 along the profile of CD line segment.
Please refer to Fig. 4 A and Fig. 4 B, first doped region 102 is formed in the substrate 104.Second doped region 106 is formed in first doped region 102.The 3rd doped region 108 is formed in the substrate 104.The first doped electrode district 110 is formed in first doped region 102.The second doped electrode district 112 and the 3rd doped electrode district 114 are formed in second doped region 106.The 4th doped electrode district 116 is formed in the 3rd doped region 108.Doping striped 118 is formed in first doped region 102.Please refer to Fig. 4 A, top doped region 120 is formed in the doping striped 118.
Please refer to Fig. 3 and Fig. 4 A, top doped region 120 has relative first side 122 and second side 124.Doping striped 118 has the 3rd relative side 126 and four side 128.In this embodiment, doping striped 118 is the first sides 122 that extend beyond top doped region 120.In other words, the first side 122 of top doped region 120 is between the 3rd side 126 and four side 128 of doping striped 118.Please refer to Fig. 4 A and Fig. 4 B, doping striped 118 is separated from each other by first doped region 102.
Please refer to Fig. 4 A and Fig. 4 B, insulation system 130 is positioned on the top doped region 120.Grid structure 132 is on second doped region 106 between first doped region 102 and the second doped electrode district 112.Semiconductor structure comprises dielectric layer 134, be electrically connected to the conductive layer 136 in the first doped electrode district 110, be electrically connected to grid structure 132 conductive layer 138, be electrically connected to the second doped electrode district 112 and the 3rd doped electrode district 114 conductive layer 140, be electrically connected to the conductive layer 142 in the 4th doped electrode district 116.
In embodiment, first doped region 102 has for example N conductivity type of first conductivity type with top doped region 120.Second doped region 106, the 3rd doped region 108, the 3rd doped electrode district 114, the 4th doped electrode district 116 and doping striped 118 have with respect to second conductivity type of first conductivity type P conductivity type for example.
In an embodiment, semiconductor structure is metal-oxide semiconductor (MOS) (MOS) device.In this example, the first doped electrode district 110 and the second doped electrode district 112 have for example N conductivity type of first conductivity type.The first doped electrode district 110 is as the source electrode of mos device and drains one of them.The second doped electrode district 112 be as the source electrode of mos device and drain electrode wherein another.For instance, the first doped electrode district 110 is used as drain electrode, and the second doped electrode district 112 is as source electrode.
In another embodiment, semiconductor structure is insulated gate bipolar transistor (IGBT) device.In this example, the first doped electrode district 110 has for example P conductivity type of second conductivity type.The second doped electrode district 112 has for example N conductivity type of first conductivity type.The first doped electrode district 110 is as the source electrode of IGBT device and drains one of them.The second doped electrode district 112 be as the source electrode of IGBT device and drain electrode wherein another.For instance, the first doped electrode district 110 is as drain electrode, and the second doped electrode district 112 is as source electrode.
Fig. 4 A to Fig. 8 B illustrates the manufacture method according to the semiconductor structure of an embodiment.The figure that is labeled as A illustrates in the semiconductor structure, and the top doped region is positioned at the profile of the part on the doping striped, for example the profile of the AB line segment of Fig. 3.The figure that is labeled as B illustrates in the semiconductor structure, and the top doped region extends the profile of the part on first doped region between the doping striped, for example profile of the CD line segment of Fig. 3.
Please refer to Fig. 5 A and Fig. 5 B, substrate 104 for example piece silicon or silicon-on-insulator (SOI) are provided.Form first doped region 102 in substrate 104.Form second doped region 106 in first doped region 102.Form the 3rd doped region 108 in substrate 104.In an embodiment, for example second doped region 106 and the 3rd doped region 108 of P conductivity type are to utilize same mask to form simultaneously all to have second conductivity type.Please refer to Fig. 5 A, form doping striped 118 in first doped region 102.
Please refer to Fig. 6 A and Fig. 6 B, form top doped region 120 in doping striped 118 and first doped region 102.In embodiment, be to be different from order to form the mask of doping striped 118 in order to the mask that forms top doped region 120.
Please refer to Fig. 7 A and Fig. 7 B, form insulation system 130 on top doped region 120.Insulation system 130 is not limited to the field oxide shown in Fig. 7 A and Fig. 7 B, also can comprise shallow trench isolation or other suitable dielectric structures.
Please refer to Fig. 8 A and Fig. 8 B, can form grid structure 132 on first doped region 102 and second doped region 106, and extend on the insulation system 130.Grid structure 132 can comprise gate dielectric layer, gate electrode layer and clearance wall.Gate electrode layer is formed on the gate dielectric layer.Clearance wall is formed on the opposing sidewalls of gate dielectric layer and gate electrode layer.In an embodiment, before forming gate dielectric layer, be to form sacrifical oxide (SAC oxide) on the surface of substrate 104, remove sacrifical oxide then, form the second best in quality gate dielectric layer to get help.Gate electrode layer can comprise polysilicon and the metal silicide tungsten silicide for example that is formed on the polysilicon.Clearance wall can comprise for example tetraethoxysilane (Tetraethoxy silane of silicon dioxide; TEOS).
Please refer to Fig. 4 A and Fig. 4 B, form the first doped electrode district 110 in first doped region 102.Form the second doped electrode district 112 in second doped region 106.Form the 3rd doped electrode district 114 in second doped region 106.Form the 4th doped electrode district 116 in the 3rd doped region 108.In embodiment, the first doped electrode district 110, the second doped electrode district 112, the 3rd doped electrode district 114 and the 4th doped electrode district 116 are heavily doped.
Please refer to Fig. 4 A and Fig. 4 B, then, form dielectric layer 134 on substrate 104.Utilize electric conducting material to fill patterning conductive material behind the opening of dielectric layer 134, to form conductive layer 136, conductive layer 138, conductive layer 140 and conductive layer 142.Conductive layer 136, conductive layer 138, conductive layer 140 comprise metal for example tungsten, copper, aluminium etc. with conductive layer 142.
Second embodiment
Fig. 9 A and Fig. 9 B illustrate the profile of the semiconductor structure of second embodiment.For instance, Fig. 9 A is that the semiconductor structure of Fig. 3 is along the profile of AB line segment.Fig. 9 B is that the semiconductor structure of Fig. 3 is along the profile of CD line segment.The difference of the semiconductor structure that the semiconductor structure that Fig. 9 A and Fig. 9 B illustrate and Fig. 4 A and Fig. 4 B illustrate is, semiconductor structure comprises the conductive layer 236 that is electrically connected to the first doped electrode district 210, and is electrically connected to the conductive layer 244 in grid structure 232, the second doped electrode district 212, the 3rd doped electrode district 214 and the 4th doped electrode district 216.In addition, in an embodiment, semiconductor structure is diode (diode) device.In this example, the first doped electrode district 210 and the second doped electrode district 212 have for example N conductivity type of first conductivity type.The first doped electrode district 210 be electrically connected to anode and negative electrode one of them.The second doped electrode district 212 be electrically connected to anode and negative electrode wherein another.
The 3rd embodiment
Figure 10 illustrates the top view of the semiconductor structure of the 3rd embodiment.Figure 11 illustrates the semiconductor structure of Figure 10 along the profile of EF line segment.The difference of the semiconductor structure that the semiconductor structure that Figure 10 and Figure 11 illustrate and Fig. 3 and Fig. 4 A illustrate is that doping striped 318 is the second sides 324 that extend beyond top doped region 320.In other words, the second side 324 of top doped region 320 is between the 3rd side 326 and four side 328 of doping striped 318.
The 4th embodiment
Figure 12 illustrates the top view of the semiconductor structure of the 4th embodiment.Figure 13 illustrates the semiconductor structure of Figure 12 along the profile of GH line segment.The difference of the semiconductor structure that the semiconductor structure that Figure 12 and Figure 13 illustrate and Fig. 3 and Fig. 4 A illustrate is, doping striped 418 are first sides 422 of extending beyond top doped region 420 with second side 424 both.In other words, the first side 422 of top doped region 420 and second side 424 are all between the 3rd side 426 and four side 428 of doping striped 418.
In embodiment, semiconductor structure has the doping striped that extends beyond the top doped region, therefore can improve the maximum of top doped region and mix, and keep vague and general situation fully, the on-resistance of device under identical high-breakdown-voltage be can reduce, firing current and usefulness promoted.In addition, semiconductor structure can be applicable to high pressure, superhigh pressure (for example device of 300V～1000V), for example MOS, IGBT and diode.Figure 14 and Figure 15 are the I-V curve of semiconductor structure, it shows compared to general semiconductor structure (comparative example), it is about 17% that the on-resistance of semiconductor structure among the embodiment (superhigh pressure Laterally Diffused Metal Oxide Semiconductor (LDMOS)) drain electrode end can reduce, current boost about 20.5%.In addition, the puncture voltage of semiconductor structure is to maintain 700V above (740V) among the embodiment.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.
Claims (10)
1. semiconductor structure comprises:
One first doped region has one first conductivity type;
One second doped region is formed in this first doped region, and has one second conductivity type with respect to this first conductivity type;
One doping striped is formed in this first doped region, and has this second conductivity type; And
One top doped region is formed in this doping striped, and has this first conductivity type, and wherein this top doped region has a relative first side and a second side, and this doping striped is to extend beyond this first side or this second side.
2. semiconductor structure according to claim 1 wherein should have relative one the 3rd side and a four side by the doping striped, and this first side of this top doped region or this second side are between the 3rd side and this four side of this doping striped.
3. semiconductor structure according to claim 1, wherein a plurality of should the doping striped be separated from each other by this first doped region.
4. semiconductor structure according to claim 1, wherein this top doped region is formed in this first doped region.
5. semiconductor structure according to claim 1 should the doping striped be to extend beyond this first side and this second side wherein.
6. semiconductor structure according to claim 1 more comprises:
One first doped electrode district is formed in this first doped region; And
One second doped electrode district is formed in this second doped region.
7. semiconductor structure according to claim 6, wherein this first doped electrode district and this second doped electrode district have this first conductivity type.
8. semiconductor structure according to claim 6 more comprises a grid structure, on this second doped region between this first doped region and this second doped electrode district.
9. semiconductor structure according to claim 6, wherein this first doped electrode district has this second conductivity type, and this second doped electrode district has this first conductivity type.
10. the formation method of a semiconductor structure comprises:
Form one second doped region in one first doped region, wherein this first doped region has one first conductivity type, and this second doped region has one second conductivity type with respect to this first conductivity type;
Form a doping striped in this first doped region, wherein should have this second conductivity type by the doping striped; And
Form a top doped region in this doping striped, wherein this top doped region has this first conductivity type, and this top doped region has a relative first side and a second side, and this doping striped is to extend beyond this first side or this second side.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105702713A (en) * | 2014-11-28 | 2016-06-22 | 旺宏电子股份有限公司 | Semiconductor structure |
Citations (3)
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| US20060145249A1 (en) * | 2004-12-30 | 2006-07-06 | Dongbuanam Semiconductor Inc. | LDMOS transistor |
| US20100140700A1 (en) * | 2008-12-04 | 2010-06-10 | Sang-Yong Lee | Semiconductor device and method for manufacturing the same |
| CN102110712A (en) * | 2009-12-23 | 2011-06-29 | 旺宏电子股份有限公司 | Lateral power metal oxide semiconductor field effect transistor structure and manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060145249A1 (en) * | 2004-12-30 | 2006-07-06 | Dongbuanam Semiconductor Inc. | LDMOS transistor |
| US20100140700A1 (en) * | 2008-12-04 | 2010-06-10 | Sang-Yong Lee | Semiconductor device and method for manufacturing the same |
| CN102110712A (en) * | 2009-12-23 | 2011-06-29 | 旺宏电子股份有限公司 | Lateral power metal oxide semiconductor field effect transistor structure and manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105702713A (en) * | 2014-11-28 | 2016-06-22 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN105702713B (en) * | 2014-11-28 | 2018-11-16 | 旺宏电子股份有限公司 | Semiconductor structure |
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