CN103278788A - Hall plate simulation model - Google Patents
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- CN103278788A CN103278788A CN2013101483796A CN201310148379A CN103278788A CN 103278788 A CN103278788 A CN 103278788A CN 2013101483796 A CN2013101483796 A CN 2013101483796A CN 201310148379 A CN201310148379 A CN 201310148379A CN 103278788 A CN103278788 A CN 103278788A
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- 238000004088 simulation Methods 0.000 title claims abstract description 15
- 238000012360 testing method Methods 0.000 claims description 7
- 230000035945 sensitivity Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000005355 Hall effect Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000036962 time dependent Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
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Abstract
The application discloses a hall plate simulation model, comprising four hall plate resistors, four hall voltage sources used for simulating hall voltage and four offset voltage sources used for simulating offset voltage; the four hall plate resistors are sequentially connected in an end-to-end manner to constitute a resistor bridge, and each junction of the resistor bridge is connected with one hall voltage source and one offset voltage source in series; at any moment, the voltage of an offset voltage source and the voltage of a hall voltage source, which are connected in series on only two non-adjacent junctions, are 0.5*VOS and 0.5 SIV (MF) respectively, wherein I represents current for generating hall effect, and V(MF) represents an equivalent voltage signal corresponding to a magnetic field signal B required by the hall effect. According to the application, offset voltage sources are respectively arranged at the two output ends, the total output voltage is the offset voltage VOS of the simulated hall plate, the simulation on the offset voltage of the hall plate is realized, the offset characteristic of the hall plate is further obtained, and the existing technical problems are solved.
Description
Technical field
The application relates to simulation technical field, relates in particular to a kind of Hall disc realistic model.
Background technology
When electric current passes through conductor perpendicular to external magnetic field, electric potential difference can appear between two end faces perpendicular to magnetic field and direction of current of conductor, and this phenomenon is called Hall effect, and this electric potential difference is called Hall voltage.Utilize the principle of Hall effect can measure and perception magnetic field, realize that wherein the device of Hall effect is called Hall disc (or Hall element).The terminal that Hall disc all has two pairs of diagonal angles to arrange, as shown in Figure 1, the first terminal T and the second terminal B, the 3rd terminal L and the 4th terminal R form the diagonal angle terminal respectively.During application, between any a pair of diagonal angle terminal (as T and B), feed suitable electric current, can between another is to terminal (L and R), produce Hall voltage V
HBecause the technology restriction, existing Hall disc also can produce bigger offset voltage when producing Hall voltage.
In the circuit design process, for ease of by software circuit being studied debugging, need the corresponding circuit simulation model of design to simulate the electrology characteristic of Hall disc usually; Yet the realistic model of existing Hall disc has generally been ignored the offset voltage of Hall disc, can't carry out emulation to its characteristic of lacking of proper care.
Summary of the invention
In view of this, the application's purpose is to provide a kind of Hall disc realistic model, to solve the problem that existing Hall disc emulation technology is ignored offset voltage, can't be carried out emulation to the imbalance characteristic of Hall disc.
For achieving the above object, the application provides following technical scheme:
A kind of Hall disc realistic model comprises four Hall disc resistance, four Hall voltage source and four offset voltage sources that are used for the simulation offset voltage that are used for analog hall voltage;
Described four Hall disc resistance are end to end formation resistance bridge successively, is connected in series with a described Hall voltage source and a described offset voltage source on each contact of described resistance bridge;
In arbitrary moment, the voltage that has and only have the offset voltage source that is connected in series on two non-conterminous contacts is 0.5*V
OS, the Hall voltage source voltage be 0.5SIV (MF), the offset voltage source that is connected in series on two other contact and the voltage in Hall voltage source are zero; Wherein, V
OSOffset voltage for Hall disc, S is the current sensitivity of Hall disc, I flows through the electric current that described offset voltage source voltage is two contacts of zero, V (MF) is the equivalent voltage signal, and the size of described V (MF) is determined according to the default corresponding relation of the size that produces the required field signal B of described Hall voltage and described equivalent voltage signal and field signal.
Preferably, described equivalent voltage signal V (MF) is the sinusoidal signal with described field signal B same frequency.
Preferably, the corresponding relation of described equivalent voltage signal V (MF) and field signal B is the corresponding 1mT of 1mV.
Preferably, behind each contact of described resistance bridge and Hall voltage source and the offset voltage subject string connection, also connect with direct earth capacitance.
Preferably, described Hall voltage source is current-controlled voltage source.
Preferably, described offset voltage obtains by Hall disc being carried out the flow test.
From above-mentioned technical scheme as can be seen, the application is by arranging the offset voltage source respectively at two output terminals, and to make its total output voltage be the offset voltage of the Hall disc that simulated, and together export with Hall voltage, simulation, emulation to the Hall disc offset voltage have been realized, and then can handle the imbalance characteristic that obtains Hall disc by corresponding data, solved the prior art problem.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiment of the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is Hall disc structure and principle of work synoptic diagram;
The structural representation of the Hall disc realistic model that Fig. 2 provides for the embodiment of the present application;
The Hall disc realistic model test philosophy figure that Fig. 3 provides for the embodiment of the present application;
Fig. 4 exports control principle figure for the Hall voltage of the Hall disc realistic model that the embodiment of the present application provides;
The Hall disc realistic model simulation result synoptic diagram that Fig. 5 provides for the embodiment of the present application.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the application's protection.
The embodiment of the present application discloses a kind of Hall disc realistic model, to solve the problem that prior art can't be carried out emulation to the imbalance characteristic of Hall disc.
With reference to Fig. 2, a kind of Hall disc realistic model that the embodiment of the present application one provides comprises 4 Hall disc resistance, 4 offset voltage source V that resistance is incomplete same
1With 4 Hall voltage source V
2Wherein, offset voltage source V
1The offset voltage that produces when being used for simulation Hall disc generation Hall effect, Hall voltage source V
2The Hall voltage that produces when being used for simulation Hall disc generation Hall effect; 4 Hall disc resistance comprise the first Hall disc resistance R
1, the second Hall disc resistance R
2, the 3rd Hall disc resistance R
3With the 4th Hall disc resistance R
4, four end to end formation resistance bridges successively are connected in series with an offset voltage source V on each contact
1With a Hall voltage source V
2General, the resistance that 4 Hall resistances can be set is identical, and for example resistance is R, i.e. R
1=R
2=R
3=R
4=R.Two offset voltage source V that are connected in series on non-conterminous two contacts
1With two Hall voltage source V
2Direction all identical.Wherein, Hall voltage source V
2Be current-controlled voltage source.
Concrete, the first contact ti of 4 Hall resistances and the first offset voltage source V
11Negative pole t i2 connect V
11Positive pole and the first Hall voltage source V
21Negative pole connect (contact is ts), V
21Positive pole as the first terminal T of this Hall disc realistic model; The second contact ri and the second offset voltage source V
12Negative pole ri2 connect V
12Positive pole and the second Hall voltage source V
22Negative pole connect (contact is rs), V
22Positive pole as the second terminal R of this Hall disc realistic model; The 3rd contact bi and the 3rd offset voltage source V
13Anodal bi2 connect V
13Negative pole and the 3rd Hall voltage source V
23Positive pole connect (contact is bs), V
23Negative pole as the 3rd terminal B of this Hall disc realistic model; The 4th contact li and the 4th offset voltage source V
14Anodal li2 connect V
14Negative pole and the 4th Hall voltage source V
24Positive pole connect (contact is ls), V
24Negative pole as the 4th terminal L of this Hall disc realistic model.
In the simulation process, have and only have two non-conterminous terminals as the output terminal of this Hall disc realistic model, two other terminal is as input end, and the magnitude of voltage of each voltage source is set.For example, when the first terminal T and the 3rd terminal B are input end, the second terminal R and the 4th terminal L when being output terminal, the first offset voltage source V
11, the 3rd offset voltage source V
13, the first Hall voltage source V
21With the 3rd Hall voltage source V
23Voltage all to be set to 0(be V
11=V
13=0, V
21=V
23=0), the second offset voltage source V
12With the 4th offset voltage source V
14All be set to 0.5*V
OS, the second Hall voltage source V
22With the 4th Hall voltage source V
24Voltage all to be set to 0.5SIV (MF) (be V
12=V
14=0.5*V
OS, V
22=V
24=0.5SIV (MF)).Wherein, V
OSOffset voltage for the Hall disc that simulated, S is the current sensitivity of this Hall disc, I is that to flow through offset voltage source voltage be zero the first terminal T and the electric current of the 3rd terminal B, V (MF) is the equivalent voltage signal, its size is determined according to the default corresponding relation of the size that produces the required field signal B of described Hall voltage and described equivalent voltage signal and field signal, namely passes through the required field signal B of generation Hall effect of a certain size the corresponding size of equivalent voltage signal imitation.
Because the mode of exporting by two non-conterminous two terminals is difference output, so be 0.5*V when each lead-out terminal all is connected with size
OSOffset voltage the time, total offset voltage of output is the actual offset voltage of Hall disc just.
By said structure as can be known, the embodiment of the present application is by arranging the offset voltage source respectively at two output terminals, and to make its total output voltage be the offset voltage of the Hall disc that simulated, and together export with Hall voltage, simulation, emulation to the Hall disc offset voltage have been realized, and then can handle the imbalance characteristic that obtains Hall disc by corresponding data, solved the prior art problem.
Concrete, above-mentioned offset voltage V
OSConcrete big I obtain by the flow test, perhaps rule of thumb estimation is generally several millivolts～tens millivolts.
Further, above-mentioned Hall voltage source is current-controlled voltage source; Equivalent voltage signal V (MF) is sinusoidal signal, and the frequency of V (MF) is identical with field signal B, and the amplitude of V (MF) and the corresponding relation of magnetic field intensity are decided according to the actual requirements.For example this corresponding relation can be for the field signal of the corresponding 10mT of equivalent voltage signal of the field signal of the corresponding 1mT of the equivalent voltage signal of 1mV, 1mV etc.
Below with reference to the schematic diagram that emulation testing circuit theory diagrams shown in Figure 3 (the Hall disc realistic model is reduced to rhombus hall among the figure) and Hall voltage output shown in Figure 4 are controlled, the corresponding method of carrying out emulation testing and principle with above-mentioned Hall disc realistic model is introduced:
Suppose the Hall disc sensitivity S=1000V/ (AT), the equivalent resistance R that simulated
H=10K Ω, electric current by this Hall disc when producing Hall effect is that the I size is to be flowed to B(or flowed to R by L by T for 0.2mA, direction), the intensity that puts on the field signal B of this Hall disc is that 1T, frequency are that 1KHz, direction are that vertical paper is downward, the offset voltage V of generation
OS=20mV, then in theory, when Hall effect takes place in Hall realistic model under these conditions, the Hall voltage V of generation
H=SIB=1000V/ (AT) * 0.2mA*1T=200mV, direction is the positive R of L negative (or the positive B of T is negative), produces the offset voltage of 20mV simultaneously.During emulation testing, it is that 1V, frequency are the sinusoidal signal of 1KHz that equivalent voltage signal V (MF) adopts amplitude, shown in Fig. 5 curve L0, to simulate above-mentioned field signal B; By R
H=(R
1+ R
4) // (R
2+ R
3) and R
1=R
2=R
3=R
4As can be known, need the resistance of 4 Hall resistances of setting to be R
HThe corresponding supply voltage U=I*R that sets
H=2V, the switching by square-wave signal realization equivalent switch HAL0 and HAL90 makes above-mentioned Hall disc realistic model hall alternately be in following two states:
The first state Closing Switch HAL0, cut-off switch HAL90, the Hall voltage source voltage that the voltage in the Hall voltage source of the first terminal T and the 3rd terminal B and offset voltage source all is set to 0, the four terminal L and the second terminal R is set to 0.5SIV (MF), offset voltage source voltage is set to 0.5*V
OS, be equivalent between the first terminal T and the 3rd terminal B, apply supply voltage U, output Hall voltage VP(is that electric current I flows to B by T between the 4th terminal L and the second terminal R, voltage VP direction be the L end for just, the R end is for bearing);
The second state Closing Switch HAL90, cut-off switch HAL0, the Hall voltage source of the 4th terminal L and the second terminal R and the voltage in offset voltage source all are set to 0, and the Hall voltage source voltage of the first terminal T and the 3rd terminal B is set to 0.5SIV (MF), offset voltage source voltage is set to 0.5*V
OS, be equivalent between the 4th terminal L and the second terminal R, apply supply voltage U, output voltage V N(is that electric current I flows to R by L between the 3rd terminal B and the first terminal T, voltage VN direction be B end for just, the T end is for bearing).
The time dependent oscillogram of voltage VN that emulation obtains shown in Fig. 5 dotted line L1, the time dependent oscillogram of voltage VP shown in Fig. 5 solid line L2 shown in.As shown in Figure 5, the Hall voltage of the actual generation of Hall disc realistic model that the application provides size is 200mV, and has produced the offset voltage of 20mV, and is identical with theoretical value.
By above-described embodiment as can be known, the application not only by the offset voltage source to offset voltage simulate, emulation, also utilize the field signal B in voltage signal V (MF) the simulation Hall effect, the process equivalence that will produce Hall voltage under the effect of electric current I and magnetic field B is the voltage identical with above-mentioned Hall voltage size is exported in the Hall voltage source under control of current I process, simulation, emulation to Hall voltage, Hall effect have been realized, therefore, the embodiment of the present application has more fully been simulated electrology characteristics such as Hall disc voltage characteristic, imbalance characteristic.
Because in the above embodiments of the present application, have only output terminal to have electric current to flow through, the input end electric current is 0, so can flow through the electric current of certain terminal (T, B, L or R) and 0 magnitude relationship by judgement, determines that the voltage in the offset voltage source of this terminal correspondence answers zero setting still to be set to 0.5*V
OSAbove-mentioned electric current is judged and the voltage setting up procedure can be realized by the VerilogA language, and concrete statement is (It, Ib, Il, Ir represent the electric current of terminal respectively):
if(It>0)begin
V(rs,ri2)<+0.5*Vos;
V(li2,ls)<+0.5*Vos;
V(ts,ti2)<+0;
V(bs,bi2)<+0;
end
else?if(Il>0)begin
V(ti2,ts)<+0.5*Vos;
V(bs,bi2)<+0.5*Vos;
V(ls,li2)<+0;
V(rs,ri2)<+0;
end
else?if(Ib>0)begin
V(ls,li2)<+0.5*Vos;
V(ri2,rs)<+0.5*Vos;
V(ts,ti2)<+0;
V(bs,bi2)<+0;
end
else?if(Ir>0)begin
V(ts,ti2)<+0.5*Vos;
V(bi2,bs)<+0.5*Vos;
V(rs,ri2)<+0;
V(ls,li2)<+0;
end
else?begin
V(ts,ti2)<+0;
V(bi2,bs)<+0;
V(rs,ri2)<+0;
V(ls,li2)<+0;
end。
Similarly, the setting of 4 Hall voltage source voltages also can realize by the VerilogA language.
In addition, the first terminal T, the second terminal R, the 3rd terminal B and the 4th terminal L are equipped with direct earth capacitance C in above-described embodiment, can be used for simulating the ground capacitance of four terminals of Hall disc.The size of this direct earth capacitance C is relevant with level of Hall disc size, use etc., generally between tens fF～hundreds of fF.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, described program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the application.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation of the spirit or scope that do not break away from the application in other embodiments herein.Therefore, the application will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1. a Hall disc realistic model is characterized in that, comprises four Hall disc resistance, four Hall voltage source and four offset voltage sources that are used for the simulation offset voltage that are used for analog hall voltage;
Described four Hall disc resistance are end to end formation resistance bridge successively, is connected in series with a described Hall voltage source and a described offset voltage source on each contact of described resistance bridge;
In arbitrary moment, the voltage that has and only have the offset voltage source that is connected in series on two non-conterminous contacts is 0.5*V
OS, the Hall voltage source voltage be 0.5SIV (MF), the offset voltage source that is connected in series on two other contact and the voltage in Hall voltage source are zero; Wherein, V
OSOffset voltage for Hall disc, S is the current sensitivity of Hall disc, I flows through the electric current that described offset voltage source voltage is two contacts of zero, V (MF) is the equivalent voltage signal, and the size of described V (MF) is determined according to the default corresponding relation of the size that produces the required field signal B of described Hall voltage and described equivalent voltage signal and field signal.
2. Hall disc realistic model according to claim 1 is characterized in that, described equivalent voltage signal V (MF) is the sinusoidal signal with described field signal B same frequency.
3. Hall disc realistic model according to claim 2 is characterized in that, the corresponding relation of described equivalent voltage signal V (MF) and field signal B is the corresponding 1mT of 1mV.
4. according to each described Hall disc realistic model of claim 1～3, it is characterized in that, behind each contact of described resistance bridge and Hall voltage source and the offset voltage subject string connection, also connect with direct earth capacitance.
5. according to each described Hall disc realistic model of claim 1～3, it is characterized in that described Hall voltage source is current-controlled voltage source.
6. according to each described Hall disc realistic model of claim 1～3, it is characterized in that described offset voltage obtains by Hall disc being carried out the flow test.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150276892A1 (en) * | 2014-03-27 | 2015-10-01 | Texas Instruments Incorporated | Systems and methods for operating a hall-effect sensor without an applied magnetic field |
| CN111474456A (en) * | 2020-04-14 | 2020-07-31 | 新磊半导体科技（苏州）有限公司 | Hall effect voltage determining method and Hall test system |
| CN112798867A (en) * | 2020-12-28 | 2021-05-14 | 北京东方计量测试研究所 | Base for realizing combined quantum Hall resistance sample |
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| US20030107373A1 (en) * | 2001-06-01 | 2003-06-12 | Koninklijke Philips Electronics N.V. | Sensor for measuring a magnetic field and method of regulating said sensor |
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2013
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| US20030107373A1 (en) * | 2001-06-01 | 2003-06-12 | Koninklijke Philips Electronics N.V. | Sensor for measuring a magnetic field and method of regulating said sensor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150276892A1 (en) * | 2014-03-27 | 2015-10-01 | Texas Instruments Incorporated | Systems and methods for operating a hall-effect sensor without an applied magnetic field |
| US9791521B2 (en) * | 2014-03-27 | 2017-10-17 | Texas Instruments Incorporated | Systems and methods for operating a hall-effect sensor without an applied magnetic field |
| CN111474456A (en) * | 2020-04-14 | 2020-07-31 | 新磊半导体科技（苏州）有限公司 | Hall effect voltage determining method and Hall test system |
| CN112798867A (en) * | 2020-12-28 | 2021-05-14 | 北京东方计量测试研究所 | Base for realizing combined quantum Hall resistance sample |
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| CN103278788B (en) | 2015-09-09 |
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Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |