CN103248218B - Charge pump single-stage circuit and charge pump circuit - Google Patents
Charge pump single-stage circuit and charge pump circuit Download PDFInfo
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- CN103248218B CN103248218B CN201210027290.XA CN201210027290A CN103248218B CN 103248218 B CN103248218 B CN 103248218B CN 201210027290 A CN201210027290 A CN 201210027290A CN 103248218 B CN103248218 B CN 103248218B
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Abstract
The invention discloses a kind of charge pump single-stage circuit and charge pump circuit, overcome existing Dickson charge pump by NMOS threshold voltage affect operating efficiency defect on the low side, in this charge pump single-stage circuit, the first transmission unit comprises the first clock incoming end, accesses the first input end of the first input signal and exports the first the first output outputed signal; Second transmission unit comprises second clock incoming end, accesses the second input of the second input signal and exports the second the second output outputed signal; First and second clock incoming end accesses the wherein phase in two-phase complementary clock signal respectively, first transmission unit is followed accessed clock signal and electric charge is transferred to the first output from first input end, and the second transmission unit is followed accessed clock signal and electric charge is transferred to the second output from the second input.This invention removes the impact of traditional Dickson charge pump by NMOS threshold voltage, significantly improve charge transfer efficiency.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of charge pump single-stage circuit and a kind of charge pump circuit.
Background technology
Fig. 1 is the schematic diagram of existing Dickson charge pump circuit.In the charge pump circuit shown in Fig. 1, comprise x (x is integer) the individual NMOS tube be connected step by step, NMOS tube at different levels is all serially connected with diode-connected (namely grid and drain electrode link together), the wherein drain electrode access input voltage Vdd of first order NMOS tube N1, the drain electrode of second level NMOS tube N2 connects the source electrode of first order NMOS tube N1, the drain electrode of third level NMOS tube N3 connects the source electrode of second level NMOS tube N2, ..., the drain electrode of xth level NMOS tube Nx connects the source electrode of xth-1 grade of NMOS tube Nx-1, and source electrode is voltage output end.The NMOS tube of x-1 level before corresponding, correspondence has access to the pump electric capacity of x-1 level, and wherein the first end of pump electric capacity at different levels accesses the source electrode of the NMOS tube of corresponding progression, and the other end is access first-phase clock signal clka and second-phase clock signal clka ' alternately.The source electrode of xth level (also claiming output stage) NMOS tube Nx connects the first end of output capacitance Cout, the second end ground connection of output capacitance Cout.Wherein, NMOS tube at different levels is all transferring charge pipes, and be cascaded formation charge transfer path; First-phase clock signal clka and second-phase clock signal clka ' is two-phase complementary clock as shown in Figure 2.Under the effect of two-phase complementary clock (first-phase clock signal clka and second-phase clock signal clka '), electric charge can be transferred to output voltage Vout from Vdd by charge pump circuit shown in Fig. 1 step by step, raises the output voltage of charge pump.
Fig. 3 is the schematic diagram of the Dickson charge pump circuit with complementary function.It is formed primarily of two charge transfer path as shown in Figure 1, article two, the drain electrode of the first order NMOS tube of charge transfer path accesses input voltage Vdd after linking together, afterbody (xth level, wherein x is integer) the source electrode of NMOS tube link together after connect the first end of output capacitance Cout, and provide output voltage Vout.
The Dickson charge pump circuit with complementary function shown in Fig. 3 is compared with the Dickson charge pump circuit shown in Fig. 1, the main distinction is that the order that two-phase complementary clock is alternately linked in charge transfer path is different, particularly, that be linked into the first order NMOS tube N1 in the first transmission path is first-phase clock signal clka, and that be linked into the first order NMOS tube N1 ' in the second transmission path is second-phase clock signal clka '.
But, in Dickson charge pump, grid and the drain electrode of NMOS diode link together, during transferring charge, NMOS tube is operated in saturation region, make a source voltage threshold voltage vt h lower than drain voltage all the time, the electric charge of such previous stage fully can not transfer to rear class, reduces charge transfer efficiency, and operating voltage is lower, the impact of threshold voltage vt h is more remarkable.In addition, the progression of NMOS tube is higher, and the voltage on its source electrode is higher, and in the standard CMOS process of P-sub, the Substrate ground of NMOS, then VsB (voltage difference between the source electrode of metal-oxide-semiconductor and substrate) increases, the impact of receptor effect, and threshold voltage vt h increases, that further reduces the voltage gain of Dickson charge pump rear class, and the progression of NMOS tube in charge transfer path is more, the closer to output stage, one pass gain is less.These are not enough above, all reduce the operating efficiency of Dickson charge pump.
Therefore, traditional Dickson charge pump by NMOS threshold voltage to affect operating efficiency on the low side, and its restriction by operating voltage and progression is obvious, needs to be improved.
Summary of the invention
Technical problem to be solved by this invention be overcome existing Dickson charge pump by NMOS threshold voltage affect operating efficiency defect on the low side.
In order to solve the problems of the technologies described above, the invention provides a kind of charge pump single-stage circuit, comprise the first transmission unit and the second transmission unit, wherein:
Described first transmission unit comprises the first clock incoming end, first input end and the first output, and described first input end is for accessing the first input signal, and described first output is for exporting the first output signal;
Described second transmission unit comprises second clock incoming end, the second input and the second output, and described second input is for accessing the second input signal, and described second output is for exporting the second output signal;
Described first clock incoming end and second clock incoming end access the wherein phase in two-phase complementary clock signal respectively, electric charge is transferred to the first output from described first input end for following accessed clock signal by described first transmission unit, and electric charge is transferred to the second output from described second input for following accessed clock signal by described second transmission unit.
Preferably, described first transmission unit comprises the first transmission circuit, comprise the first input control circuit of four control ends and comprise the first output control circuit of four control ends, wherein:
Described first transmission circuit comprises described first clock incoming end, first input end and the first output, also comprises the first input control end and the first output control terminal;
First control end of described first input control circuit connects described first input end, and the second control end connects described first clock incoming end, and the 3rd control end connects described first input control end;
First control end of described first output control circuit connects described first output, and the second control end connects described first clock incoming end, and the 3rd control end connects described first output control terminal;
4th control end of described first input control circuit and the 4th control end of described first output control circuit connect described second transmission unit respectively, turn off for the clock signal of following described first clock incoming end access or open described second transmission unit transmission charge.
Preferably, described first transmission circuit comprises the first transmission NMOS tube Nt1, the first transmission PMOS Pt1 and first transmission electric capacity Ct1, wherein:
The drain electrode of described first transmission NMOS tube Nt1 is described first input end, and grid is described first input control end, and source electrode connects the first end of described first transmission electric capacity Ct1 and the drain electrode of described first transmission PMOS Pt1;
Second end of described first transmission electric capacity Ct1 is described first clock incoming end;
The grid of described first transmission PMOS Pt1 is described first output control terminal, and source electrode and substrate link together, and are described first output.
Preferably, described first input control circuit comprises the first charging NMOS tube Nc1 and the first NMOS tube control capacitance Cn1, wherein:
The drain electrode of described first charging NMOS tube Nc1 is the first control end of described first input control circuit, and grid is the 3rd control end of described first input control circuit, and source electrode is the 4th control end of described first input control circuit;
The first end of described first NMOS tube control capacitance Cn1 connects the source electrode of described first charging NMOS tube Nc1, and the second end is the second control end of described first input control circuit.
Preferably, described first output control circuit comprises the first charging PMOS Pc1 and the first PMOS control capacitance Cp1, wherein:
Source electrode and the substrate of described first charging PMOS Pc1 link together, and be the first control end of described first output control circuit, grid is the 3rd control end of described first output control circuit, drains as the 4th control end of described first output control circuit;
The first end of the first PMOS control capacitance Cp1 connects the drain electrode of described first charging PMOS Pc1, and the second end is the second control end of described first output control circuit.
Preferably, described second transmission unit comprises the second transmission circuit, comprise the second input control circuit of four control ends and comprise the second output control circuit of four control ends, wherein:
Described second transmission circuit comprises described second clock incoming end, the second input and the second output, also comprises the second input control end and the second output control terminal;
First control end of described second input control circuit connects described second input, and the second control end connects described second clock incoming end, and the 3rd control end connects described second input control end;
First control end of described second output control circuit connects described second output, and the second control end connects described second clock incoming end, and the 3rd control end connects described second output control terminal;
4th control end of described second input control circuit and the 4th control end of described second output control circuit connect described first transmission unit respectively, turn off for the clock signal of following the access of described second clock incoming end or open described first transmission unit transmission charge.
Preferably, described second transmission circuit comprises the second transmission NMOS tube Nt1 ', the second transmission PMOS Pt1 ' and second transmission electric capacity Ct1 ', wherein:
The drain electrode of described second transmission NMOS tube Nt1 ' is described second input, and grid is described second input control end, and source electrode connects the first end of described second transmission electric capacity Ct1 ' and the drain electrode of described second transmission PMOS Pt1 ';
Second end of described second transmission electric capacity Ct1 ' is described second clock incoming end;
The grid of described second transmission PMOS Pt1 ' is described second output control terminal, and source electrode and substrate link together, and are described second output.
Preferably, described second input control circuit comprises the second charging NMOS tube Nc1 ' and the second NMOS tube control capacitance Cn1 ', wherein:
The drain electrode of described second charging NMOS tube Nc1 ' is the first control end of described second input control circuit, and grid is the 3rd control end of described second input control circuit, and source electrode is the 4th control end of described second input control circuit;
The first end of described second NMOS tube control capacitance Cn1 ' connects the source electrode of described second charging NMOS tube Nc1 ', and the second end is the second control end of described second input control circuit.
Preferably, described second output control circuit comprises the second charging PMOS Pc1 ' and the second PMOS control capacitance Cp1 ', wherein:
Source electrode and the substrate of described second charging PMOS Pc1 ' link together, for the first control end of described second output control circuit, grid is the 3rd control end of described second output control circuit, drains as the 4th control end of described second output control circuit;
The first end of the second PMOS control capacitance Cp1 ' connects the drain electrode of described second charging PMOS Pc1 ', and the second end is the second control end of described second output control circuit.
Present invention also offers a kind of charge pump circuit, comprise the foregoing single-level circuit of at least two-stage, wherein:
First input end and second input of first order single-level circuit link together, as the input of described charge pump circuit; First output and second output of afterbody single-level circuit link together, as the output of described charge pump circuit, and through output capacitance ground connection;
When the progression x of described charge pump circuit is greater than 2, the first input end of i-th grade of single-level circuit connects the first output of the i-th-1 grade single-level circuit, and the second input connects the second output of the i-th-1 grade single-level circuit; Wherein, i is more than or equal to 2 and is less than or equal to x-1, and xth level single-level circuit is described afterbody single-level circuit;
The clock signal complement of the first transmission unit access of the single-level circuit of adjacent two-stage.
Compared with prior art, embodiments of the invention can ensure that transferring charge pipe is operated in dark linear zone when conducting, cut-off region is operated in when turning off, and electric charge can close to the transmission of 100%, eliminate the impact of traditional Dickson charge pump by NMOS threshold voltage, significantly improve charge transfer efficiency.Embodiments of the invention overcome the obvious defect of restriction ratio that existing Dickson charge pump is subject to operating voltage and progression.Embodiments of the invention are more suitable for work (1.2 volts of V are even lower) at a low input voltages than existing Dickson charge pump.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in specification, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Accompanying drawing is used to provide the further understanding to technical solution of the present invention, and forms a part for specification, together with embodiments of the present invention for explaining technical scheme of the present invention, does not form the restriction to technical solution of the present invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of existing Dickson charge pump circuit.
Fig. 2 is two-phase complementary clock waveform schematic diagram.
Fig. 3 is the schematic diagram of the Dickson charge pump circuit with complementary function.
Fig. 4 is a kind of charge pump single-stage circuit that the embodiment of the present invention provides.
Fig. 5 is the structural representation of a kind of charge pump circuit that the embodiment of the present invention provides.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.
Fig. 4 is a kind of charge pump single-stage circuit that the embodiment of the present invention provides.As shown in Figure 4, the present embodiment charge pump single-stage circuit comprises the first transmission unit 410 and the second transmission unit 420.
First transmission unit 410 comprises the first clock incoming end, first input end and the first output, and first input end is for accessing the first input signal, and the first output is for exporting the first output signal;
Second transmission unit 420 comprises second clock incoming end, the second input and the second output, and the second input is for accessing the second input signal, and the second output is for exporting the second output signal;
First clock incoming end and second clock incoming end access the wherein phase in two-phase complementary clock signal respectively, electric charge is transferred to the first output from first input end for following accessed clock signal by the first transmission unit, and electric charge is transferred to the second output from the second input for following accessed clock signal by the second transmission unit.
In the present embodiment, the first transmission unit 410 comprises the first transmission circuit, comprise the first input control circuit of four control ends and comprise the first output control circuit of four control ends, wherein:
First transmission circuit comprises the first clock incoming end, first input end and the first output, also comprises the first input control end and the first output control terminal;
First control end of the first input control circuit connects first input end, and the second control end connects the first clock incoming end, and the 3rd control end connects the first input control end;
First control end of the first output control circuit connects the first output, and the second control end connects the first clock incoming end, and the 3rd control end connects the first output control terminal;
4th control end of the first input control circuit and the 4th control end of the first output control circuit connect the second transmission unit respectively, for following a two-phase complementary clock signal wherein phase shutoff or unlatching the second transmission unit transmission charge.
In the present embodiment, the drain electrode of the first transmission NMOS tube Nt1 is first input end, and grid is the first input control end, and source electrode connects the first end of the first transmission electric capacity Ct1 and the drain electrode of the first transmission PMOS Pt1; Second end of the first transmission electric capacity Ct1 is the first clock incoming end; The grid of the first transmission PMOS Pt1 is the first output control terminal, and source electrode and substrate link together, and are the first output.
In the present embodiment, the first input control circuit comprises the first charging NMOS tube Nc1 and the first NMOS tube control capacitance Cn1, wherein:
The drain electrode of the first charging NMOS tube Nc1 is the first control end of the first input control circuit, and grid is the 3rd control end of the first input control circuit, and source electrode is the 4th control end of the first input control circuit; The first end of the first NMOS tube control capacitance Cn1 connects the source electrode of the first charging NMOS tube Nc1, and the second end is the second control end of the first input control circuit.
In the present embodiment, the first output control circuit comprises the first charging PMOS Pc1 and the first PMOS control capacitance Cp1, wherein:
Source electrode and the substrate of the first charging PMOS Pc1 link together, and be the first control end of the first output control circuit, grid is the 3rd control end of the first output control circuit, and drain electrode is the 4th control end of the first output control circuit; The first end of the first PMOS control capacitance Cp1 connects the drain electrode of the first charging PMOS Pc1, and the second end is the second control end of the first output control circuit.
In the present embodiment, the second transmission unit 420 comprises the second transmission circuit, comprise the second input control circuit of four control ends and comprise the second output control circuit of four control ends, wherein:
Second transmission circuit comprises second clock incoming end, the second input and the second output, also comprises the second input control end and the second output control terminal;
First control end of the second input control circuit connects the second input, and the second control end connects second clock incoming end, and the 3rd control end connects the second input control end;
First control end of the second output control circuit connects the second output, and the second control end connects second clock incoming end, and the 3rd control end connects the second output control terminal;
4th control end of the second input control circuit and the 4th control end of the second output control circuit connect the first transmission unit respectively, for following the two-phase complementary clock signal wherein shutoff of another phase or unlatching the first transmission unit transmission charge.
In the present embodiment, the second transmission circuit comprises the second transmission NMOS tube Nt1 ', the second transmission PMOS Pt1 ' and second transmission electric capacity Ct1 ', wherein:
The drain electrode of the second transmission NMOS tube Nt1 ' is the second input, and grid is the second input control end, and source electrode connects the first end of the second transmission electric capacity Ct1 ' and the drain electrode of the second transmission PMOS Pt1 '; Second end of the second transmission electric capacity Ct1 ' is second clock incoming end; The grid of the second transmission PMOS Pt1 ' is the second output control terminal, and source electrode and substrate link together, and are the second output.
In the present embodiment, the second input control circuit comprises the second charging NMOS tube Nc1 ' and the second NMOS tube control capacitance Cn1 ', wherein:
The drain electrode of the second charging NMOS tube Nc1 ' is the first control end of the second input control circuit, and grid is the 3rd control end of the second input control circuit, and source electrode is the 4th control end of the second input control circuit; The first end of the second NMOS tube control capacitance Cn1 ' connects the source electrode of the second charging NMOS tube Nc1 ', and the second end is the second control end of the second input control circuit.
In the present embodiment, the second output control circuit comprises the second charging PMOS Pc1 ' and the second PMOS control capacitance Cp1 ', wherein:
Source electrode and the substrate of the second charging PMOS Pc1 ' link together, and be the first control end of the second output control circuit, grid is the 3rd control end of the second output control circuit, and drain electrode is the 4th control end of the second output control circuit; The first end of the second PMOS control capacitance Cp1 ' connects the drain electrode of the second charging PMOS Pc1 ', and the second end is the second control end of the second output control circuit.
As shown in Figure 4, in embodiments of the invention, the first transmission unit 410 comprises the first charging NMOS tube Nc1 (N-type metal-oxide-semiconductor), the first transmission NMOS tube Nt1 (N-type metal-oxide-semiconductor), the first charging PMOS Pc1 (P type metal-oxide-semiconductor), the first transmission PMOS Pt1 (P type metal-oxide-semiconductor), the first NMOS tube control capacitance Cn1, the first PMOS control capacitance Cp1 and the first transmission electric capacity Ct1.
In the first transmission unit 410, the drain electrode of the first transmission NMOS tube Nt1 is first input end, access the first input signal Vin, grid connects the grid of the first charging NMOS tube Nc1, and source electrode connects the first end of the first transmission electric capacity Ct1 and the drain electrode of the first transmission PMOS Pt1.The drain electrode of the first charging NMOS tube Nc1 connects the drain electrode of the first transmission NMOS tube Nt1, and also access the first input signal Vin, source electrode connects the first end of the first NMOS tube control capacitance Cn1.The grid of the first transmission PMOS Pt1 connects the grid of the first charging PMOS Pc1, and source electrode and substrate link together, and connect source electrode and the substrate of the first charging PMOS Pc1, are the first output, exports the first output signal Vo1.The drain electrode of the first charging PMOS Pc1 connects the first end of the first PMOS control capacitance Cp1.Second end of the first NMOS tube control capacitance Cn1, the first transmission electric capacity Ct1 and the first PMOS control capacitance Cp1 links together, access first-phase clock signal clka.
As shown in Figure 4, in embodiments of the invention, the second transmission unit 420 comprises the second charging NMOS tube Nc1 ' (N-type metal-oxide-semiconductor), the second transmission NMOS tube Nt1 ' (N-type metal-oxide-semiconductor), the second charging PMOS Pc1 ' (P type metal-oxide-semiconductor), the second transmission PMOS Pt1 ' (P type metal-oxide-semiconductor), the second NMOS tube control capacitance Cn1 ', the second PMOS control capacitance Cp1 ' and the second transmission electric capacity Ct1 '.
In the second transmission unit 420, the drain electrode of the second transmission NMOS tube Nt1 ' is the second input, access the second input signal Vin ', grid connects the grid of the second charging NMOS tube Nc1 ', and source electrode connects the first end of the second transmission electric capacity Ct1 ' and the drain electrode of the second transmission PMOS Pt1 '.The drain electrode of the second charging NMOS tube Nc1 ' connects the drain electrode of the second transmission NMOS tube Nt1 ', and also access the first input signal Vin ', source electrode connects the first end of the second NMOS tube control capacitance Cn1 '.The grid of the second transmission PMOS Pt1 ' connects the grid of the second charging PMOS Pc1 ', and source electrode and substrate link together, and connect source electrode and the substrate of the second charging PMOS Pc1 ', are the second output, exports the second output signal Vo1 '.The drain electrode of the second charging PMOS Pc1 ' connects the first end of the second PMOS control capacitance Cp1 '.Second end of the second NMOS tube control capacitance Cn1 ', the second transmission electric capacity Ct1 ' and the second PMOS control capacitance Cp1 ' links together, access second-phase clock signal clka '.
And, the grid of the first transmission NMOS tube Nt1 in the first transmission unit 410 and the grid of the first charging NMOS tube Nc1, also connect the second charging source electrode of NMOS tube Nc1 ' and first end of the second NMOS tube control capacitance Cn1 ' in the second transmission unit 420.The grid of the second transmission NMOS tube Nt1 ' in the second transmission unit 420 and the grid of the second charging NMOS tube Nc1 ', also connect the first charging source electrode of NMOS tube Nc1 and first end of the first NMOS tube control capacitance Cn1 in the first transmission unit 410.
The grid of the first transmission PMOS Pt1 in the first transmission unit 410 and the grid of the first charging PMOS Pc1, also connect the second charging drain electrode of PMOS Pc1 ' and first end of the second PMOS control capacitance Cp1 ' in the second transmission unit 420.The grid of the second transmission PMOS Pt1 ' in the second transmission unit 420 and the grid of the second charging PMOS Pc1 ', also connect the first charging drain electrode of PMOS Pc1 and first end of the first PMOS control capacitance Cp1 in the first transmission unit 410.
Embodiment shown in Fig. 4, first NMOS tube control capacitance Cn1 is the control capacitance of the second charging NMOS tube Nc1 ' and second transmission NMOS tube Nt1 ', first PMOS control capacitance Cp1 is the control capacitance of the second charging PMOS Pc1 ' and second transmission PMOS Pt1 ', second NMOS tube control capacitance Cn1 ' is the control capacitance of the first charging NMOS tube Nc1 and first transmission NMOS tube Nt1, and the second PMOS control capacitance Cp1 ' is the control capacitance of the first charging PMOS Pc1 and first transmission PMOS Pt1.First transmission NMOS tube Nt1 and second transmission NMOS tube Nt1 ' is the NMOS tube in charge transfer path, and the first transmission PMOS Pt1 and second transmission PMOS Pt1 ' is the PMOS in charge transfer path.First charging NMOS tube Nc1 is used for being that the first NMOS tube control capacitance Cn1 charges, and the second charging NMOS tube Nc1 ' is for charging for the second NMOS tube control capacitance Cn1 '; First charging PMOS Pc1 is used for being that the first PMOS control capacitance Cp1 charges, and the second charging PMOS Pc1 ' is for charging for the second PMOS control capacitance Cp1 '.
First-phase clock signal clka and second-phase clock signal clka ' is two-phase complementary clock as shown in Figure 3, can make at any one time, all there are two metal-oxide-semiconductors in running order (please refer to labor described later) in first transmission NMOS tube Nt1, the first transmission PMOS Pt1, the second transmission NMOS tube Nt1 ' and second transmission PMOS Pt1 ', improve the efficiency of transferring charge in charge pump single-stage circuit.
Fig. 5 is the structural representation of a kind of charge pump circuit that the embodiment of the present invention provides.As shown in Figure 5, it comprises multistage (two-stage or the two-stage more than) charge pump single-stage circuit be as shown in Figure 4 connected step by step, the numeral identified in figure single-level circuit at different levels is arranged in the progression (which level) of charge pump circuit, x is integer, represent the quantity of charge pump single-stage circuit, also represent the progression of charge pump circuit in the present embodiment simultaneously.
As shown in Figure 5, in the charge pump circuit of the present embodiment, in first order single-level circuit, first input end and the second input link together, as the input of whole charge pump circuit, access input voltage Vdd, in xth level (xth level is afterbody) single-level circuit, the first output and the second output link together, and connect the first end of output capacitance Cout, and as the output of whole charge pump circuit, provide output voltage Vout; The second end ground connection of output capacitance Cout.
When the progression x of charge pump circuit is greater than 2, except the charge pump single-stage circuit of the first order and afterbody, in all the other charge pump single-stage circuit at different levels, the first input end of i-th grade of single-level circuit connects first output of the i-th-1 grade, and the second input connects second output of the i-th-1 grade; First output connects the first input end of the i-th+1 grade, and the second output connects second input of the i-th+1 grade; Wherein, i is the integer being more than or equal to 2 and being less than or equal to x-1, and xth level single-level circuit is afterbody single-level circuit.The first input end of such as second level charge pump single-stage circuit connects the first output of first order charge pump single-stage circuit, and the second input connects the second output of first order charge pump single-stage circuit; And for example the first input end of third level charge pump single-stage circuit connects the first output of second level charge pump single-stage circuit, and the second input connects the second output of second level charge pump single-stage circuit; Etc., by that analogy, charge pump single-stage circuit at different levels is serially connected, and forms the charge pump circuit of the present embodiment.
As shown in Figure 5, the clock signal complement (meanwhile, the clock signal that accesses of the second transmission unit of the single-level circuit of adjacent two-stage is also complementary) that accesses of the first transmission unit of the single-level circuit of adjacent two-stage.The first transmission unit in single-level circuit at different levels alternately accesses two-phase complementary clock signal, and the second transmission unit simultaneously in single-level circuit at different levels also alternately accesses this two-phase complementary clock signal.
Embodiment as shown in Figure 5, total upper and lower two charge transfer path, below in the first charge transfer path, electric charge is successively via Vdd, first order charge pump single-stage circuit first transmits NMOS tube Nt1, the first transmission electric capacity Ct1 and first transmission PMOS Pt1, second level charge pump single-stage circuit first transmits NMOS tube Nt2, the first transmission electric capacity Ct2 and first transmission PMOS Pt2, ..., xth level charge pump single-stage circuit first transmits NMOS tube Ntx, the first transmission electric capacity Ctx and first transmission PMOS Ptx, finally transfers to output.In second charge transfer path, the transmission of electric charge is corresponding with the transmission of electric charge in the first charge transfer path above, successively via Vdd, first order charge pump single-stage circuit second transmits NMOS tube Nt1 ', second transmission electric capacity Ct1 ' and second transmission PMOS Pt1 ', second level charge pump single-stage circuit second transmits NMOS tube Nt2 ', second transmission electric capacity Ct2 ' and second transmission PMOS Pt2 ', ..., xth level charge pump single-stage circuit second transmits NMOS tube Ntx ', second transmission electric capacity Ctx ' and second transmission PMOS Ptx ', finally transfer to output.Article two, the operation principle of charge transfer path is identical, below elaborates.
First suppose that first-phase clock signal clka is low level (such as voltage magnitude is 0) in the starting stage, second-phase clock signal clka ' is high level (such as amplitude is input voltage Vdd), and the voltage at all electric capacity two ends is all input voltage Vdd.In first order charge pump single-stage circuit, the gate source voltage Vgs < cut-in voltage Vthn of the second transmission NMOS tube Nt1 ' and second charging NMOS tube Nc1 ', then two pipes are all operated in cut-off region, and input voltage Vdd can not charge to the second transmission electric capacity Ct1 ' and the second NMOS tube control capacitance Cn1 '.The gate source voltage Vgs of the second transmission PMOS Pt1 ' and second charging PMOS Pc1 ' in first order charge pump single-stage circuit is much larger than cut-in voltage Vthp, the gate source voltage Vgs of the second transmission NMOS tube Nt2 ' and second charging NMOS tube Nc2 ' in the charge pump single-stage circuit of the second level is also much larger than cut-in voltage Vthn, they are all operated in dark linear zone, electric charge transfers to the second transmission electric capacity Ct2 ' in the charge pump single-stage circuit of the second level (the second transmission electric capacity Ct1 ' and the second PMOS control capacitance Cp1 ' in other words this moment in first order charge pump single-stage circuit by the drain electrode of the second transmission NMOS tube Nt2 ' in the source electrode of the second transmission PMOS Pt1 ' of the second transmission electric capacity Ct1 ' in first order charge pump single-stage circuit in first order single-level circuit and second level single-level circuit, second these four electric capacity of transmission electric capacity Ct2 ' and the second NMOS tube control capacitance Cn2 ' in the charge pump single-stage circuit of the second level share electric charge, till the electromotive force of their positive plate is equal).
Meanwhile, in first charge transfer path, the first transmission NMOS tube Nt1 and first charging NMOS tube Nc1 in first order charge pump single-stage circuit is operated in dark linear zone, electric charge transfers to electric capacity first by Vdd and transmits electric capacity Ct1 and the first NMOS tube control capacitance Cn1, till the voltage of the first transmission electric capacity Ct1 and the first NMOS tube control capacitance Cn1 charges to Vdd; The first transmission PMOS Pt1 and first charging PMOS Pc1 in first order charge pump single-stage circuit, the first transmission NMOS tube Nt2 and first charging NMOS tube Nc2 in the charge pump single-stage circuit of the second level is all operated in cut-off region, and electric charge can not be transferred on the first transmission electric capacity Ct2 in the charge pump single-stage circuit of the second level by the drain electrode of the first transmission NMOS tube Nt2 in the source electrode of the first transmission PMOS Pt1 of the first transmission electric capacity Ct1 in first order single-level circuit in first order charge pump single-stage circuit and second level single-level circuit.
When first-phase clock signal clka by low level overturn be high level, after second-phase clock signal clka ' is overturn be low level by high level, in first order charge pump single-stage circuit, the grid voltage of the second transmission NMOS tube Nt1 ' and second charging NMOS tube Nc1 ' increases, two pipe works are in dark linear zone, and electric charge transfers to the second transmission electric capacity Ct1 ' and the second NMOS tube control capacitance Cn1 ' by input (Vdd), the grid voltage of the second transmission PMOS Pt1 ' and second charging PMOS Pc1 ' in first order charge pump single-stage circuit increases, two pipe works are in cut-off region, the second transmission NMOS tube Nt2 ' and second charging NMOS tube Nc2 ' grid voltage in the charge pump single-stage circuit of the second level reduces, also cut-off region is operated in, therefore electric charge can not be transferred to the second transmission electric capacity Ct2 ' in the charge pump single-stage circuit of the second level by the drain electrode of the second transmission NMOS tube Nt2 ' in the source electrode of the second transmission PMOS Pt1 ' of the second transmission electric capacity Ct1 ' in first order single-level circuit in first order charge pump single-stage circuit and second level single-level circuit.Meanwhile, in second charge transfer path, the first transmission NMOS tube Nt1 and first charging NMOS tube Nc1 in first order charge pump single-stage circuit is operated in cut-off region, and input voltage Vdd can not charge to the first transmission electric capacity Ct1 and the first NMOS tube control capacitance Cn1, in first order charge pump single-stage circuit first transmission PMOS Pt1 and and first charging PMOS Pc1, the first transmission NMOS tube Nt2 and first charging NMOS tube Nc2 in the charge pump single-stage circuit of the second level is operated in dark linear zone, the first transmission electric capacity Ct2 that electric charge is transferred in the charge pump single-stage circuit of the second level by the drain electrode of the first transmission NMOS tube Nt2 in the source electrode of the first transmission PMOS Pt1 of the first transmission electric capacity Ct1 in first order charge pump single-stage circuit in first order single-level circuit and second level single-level circuit is upper, and (first in first order charge pump single-stage circuit transmits electric capacity Ct1 and the first PMOS control capacitance Cp1 this moment in other words, second these four electric capacity of transmission electric capacity Ct2 and the first NMOS tube control capacitance Cn2 in the charge pump single-stage circuit of the second level share electric charge, till the electromotive force of their positive plate is equal).
Like this, the charge pump circuit shown in Fig. 5 just completes the transferring charge work in the clock cycle.At subsequent clock period, the second level ..., until the course of work of xth level is identical with the first order, can understands with reference to the process of the aforementioned first order and second level charge pump single-stage circuit transmission electric charge, not repeat herein.Along with the propelling of clock, the electric charge in the charge pump circuit of the present embodiment is constantly shifted to rear class by prime, until output voltage is raised to desired value.
From the course of work above, the course of work of upper and lower two charge transfer path is complementary, if the i.e. half period before clock, electric charge is provided to output by the second charge transfer path above, then provide electric charge by the first charge transfer path below to output in second cycle of clock, thus ensure within the whole clock cycle, the driving force of charge pump is all the same, which enhance operating efficiency, reduce the ripple of charge pump output voltage.In addition, in each charge transfer path, the grid voltage of transferring charge pipe is all produced by another charge transfer path, this grid voltage remains constant within the corresponding cycle, particularly, during transferring charge, higher grid voltage ensure that NMOS tube always works in dark linear zone, lower grid voltage ensure that PMOS always works in dark linear zone, thus guarantee during transferring charge, conduction pipe always works in dark linear zone, turn off pipe to end all the time, eliminate the impact of threshold voltage, improve the efficiency of transmission of electric charge, improve the voltage gain of every one-level charge pump single-stage circuit, electric charge transmits close to 100% ground, improve the efficiency of transmission of electric charge.
Compare existing Dickson charge pump, embodiments of the invention are more suitable for work at a low input voltages, and such as 1.2 volts (V) are even lower.Because the threshold voltage of NMOS tube is 0.8 volt of V, if the input voltage adopting existing Dickson charge pump is 1.2V, then the transmission capacitor charging of the first order can only be given to 0.4V, and the closer to output stage, receptor effect impact is larger, and the threshold voltage of NMOS tube can increase, as 1.0V etc.If threshold voltage increases to 1.2V, more backward just can not transmission charge, output voltage would not increase.Embodiments of the invention overcome this defect, and the every one-level in charge pump circuit can transmit whole electric charges.
Although the execution mode disclosed by the present invention is as above, the execution mode that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technical staff in any the technical field of the invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (4)
1. a charge pump single-stage circuit, comprises the first transmission unit and the second transmission unit, wherein:
Described first transmission unit comprises the first clock incoming end, first input end and the first output, and described first input end is for accessing the first input signal, and described first output is for exporting the first output signal;
Described second transmission unit comprises second clock incoming end, the second input and the second output, and described second input is for accessing the second input signal, and described second output is for exporting the second output signal;
Described first clock incoming end and second clock incoming end access the wherein phase in two-phase complementary clock signal respectively, electric charge is transferred to the first output from described first input end for following accessed clock signal by described first transmission unit, and electric charge is transferred to the second output from described second input for following accessed clock signal by described second transmission unit;
Wherein: described first transmission unit comprises the first transmission circuit, comprise the first input control circuit of four control ends and comprise the first output control circuit of four control ends, wherein:
Described first transmission circuit comprises described first clock incoming end, first input end and the first output, also comprises the first input control end and the first output control terminal;
First control end of described first input control circuit connects described first input end, and the second control end connects described first clock incoming end, and the 3rd control end connects described first input control end;
First control end of described first output control circuit connects described first output, and the second control end connects described first clock incoming end, and the 3rd control end connects described first output control terminal;
4th control end of described first input control circuit and the 4th control end of described first output control circuit connect described second transmission unit respectively, turn off for the clock signal of following described first clock incoming end access or open described second transmission unit transmission charge;
Wherein, described first input control circuit comprises the first charging NMOS tube Nc1 and the first NMOS tube control capacitance Cn1, wherein:
The drain electrode of described first charging NMOS tube Nc1 is the first control end of described first input control circuit, and grid is the 3rd control end of described first input control circuit, and source electrode is the 4th control end of described first input control circuit;
The first end of described first NMOS tube control capacitance Cn1 connects the source electrode of described first charging NMOS tube Nc1, and the second end is the second control end of described first input control circuit;
Wherein, described first output control circuit comprises the first charging PMOS Pc1 and the first PMOS control capacitance Cp1, wherein:
Source electrode and the substrate of described first charging PMOS Pc1 link together, and be the first control end of described first output control circuit, grid is the 3rd control end of described first output control circuit, drains as the 4th control end of described first output control circuit;
The first end of the first PMOS control capacitance Cp1 connects the drain electrode of described first charging PMOS Pc1, and the second end is the second control end of described first output control circuit;
Wherein:
Described second transmission unit comprises the second transmission circuit, comprise the second input control circuit of four control ends and comprise the second output control circuit of four control ends, wherein:
Described second transmission circuit comprises described second clock incoming end, the second input and the second output, also comprises the second input control end and the second output control terminal;
First control end of described second input control circuit connects described second input, and the second control end connects described second clock incoming end, and the 3rd control end connects described second input control end;
First control end of described second output control circuit connects described second output, and the second control end connects described second clock incoming end, and the 3rd control end connects described second output control terminal;
4th control end of described second input control circuit and the 4th control end of described second output control circuit connect described first transmission unit respectively, turn off for the clock signal of following the access of described second clock incoming end or open described first transmission unit transmission charge;
Wherein, described second input control circuit comprises the second charging NMOS tube Nc1 ' and the second NMOS tube control capacitance Cn1 ', wherein:
The drain electrode of described second charging NMOS tube Nc1 ' is the first control end of described second input control circuit, and grid is the 3rd control end of described second input control circuit, and source electrode is the 4th control end of described second input control circuit;
The first end of described second NMOS tube control capacitance Cn1 ' connects the source electrode of described second charging NMOS tube Nc1 ', and the second end is the second control end of described second input control circuit;
Wherein, described second output control circuit comprises the second charging PMOS Pc1 ' and the second PMOS control capacitance Cp1 ', wherein:
Source electrode and the substrate of described second charging PMOS Pc1 ' link together, for the first control end of described second output control circuit, grid is the 3rd control end of described second output control circuit, drains as the 4th control end of described second output control circuit;
The first end of the second PMOS control capacitance Cp1 ' connects the drain electrode of described second charging PMOS Pc1 ', and the second end is the second control end of described second output control circuit.
2. charge pump single-stage circuit as claimed in claim 1, wherein, described first transmission circuit comprises the first transmission NMOS tube Nt1, the first transmission PMOS Pt1 and first transmission electric capacity Ct1, wherein:
The drain electrode of described first transmission NMOS tube Nt1 is described first input end, and grid is described first input control end, and source electrode connects the first end of described first transmission electric capacity Ct1 and the drain electrode of described first transmission PMOS Pt1;
Second end of described first transmission electric capacity Ct1 is described first clock incoming end;
The grid of described first transmission PMOS Pt1 is described first output control terminal, and source electrode and substrate link together, and are described first output.
3. charge pump single-stage circuit as claimed in claim 1, wherein, described second transmission circuit comprises the second transmission NMOS tube Nt1 ', the second transmission PMOS Pt1 ' and second transmission electric capacity Ct1 ', wherein:
The drain electrode of described second transmission NMOS tube Nt1 ' is described second input, and grid is described second input control end, and source electrode connects the first end of described second transmission electric capacity Ct1 ' and the drain electrode of described second transmission PMOS Pt1 ';
Second end of described second transmission electric capacity Ct1 ' is described second clock incoming end;
The grid of described second transmission PMOS Pt1 ' is described second output control terminal, and source electrode and substrate link together, and are described second output.
4. a charge pump circuit, comprises at least single-level circuit of two-stage any one of claims 1 to 3 as described in claim, wherein:
First input end and second input of first order single-level circuit link together, as the input of described charge pump circuit; First output and second output of afterbody single-level circuit link together, as the output of described charge pump circuit, and through output capacitance ground connection;
When the progression x of described charge pump circuit is greater than 2, the first input end of i-th grade of single-level circuit connects the first output of the i-th-1 grade single-level circuit, and the second input connects the second output of the i-th-1 grade single-level circuit; Wherein, i is more than or equal to 2 and is less than or equal to x-1, and xth level single-level circuit is described afterbody single-level circuit;
The clock signal complement of the first transmission unit access of the single-level circuit of adjacent two-stage;
Wherein: described first transmission unit comprises the first transmission circuit, comprise the first input control circuit of four control ends and comprise the first output control circuit of four control ends, wherein:
Described first transmission circuit comprises described first clock incoming end, first input end and the first output, also comprises the first input control end and the first output control terminal;
First control end of described first input control circuit connects described first input end, and the second control end connects described first clock incoming end, and the 3rd control end connects described first input control end;
First control end of described first output control circuit connects described first output, and the second control end connects described first clock incoming end, and the 3rd control end connects described first output control terminal;
4th control end of described first input control circuit and the 4th control end of described first output control circuit connect described second transmission unit respectively, turn off for the clock signal of following described first clock incoming end access or open described second transmission unit transmission charge;
Wherein, described first input control circuit comprises the first charging NMOS tube Nc1 and the first NMOS tube control capacitance Cn1, wherein:
The drain electrode of described first charging NMOS tube Nc1 is the first control end of described first input control circuit, and grid is the 3rd control end of described first input control circuit, and source electrode is the 4th control end of described first input control circuit;
The first end of described first NMOS tube control capacitance Cn1 connects the source electrode of described first charging NMOS tube Nc1, and the second end is the second control end of described first input control circuit;
Wherein, described first output control circuit comprises the first charging PMOS Pc1 and the first PMOS control capacitance Cp1, wherein:
Source electrode and the substrate of described first charging PMOS Pc1 link together, and be the first control end of described first output control circuit, grid is the 3rd control end of described first output control circuit, drains as the 4th control end of described first output control circuit;
The first end of the first PMOS control capacitance Cp1 connects the drain electrode of described first charging PMOS Pc1, and the second end is the second control end of described first output control circuit.
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| CN103872904B (en) * | 2014-03-17 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Electric charge pump and memorizer |
| CN106026637B (en) * | 2016-07-06 | 2018-05-25 | 西安紫光国芯半导体有限公司 | A kind of charge pump circuit and its single-level circuit |
| CN107592012B (en) * | 2017-09-20 | 2024-01-02 | 深圳贝特莱电子科技股份有限公司 | Multi-stage multiphase high voltage charge pump for generating high voltage at low voltage by using medium-low voltage device |
| CN108880233B (en) * | 2018-08-03 | 2023-10-24 | 上海艾为电子技术股份有限公司 | Charge pump circuit |
| CN115987092B (en) * | 2023-03-22 | 2023-05-23 | 上海海栎创科技股份有限公司 | Cross-coupled charge pump unit and structure |
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| FR2864272B1 (en) * | 2004-04-30 | 2006-05-26 | Atmel Corp | HIGH EFFICIENCY, LOW COST LOAD PUMP CIRCUIT |
| CN101212174A (en) * | 2006-12-31 | 2008-07-02 | 中国科学院半导体研究所 | Charge pump circuit for passive radio frequency identification system |
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| CN102281000A (en) * | 2011-07-27 | 2011-12-14 | 清华大学 | High-efficiency charge pump under low power supply voltage |
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| US7446596B1 (en) * | 2007-05-25 | 2008-11-04 | Atmel Corporation | Low voltage charge pump |
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| FR2864272B1 (en) * | 2004-04-30 | 2006-05-26 | Atmel Corp | HIGH EFFICIENCY, LOW COST LOAD PUMP CIRCUIT |
| CN101212174A (en) * | 2006-12-31 | 2008-07-02 | 中国科学院半导体研究所 | Charge pump circuit for passive radio frequency identification system |
| CN101753012A (en) * | 2008-12-12 | 2010-06-23 | 中芯国际集成电路制造(北京)有限公司 | Charge pump circuit |
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