CN103141029B - Sampler circuit - Google Patents
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- CN103141029B CN103141029B CN201180047188.XA CN201180047188A CN103141029B CN 103141029 B CN103141029 B CN 103141029B CN 201180047188 A CN201180047188 A CN 201180047188A CN 103141029 B CN103141029 B CN 103141029B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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Abstract
A kind of sampler circuit comprises multiple sampler unit of being connected in series and detector circuit.Each connecting stage comprises the sampler unit that parallel quantity is previous stage twice, and at the half place of the sample frequency of previous stage clock in addition.Each sampler unit comprises two parallel branchs of the clock inverter be connected in series.Clock inverter operation with during a stage of the sampling clock applied to the signal inversion applied, and obtain high impedance output during another sampling clock phase.The clock inverter continued utilizes relative (namely positive/negative) version of sampling clock to carry out clock.Detector circuit checks the output of the most rear class of sampler unit, and can such as comprise OR(or) function is to detect the state-transition in the input signal applied.Sampler circuit shows immunity for metastability and low-power consumption.
Description
This application claims submit on September 30th, 2010 be entitled as " ReferenceClockSamplerCircuitforDigitalPLL(is used for the reference clock sampler circuit of digital phase-locked loop) ", sequence number is No.61/388, the priority of the U.S. Utility Patent application that what the U.S. Provisional Patent Application of 302 and on August 4th, 2011 submitted to is entitled as " ReferenceClockSamplerCircuitforDigitalPLL(is used for the reference clock sampler circuit of digital phase-locked loop) ", the disclosure of these documents is all herein incorporated by reference.Transfer this application assignee and meanwhile submit to be co-pendingly entitled as " ReferenceClockSamplingDigitalPLL(reference clock sampling digital phase-locked loop) ", U.S. Patent application that sequence number is No._ is all herein incorporated by reference.
Technical field
Present invention relates in general to sample circuit, and especially relate to a kind of clock inverter sampler circuit substantially eliminating metastability.
Background technology
Sampler circuit is by quantizing the signal applied rapidly or sample and one or more feature of the signal becoming representative to sample sample process and determine the circuit of the state of this signal.In some applications, sampler circuit only can need the special characteristic for determining the signal applied, the such as timing of the state-transition of the periodic signal of such as dagital clock signal and so on.
Phase-locked loop (PLL) is a kind of circuit of the known high frequency output signal for deriving stable (sometimes variable or adjustable).PLL is widely used in telecommunication circuit, such as, to produce the carrier wave and local oscillator frequencies signal that are used for modulation and demodulation radiocommunication signals.Radio frequency (RF) signal of frequency division and reference clock compare to realize phase-locked by PLL, thus the frequency that the RF of the non-frequency division of stabilisation exports.Figure 11 depicts the functional block diagram of conventional simulation PLL.The phase place of the reference clock in the accurate source 14 from such as crystal oscillator and so on and the feedback signal from frequency divider 16 compare by phase-frequency detector (PFD) 12.RF is outputed signal downward frequency division to PLL frequency of operation by frequency divider 16.PFD12 converts control voltage level to reference to the phase difference between clock and the RF signal of frequency division and exports.PDF12 exports and carries out low-pass filtering by filter 18, and control voltage is imported into the voltage controlled oscillator (VCO) 19 of the frequency changing RF output signal in response to control voltage level.
Recently, digital PLL framework develops, wherein with quantize mode measure phase difference and the digital control codes converted thereof into for numerically-controlled oscillator (DCO).Digital phase detector measure phase difference.The digital phase detector of prior art is subject to the impact of metastability issues due to the reason of the asynchronous relationship between sampling clock and the reference clock of sampling.In addition, known digital phase detector is not very sensitive, and they suffer sluggish and dead band/dead time due to the reason of regenerative gain.
Summary of the invention
According to described herein and claimed one or more embodiments, a kind of sampler circuit comprises multiple sampler unit (cell) of being connected in series and detector circuit.Each connecting stage comprises the sampler unit that parallel quantity is previous stage twice, and at the half place of the sample frequency of previous stage clock in addition.Each sampler unit comprises two parallel branchs of the clock inverter be connected in series.Clock inverter operation with during a stage of the sampling clock applied to the signal inversion applied, and obtain high impedance output during another sampling clock phase.The clock inverter continued utilizes relative (namely positive/negative) version of sampling clock to carry out clock.In this arrangement, each clock inverter is as having the sampling of gain and holding circuit and operating, and wherein keeping capacitor is the input capacitance of next inverter.Clock inverter also can be considered to the transparent latch with anti-phase output, can conformation function trigger by it.Detector circuit checks the output of the most rear class of sampler unit, and can such as comprise OR(or) function is to detect the state-transition in the input signal applied.Sampler circuit shows immunity for metastability and low-power consumption.Sampler circuit can find specific effectiveness by being used as the numerically-controlled oscillator of sampling clock to the reference clock sampling of digital phase-locked loop.
An embodiment relates to a kind of sampler circuit, and its operation detects one or more transformation edges of the input signal being applied to this sampler circuit.This sampler circuit comprises signal input, sampling clock inputs and one or more levels be connected in series of sampler unit.Each sampler unit comprises two parallel branchs of the clock inverter be connected in series.Each clock inverter operation is applied to the anti-phase of the input of clock inverter with output during a stage of sampling clock and represents, and operates to obtain high impedance in its output during another stage of sampling clock further.Clock inverter in each branch alternately carries out clock by sampling clock and anti-phase sampling clock.The operation of each sampler unit with in the frequency determined by sampling clock to the signal sampling of input being applied to sampler unit, and export two parallel sample streams at the half place of sample clock frequency, the sample in each stream is from input signal demultiplexing.Described sampler circuit also comprises detector circuit, and the operation of this detector circuit detects one or more transformation edges of the signal being applied to sampler unit input according to the output of the last sampler unit in the level be connected in series of sampler unit.
Another embodiment relates to a kind of method that detection is applied to the transformation edge of the input signal of sample circuit.Receive the input signal and the sampled clock signal that are applied to sampler circuit.Utilize one or more levels be connected in series of sampler unit to the input signal sampling being applied to sampler circuit.Each level be connected in series of sampler unit comprises two parallel branchs of the clock inverter be connected in series.Each clock inverter operation exports the anti-phase expression being applied to the input of clock inverter during a stage of sampling clock, and operation obtains high impedance in its output during another stage of sampling clock further.The operation of each sampler unit to the signal sampling of input being applied to sampler unit in the frequency determined by sampling clock, and operates further and exports two parallel sample streams at the half place of sample clock frequency.Sample in each stream is from input signal demultiplexing.One or more transformation edges of the input signal of sampler circuit are applied to according to the output detections of the last sampler unit in the level be connected in series of sampler unit.
Accompanying drawing explanation
Fig. 1 is the functional schematic of the sampler circuit according to one embodiment of the invention.
Fig. 2 is the functional block diagram of sampler unit.
Fig. 3 is the functional schematic of sampler unit.
Fig. 4 is the functional schematic of interchangeable sampler unit.
Fig. 5 is the sequential chart of the operation of the sampler unit drawing Fig. 2-4.
Fig. 6 is the functional block diagram of sampler circuit.
Fig. 7 is the functional block diagram drawing the demultiplexing of input amendment and the sampler unit of parallelization.
Fig. 8 is the functional block diagram of the digital phase-locked loop of the sampler circuit adopting Fig. 6.
Fig. 9 is the functional block diagram of four phase sampler device circuit.
Figure 10 is the flow chart of the method to signal sampling.
Figure 11 is the functional block diagram of prior art analog phase-locked look.
Embodiment
In DPLL, it is asynchronous each other that reference clock and DCO export.In fact, these two signals are locked to each other only by DPLL corrective action.So, utilize the clock of deriving from DCO output to cause significant metastability deeply concerned to reference clock sampling.Phase difference between these two clocks is in lasting change.When phase difference close to 0 time, exist wherein do not know that sampled value is the brief duration of logical zero or logical one.In the implementation of reality, this duration is actually a little time window, and for this time window, the correct level of sampled signal can not suitably be resolved.This is called metastability window.
Most of sampler circuit adopts the Regenerative feedback of certain form to derive logical zero or logical one from the input signal of sampling.The speed that input signal is resolved to logical zero or logical one by regenerative circuit exponentially depends on the amplitude of input signal.If input signal is sampled at its zero crossing (zero-crossing) (phase difference is 0) place, so regenerative circuit may spend a large amount of time to reach stable state (logical zero or logical one).If sample circuit exports and is not resolved, so DPLL may fully charge.Therefore, metastability must be avoided at all costs.The many circuit implementations reducing metastability window come forth; Known neither one completely avoid metastability.
Sampler circuit according to the embodiment of the present invention substantially eliminates metastability concern by design.Fig. 1 depicts an embodiment of sampler circuit 20 of the present invention.Sampler circuit 20 comprises one or more levels be connected in series of sampler unit 22 and detector circuit 24.Sampler circuit 20 detects the state-transition in input signal, and this input signal can such as comprise reference frequency clock signal.Sampler circuit 20 exports the n-bit numeric word of the state-transition described in input signal usually, the quantization means of such as input signal or cycle count.
The frequency place that each sampler unit 22 is determined at sampling clock 26 samples to its input signal, and exports two parallel sample streams at the half place of sample clock frequency.As will be more completely explained herein, the alternately interlace value of the sample representation input signal in each stream.Sampling clock 26 can comprise DCO output or frequency division DCO exports.As shown in the figure, each sampler unit receives sampling clock and anti-phase, and namely sampling clock 26 is for having the balanced signal of the positive and negative component (i.e. 180 ° of out-phase) (being called CKP and CKN in this article) of coupling.Because each sampler unit 22 exports two parallel sample streams at the half place of sample clock frequency, each connecting stage of the sampler unit 22 be connected in series thus in sampler circuit 20 comprises sampler unit 22(setting concurrently in each level that quantity is the twice of first prime).So, the sampler unit 22 of each connecting stage as indicated in figure 1 carry out clock by clock divider circuit 28 at the half place of the sample clock frequency of first prime.Usually, sampler unit 22 can comprise the level of any amount of the sampler unit 22 be connected in series.
Detector circuit 24 is according to one or more state-transition of the output detections input signal of the most rear class of sampler unit 22.The output of detector circuit 24 is for comprising the n-bit numeric word of the information of the state-transition of the input signal about sampler circuit 20.Detector circuit 24 can comprise gate, or can comprise the rearrangement of output of most rear class of sampler unit 22 simply.After the structure explaining sampler unit 22 and operation, content and the form of the configuration of the detector circuit 24 in each different embodiment and operation and the output of n-bit numeral will be clearly for those skilled in the art.
Fig. 2 depicts the function diagram of sampler unit 22.Sampler unit 22 comprises two parallel branches, and each branch comprises the clock inverter 30 be connected in series.Clock inverter 30 in each branch alternately carries out clock by positive and negative sampling clock.As use alpha nerein, term " clock inverter " 30 refers to such circuit, it exports the anti-phase expression of the input of applying during a state of the sampling clock applied, and provides high impedance or " tri-state " in its output during another state of sampling clock.When as in Fig. 1 paint be connected in series time, each clock inverter 30 together with the input capacitance of its connecting circuit (such as another inverter) as there is the sampling of gain and maintenance (S & H) unit and operating.The part (namely during operational phase of the sampling clock applied) during its inverter operation of clock inverter 30 provides gain, and the input capacitance of ensuing inverter serves as S & H unit keeping capacitor.Take the gain of modern CMOS processes and every inverter 10 times, be connected in series five clock inverters and realize 100,000 times of gain.This is enough to by applying an electronics in the input of the first clock inverter and produces rail-to-rail signal (such as completely saturated logical zero or logical one).
Fig. 3 depicts with an embodiment of the sampler unit 22 of Fig. 2 of CMOS realization.Each clock inverter 30 comprises four MOS transistor 32,34,36,38---two PMOS transistor, 32,34 and two nmos pass transistors 36,38 be connected in series between supply path and ground connection path.Input is connected to and forms a PMOS transistor 34 of regular inverter and the grid of nmos pass transistor 36.Positive sampled clock signal CKP is connected to the grid of PMOS transistor 32, and negative sampled clock signal CKN is connected to the grid of nmos pass transistor 38, the two and the inverter series formed by transistor 34,36.During CKP is high and CKN is the first stage of low clock cycle, transistor 32,38 by inverter transistor 34,36 with supply path and isolate, and export E1 and be in high impedance.During CKP is low and CKN is the second stage of high clock cycle, transistor 32,38 conducting, and transistor 34,36 anti-phase and amplify the state of the signal that its grid place exists.
Fig. 4 depicts another embodiment of sampler unit 22, and the transistor 32,38 wherein applying clock signal to it is positioned at the center of transistor stack, and is located transistor 34,36 anti-phase for data-signal near VDD and VSS node.This layout is by upper frequency sampled clock signal 26 centering.Standard practices in CMOS design is the center transistor at upper frequency place switch being arranged on transistor stack.
Clock inverter 30 does not comprise any feedback of such as cross-coupled gates and so on to form memory element.Each clock inverter 30 can not the state of storage signal individually.But when being connected in series as illustrated in figs. 2-4, each clock inverter 30 utilizes the input capacitance of ensuing inverter 30 effectively to serve as S & H unit with stored logic levels while being in high impedance status in its output.When connecting with this configuration, each clock inverter 30 during a stage of sampling clock 26 by its input inversion---thus can be changed it export, and keep certain logic state in its output during another stage of sampling clock 26.So when so arranged, each clock inverter 30 operates as the transparent latch with anti-phase output.As known in the art, the cascade transparent latch relative stage of clock operated achieves " MS master-slave " trigger function.
Fig. 5 is the sequential chart of the operation of drawing sampler unit 22.Input signal D is depicted as to be had uniquely and the input value of the unknown during each half period of sampling clock 26.These states are depicted as digital 0-7 in Figure 5.It should be pointed out that these numerals not reflection such as many bit values on the data bus, but reflect the state of input signal D.Any one in the state 0-7 described can comprise state-transition or edge.The state of the input of the operation edge of sampling clock 26 is the things not having metastability issues of catching in the first order of the clock inverter 30 be connected in series.
The output of the first clock inverter in " idol " branch being expressed as E1 is by the state inversions of input signal D during each low stage of positive sampling clock CKP, and first is expressed as " zero stick " in Figure 5.During the follow-up high-stage of positive sampling clock CKP, as indicated by a dotted line in Fig. 5, this value remains on node E1 place by charging (output of the first clock inverter 30 is in high impedance status) to the input capacitance of the transistor in ensuing clock inverter 30.Equally in this sampling clock phase (high-stage of CKP) period, input signal D has the state represented by numeral 1, and the state at node E1 place is anti-phase at output E2 place, because compared with the first clock inverter, clock signal overturns at the second clock inverter 30 place.At the next one of CKP low stage place, the current state being expressed as the input signal D of 2 is anti-phase at node E1 place, and state 0 is anti-phase at node E3 place.Last inverter 40 provides input capacitance so that in the state of node E3 place inhibit signal during the positive stage of CKP, and even at EVEN() output is by state inversions.
In a comparable manner, " very " sample 1-7 is captured and is propagated by the odd component of sampler unit 22 and strange at ODD() export 40 places and present (anti-phase).For the complete period of sampling clock 26, the state of input signal D is sampled at the place of each half period of sampling clock 26, and presents in EVEN or the ODD output of sampler unit 22.Therefore the frequency of sampled signal is divided equally and is split into two parallel outputs from single input.In the sampler circuit 20 of reality, sampler unit 22 can be connected in series at different levels, and each connecting stage comprises the sampler unit 22 that parallel quantity is the twice of previous stage, and each connecting stage carries out clock at the half place of the sample frequency of previous stage.
Fig. 6 depicts the sampler circuit 20 comprising level Four sampler unit 22, every grade of quantity doubling sampler unit 22 and divide the frequency of sampling clock 26 equally.As mentioned above, when such as Fig. 2, Fig. 3 and cascade depicted in figure 4, clock inverter 30 operates as the transparent latch with anti-phase output.This is in figure 6 by the alphabetical L instruction on each clock inverter 30.
Fig. 7 depicts first three grade of sampler unit 22 of the sampler circuit 20 from Fig. 6.How the state that Fig. 7 depicts sampling time 0-7 place input signal D is in detail captured, amplify, parallelization and reduce frequency at each connecting stage.The state of input signal uses digital " 0 " to " 7 " according to presenting to the time sequencing of first order sampler unit 22 (in other words, indicated by CKP signal and time orientation indicating device, signal condition comparatively early present to the right and comparatively after signal condition present to the left side) draw.Indicated by the duration of the status input signal in Fig. 7, at each connecting stage place of sampler unit 22, the sampling clock applied is the half of the frequency being applied to previous stage, and the doubles of sampler unit 22 in this grade.In this example, in three grades of sampler unit 22, the output of eight states of original input signal in the end level is by complete demultiplexing.
How the clock inverter 30 that Fig. 7 also depicts sampler unit 22 is formed in the function of two parallel trigger devices " idol " branch with added latch when being counted as transparent latch.But, with conventional latch or trigger unlike, clock inverter 30 does not have internal feedback path, does not have " making a policy " or regenerative gain, and so there is no the neurological susceptibility for metastability.There is what state regardless of in D, the input (even if very little amplitude) of the edge of sampling clock 26 is captured and is propagated by " idol " or " very " branch of sampler unit 22, until its value reaches logical zero or logical one level completely.The sampler unit 22 of the embodiment of the present invention is sampled, keep and amplify the state of input signal applied.In practice, clock inverter 30 can not be driven by with little signal, thus entirely eliminated any metastability issues in the significant digits trigger inside formed by the clock inverter 30 be connected in series.Therefore, the embodiment of sampler unit 22 of the present invention substantially eliminates metastability issues by design.
Fig. 7 further illustrates the logic that can be included in the embodiment that each are different in detector circuit 24.In order to re-create the state of sampled signal D, can resequence to output to place them with time sequencing simply, " very " branch along sampler unit 22 has responsible for the additional inverter (not indicating the anti-phase of the state in " very " branch in Fig. 7) needed for signal inversion.If target is only detect edge or the transformation of input signal, so exports and can carry out together or (OR) (or or non-(NOR)) operation.Cycle of input signal can by (" very " is exported anti-phase after) to the number count of logical zero or logical one value or pass through (such as utilizing counter) and measure the duration and consider that (accountfor) divides the frequency of sampling clock 26 equally at every grade of place and determine.The given disclosure, other useful functions of detector circuit 24 will be easily well-known for those skilled in the art.
Fig. 8 depicts a kind of digital PLL (DPLL) 50, and wherein sampler circuit 20 of the present invention is used for utilizing DCO derivation clock to sample to reference clock signal.DPLL50 comprise in numerically-controlled oscillator (DCO) 52, sampler circuit 20(Fig. 6 draw in detail), reference clock f
rEF54, cycle count circuit 56, difference channel 58 and loop filter 60.Frequency f
oUTthe DPLL50 output signal 51 at place is such as the frequency f of DCO52 output signal 62
dCOthe half of (by frequency division in clock division circuits 53).DPLL50 is based on utilizing DCO clock f
dCOto reference clock f
rEFsampling.DPLL50 is conceptually the frequency domain PLL of control DCO52.All calculating all performs in frequency instead of phase place.
In more detail, DCO52 is in frequency f
dCOplace produces and exports DCO clock 26.DCO clock f
dCO26 is the sampling clock to sampler circuit 20, and this sampler circuit is to having frequency
randomization reference clock signal 54 sample.In order to produce randomization reference clock signal 54, produce reference clock signal 64 from the reference clock source 66 of such as crystal oscillator and so on.The position at the transformation edge of reference clock signal 64 is by variable delay circuit 68 randomization from shake engine 70 receive delay modulator data.The transformation edge of randomization reference clock signal 54 prevents determines by frequency the spurious emissions that causes with the accumulation of the quantization error in compare operation.In over a long time,
the edge that only changes is randomized.
Be input to sampler circuit 20(see Fig. 6) D for having frequency
randomization reference clock signal 54.This clock is by being used as the DCO clock f of sampling clock
dCO26 and be sampled.In wireless transceiver, the usual selection of DCO frequency is the over-sampling rate of two times, 2 times of required local oscillator (LO) frequency (because 2*LO is convenient to produce orthogonal signalling).In this embodiment, can with 0.5*T
dCOresolution is sampled to reference clock.Sampler circuit 20 detects the transformation edge of randomization reference clock signal 54, and exports this information from detector circuit 24.
In DPLL50, cycle count circuit 56 receives Edge check information from sampler circuit 20, and determines the cycle (thus frequency) of randomization reference clock signal 54.This value compares at subtracter 58 place and frequency control word, and error signal is carried out low-pass filtering by loop filter 60 and is input to DCO52.The other details of DPLL50 is included in above-cited co-pending patent application.
Fig. 9 depicts an embodiment of DPLL, and wherein four phase sampler device circuit are by orthogonal clock---namely homophase (I) and have 90 degree of relative phase shifts orthogonal (Q) clock signal drive.In this embodiment, two sampler unit 22 walk abreast and arrange, and input signal are sampled into four parallel outputs, strange/even output on I passage and strange/even output on Q passage.These four sampler unit 22 chains exported further by the formation deserializer run at lower speeds or demodulation multiplexer process.In other words, in Fig. 9, in four frames on the right and Fig. 6, the sampler circuit 20 drawn constructs similarly.Those skilled in the art will easily recognize, can construct any heterogeneous sampler circuit (such as eight phases) similarly.
Those skilled in the art also will easily recognize, sampler circuit of the present invention can utilize DCO(to derive) any number of stages operatings of clock, convert input signal to multiple parallel output.Such as, multi-phase delay locking ring (DLL) can produce and drive the DCO(of sampler unit 22 to derive) multiple stages of clock.So sampler unit 22 can be counted as a kind of Serial-Parallel Converter of form.
Figure 10 depicts a kind of method 100 detecting the transformation edge of input signal.It will be recognized by those skilled in the art, sampling operation is continual.But the method can say that " beginning " is in step 102 place, wherein receives the input signal being applied to sampler circuit 20 together with sampled clock signal 26.In step 104 place, utilize one or more levels be connected in series of sampler unit 22 to the input signal sampling being applied to sampler circuit 20, each sampler unit 22 comprises two parallel branchs of the clock inverter 30 be connected in series.Each clock inverter 30 operates and is applied to the anti-phase of the input of clock inverter 30 represents to export during a stage of sampling clock, and further operation to obtain high impedance in its output during another stage of sampling clock.Each sampler unit 22 operate with in the frequency determined by sampling clock 26 to the signal sampling of input being applied to sampler unit 22, and export two parallel sample streams at the half place of sampling clock 26 frequency, the sample demultiplexing from input signal wherein in each stream.In step 106, from the output of the last sampler unit 22 level be connected in series of sampler unit 22, detect the one or more transformation edges being applied to the input signal of sampler circuit 20.Then, method 100 continues step 102.
As discussed above, The embodiment provides a kind of efficiently sampling and keep or transparent latch function, and not for the neurological susceptibility of metastability issues.Embodiments of the invention also show high power efficiency.The dominating power dissipation of sampler unit 22 is in the Clock Tree of the clock transistor 32,38 driving clock inverter 30.Due to the reason of demultiplexing action (strange/even output stream), the clock of each progress level is divided equally, it reduces the power that every grade of place needs.Meanwhile, the data path of sampler is the consumed power when input signal changes state only, even and if like that also only consumed power between tour.During the stable state of the input signal high or low cycle, energy is not had to be used for sampling capacitance charge/discharge.
Certainly, when not departing from intrinsic propesties of the present invention, the present invention can perform in other modes different from the mode set forth especially herein.Embodiments of the invention should be considered to illustrative and not restrictive in all respects, and all changes fallen in the implication of appended claims and equivalency range are all expected and are included.
Claims (13)
1. a sampler circuit, operation detects one or more transformation edges of the input signal being applied to this sampler circuit, comprising:
Signal inputs;
Sampling clock inputs;
One or more levels be connected in series of sampler unit, each level be connected in series comprises:
Two parallel branchs of the clock inverter be connected in series, each clock inverter operation is applied to the anti-phase of the input of clock inverter with output during a stage of sampling clock and represents, and operates to obtain high impedance in its output during another stage of sampling clock further; And
Clock inverter wherein in each branch alternately carries out clock by sampling clock and anti-phase sampling clock;
Wherein the operation of each sampler unit with in the frequency determined by sampling clock to the signal sampling of input being applied to sampler unit, and export two parallel sample streams at the half place of sample clock frequency, the sample in each stream is from input signal demultiplexing; And
Detector circuit, its operation is to detect one or more transformation edges of the signal being applied to sampler unit input according to the output of the last sampler unit in the level be connected in series of sampler unit.
2. circuit according to claim 1, the first branch of the clock inverter be wherein connected in series comprises three clock inverters and the second branch comprises two clock inverters.
3. circuit according to claim 1, wherein each level be connected in series that continues of sampler unit comprises the sampler unit that quantity is previous stage twice, and carries out clock by the sampling clock of the half of the frequency of the sampling clock of previous stage.
4. circuit according to claim 1, wherein detector circuit operation is resequenced to re-construct the signal of the input being applied to sampler unit with the output of the most rear class to sampler unit.
5. circuit according to claim 1, wherein detector circuit operation detects the one or more transformation edge of signal of the input being applied to sampler unit with the state of the output by checking last sampler unit.
6. circuit according to claim 5, wherein detector circuit comprises or function.
7. circuit according to claim 1, comprises further and is connected to detector circuit and operates the cycle count circuit determining the cycle of input signal.
8. detection is applied to the method at the transformation edge of the input signal of sample circuit, comprising:
Receive the input signal and the sampled clock signal that are applied to sampler circuit;
Utilize one or more levels be connected in series of sampler unit to the input signal sampling being applied to sampler circuit, each level comprises two parallel branchs of the clock inverter be connected in series, each clock inverter operation exports the anti-phase expression being applied to the input of clock inverter during a stage of sampling clock, and operation obtains high impedance in its output during another stage of sampling clock further, wherein the operation of each sampler unit with in the frequency determined by sampling clock to the signal sampling of input being applied to sampler unit, and two parallel sample streams are exported at the half place of sample clock frequency, sample wherein in each stream is from input signal demultiplexing, and
One or more transformation edges of the input signal being applied to sampler circuit are detected according to the output of the last sampler unit in the level be connected in series of sampler unit.
9. method according to claim 8, is wherein included in each sampler unit to the input signal sampling being applied to sampler circuit and is in two parallel branchs comprising the clock inverter be connected in series alternately to the signal sampling being applied to sampler unit input.
10. method according to claim 9, is wherein alternately included in a branch signal sampling and utilizes sampling clock to carry out clock to clock inverter and in another branch, utilize anti-phase sampling clock to carry out clock to clock inverter in two parallel branchs.
11. methods according to claim 8, wherein utilize one or more levels be connected in series of sampler unit to be included in the sampler unit of the twice that each connecting stage place utilizes quantity to be previous stage to the signal sampling being applied to this grade to the input signal sampling being applied to sampler circuit, and utilize the sampling clock of the half of the sample clock frequency of previous stage to carry out clock to sampler unit.
12. methods according to claim 8, the one or more transformation edges wherein detecting according to the output of last sampler unit the input signal being applied to sampler circuit comprise and carry out logic OR to the output of last sampler unit.
13. a kind of four phase sampler device circuit, operation detects one or more transformation edges of the input signal being applied to this four phase samplers device circuit, comprising:
Signal inputs;
Sampling clock inputs;
Clock divider circuit, it is connected to sampling clock input and operation produces in-phase sampling clock and quadrature sample clocks, wherein in-phase sampling clock is I sampling clock, quadrature sample clocks is Q sampling clock, and Q sampling clock and I sampling clock 90 degree of out-phase;
Second group of level be connected in series of the first group of level be connected in series receiving the sampler unit of I sampling clock and the sampler unit receiving Q sampling clock, wherein first and second groups of levels be connected in series of sampler unit are arranged concurrently, and wherein each level be connected in series of sampler unit comprises:
Two parallel branchs of the clock inverter be connected in series, each clock inverter operation is applied to the anti-phase of the input of clock inverter with output during the stage of sampling clock being applied to clock inverter and represents, and operates to obtain high impedance in its output during another stage of sampling clock being applied to clock inverter further; And
Clock inverter wherein in each branch alternately carries out clock by the sampling clock being applied to clock inverter with the backward crossover of the sampling clock being applied to clock inverter;
Wherein the operation of each sampler unit with in the frequency determined by the sampling clock being applied to sampler unit to the signal sampling of input being applied to sampler unit, and export two parallel sample streams at the half place of sample clock frequency, the sample in each stream is from input signal demultiplexing; And
Detector circuit, its operation is to detect one or more transformation edges of the signal being applied to four phase sampler device circuit inputs according to the output of the last sampler unit in the level be connected in series of sampler unit.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
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| US38830210P | 2010-09-30 | 2010-09-30 | |
| US61/388,302 | 2010-09-30 | ||
| US13/198,401 | 2011-08-04 | ||
| US13/198,401 US8548111B2 (en) | 2010-09-30 | 2011-08-04 | Sampler circuit |
| PCT/EP2011/066888 WO2012041915A1 (en) | 2010-09-30 | 2011-09-28 | Sampler circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103141029A CN103141029A (en) | 2013-06-05 |
| CN103141029B true CN103141029B (en) | 2016-01-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180047188.XA Active CN103141029B (en) | 2010-09-30 | 2011-09-28 | Sampler circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8548111B2 (en) |
| EP (1) | EP2622742B1 (en) |
| CN (1) | CN103141029B (en) |
| WO (1) | WO2012041915A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103620965B (en) * | 2012-06-21 | 2016-03-02 | 华为技术有限公司 | Radio frequency receiver |
| CN104702281B (en) | 2015-03-11 | 2017-12-05 | 华为技术有限公司 | A kind of sampling clock generation circuit and analog-digital converter |
| US20180006847A1 (en) * | 2016-06-30 | 2018-01-04 | Wenyan Vivian Jia | Sampler circuit with current injection for pre-amplification |
| CN107085138B (en) * | 2017-04-25 | 2019-05-21 | 电子科技大学 | A kind of high-resolution negative level detection circuit |
| CN111656204B (en) * | 2017-12-12 | 2023-04-14 | 康杜实验室公司 | Adaptive voltage scaling for receivers |
| US11196454B2 (en) * | 2019-10-09 | 2021-12-07 | Beijing Boe Technology Development Co., Ltd. | Digital transceiver driven by synchronous spread spectrum clock signal for data transmission |
| EP4346110A1 (en) * | 2022-09-29 | 2024-04-03 | Nxp B.V. | A transmitter circuit |
| CN116055928B (en) * | 2023-04-03 | 2023-06-02 | 深圳市紫光同创电子有限公司 | Data sampling method, device, electronic equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937020A (en) * | 1995-09-26 | 1999-08-10 | Hitachi, Ltd. | Digital information signal reproducing circuit and digital information system |
| CN1462114A (en) * | 2002-05-30 | 2003-12-17 | Ntt电子株式会社 | Phase-comparision circuit and clock data restoring circuit and transceiver circuit |
| CN1977342A (en) * | 2004-06-25 | 2007-06-06 | 国立科学研究中心 | Fast analog sampler for continuous recording and read-out and digital conversion system |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0738910A (en) * | 1993-07-24 | 1995-02-07 | Nec Corp | Burst control oscillation circuit |
| US5825253A (en) | 1997-07-15 | 1998-10-20 | Qualcomm Incorporated | Phase-locked-loop with noise shaper |
| JP3196725B2 (en) | 1998-06-09 | 2001-08-06 | 日本電気株式会社 | Phase comparison circuit |
| US6690215B2 (en) | 1999-03-17 | 2004-02-10 | Tropian, Inc. | Sigma-delta-based frequency synthesis |
| US7233638B2 (en) * | 2001-01-31 | 2007-06-19 | Rohm Co., Ltd. | Sampling clock generator circuit and data receiver using the same |
| DE10354558B4 (en) | 2003-11-21 | 2006-10-05 | Infineon Technologies Ag | Apparatus for generating a transmit clock signal and a receive clock signal for a transceiver |
| US20050186920A1 (en) | 2004-02-19 | 2005-08-25 | Texas Instruments Incorporated | Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor |
| DE102004009116B3 (en) | 2004-02-25 | 2005-04-28 | Infineon Technologies Ag | Delta-sigma frequency discriminator includes dither circuit for altering clock period of reference clock signal used for sampling register for suppression of modulation interference tones |
| US7015726B1 (en) * | 2004-08-25 | 2006-03-21 | Hewlett-Packard Development Company, L.P. | Edge detector and method |
| DE102005050621B4 (en) | 2005-10-21 | 2011-06-01 | Infineon Technologies Ag | Phase-locked loop and method for operating a phase locked loop |
| US8045670B2 (en) | 2007-06-22 | 2011-10-25 | Texas Instruments Incorporated | Interpolative all-digital phase locked loop |
| KR100955873B1 (en) | 2007-12-20 | 2010-05-04 | 한국과학기술원 | All-Digital Phase Locked Loop For Reduced Spur and Method of Generating an Oscillation Signal Using the Same |
| US20100019800A1 (en) | 2008-07-24 | 2010-01-28 | Mediatek Inc. | Vernier phase error detection method |
| EP2194646B1 (en) | 2008-12-04 | 2013-01-02 | STMicroelectronics Srl | Method of improving noise characteristics of an ADPLL and a relative ADPLL |
| US8837639B2 (en) * | 2010-06-18 | 2014-09-16 | Ati Technologies Ulc | Parallel synchronizing cell with improved mean time between failures |
-
2011
- 2011-08-04 US US13/198,401 patent/US8548111B2/en active Active
- 2011-09-28 EP EP11770073.2A patent/EP2622742B1/en not_active Not-in-force
- 2011-09-28 WO PCT/EP2011/066888 patent/WO2012041915A1/en active Application Filing
- 2011-09-28 CN CN201180047188.XA patent/CN103141029B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937020A (en) * | 1995-09-26 | 1999-08-10 | Hitachi, Ltd. | Digital information signal reproducing circuit and digital information system |
| CN1462114A (en) * | 2002-05-30 | 2003-12-17 | Ntt电子株式会社 | Phase-comparision circuit and clock data restoring circuit and transceiver circuit |
| CN1977342A (en) * | 2004-06-25 | 2007-06-06 | 国立科学研究中心 | Fast analog sampler for continuous recording and read-out and digital conversion system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012041915A1 (en) | 2012-04-05 |
| EP2622742A1 (en) | 2013-08-07 |
| EP2622742B1 (en) | 2014-09-03 |
| CN103141029A (en) | 2013-06-05 |
| US8548111B2 (en) | 2013-10-01 |
| US20120082280A1 (en) | 2012-04-05 |
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